From f12cf9c461320472c391f893f7d74e997ad2fea1 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 2 May 2022 10:08:19 -0600 Subject: [PATCH 1/4] Adding binder enhancemens --- Dockerfile | 3 +++ README.md | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Dockerfile b/Dockerfile index 634106ccb..348c96d80 100644 --- a/Dockerfile +++ b/Dockerfile @@ -35,3 +35,6 @@ RUN npm install @jupyterlab/server-proxy RUN jupyter serverextension enable --py jupyter_server_proxy RUN jupyter labextension install @jupyterlab/server-proxy RUN jupyter lab build + +# Set up terminal +RUN echo 'export PS1="\[$(tput bold)\]\[\033[38;5;220m\]\u\[$(tput sgr0)\]:\[$(tput sgr0)\]\[$(tput bold)\]\[\033[38;5;14m\]\W\[$(tput sgr0)\]\\$\[$(tput sgr0)\]"' >> ~/.bashrc \ No newline at end of file diff --git a/README.md b/README.md index 0135a8bc8..a79e76002 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # Getting Started with OpenFPGA [![linux build](https://github.com/LNIS-Projects/OpenFPGA/workflows/linux_build/badge.svg)](https://github.com/LNIS-Projects/OpenFPGA/actions?query=workflow%3Alinux_build) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master) -[![Binder](https://mybinder.org/badge_logo.svg)](https://mybinder.org/v2/gh/lnis-uofu/OpenFPGA/master?urlpath=lab) +[![Binder](https://mybinder.org/badge_logo.svg)](https://mybinder.org/v2/gh/lnis-uofu/OpenFPGA/master?urlpath=vscode) ## Introduction From 9891e42f7a2fb2ebbf061e757d35f9e035c41071 Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 2 May 2022 10:42:33 -0600 Subject: [PATCH 2/4] Added template task --- openfpga.sh | 15 + .../vpr_blif_template/arch/openfpga_arch.xml | 200 ++++++++++++ .../vpr_blif_template/arch/vpr_arch.xml | 288 ++++++++++++++++++ .../vpr_blif_template/config/task.conf | 38 +++ .../vpr_blif_template/example_script.openfpga | 76 +++++ .../micro_benchmark/and2/and2.act | 3 + .../micro_benchmark/and2/and2.blif | 8 + .../micro_benchmark/and2/and2.eblif | 19 ++ .../micro_benchmark/and2/and2.v | 18 ++ .../and2/and2_frac_lut4_arith.eblif | 19 ++ .../micro_benchmark/and2/and2_verific.blif | 7 + .../micro_benchmark/blinking/blinking.v | 17 ++ .../yosys_vpr_template/arch/openfpga_arch.xml | 200 ++++++++++++ .../yosys_vpr_template/arch/vpr_arch.xml | 288 ++++++++++++++++++ .../yosys_vpr_template/config/task.conf | 36 +++ .../example_script.openfpga | 76 +++++ .../micro_benchmark/and2/and2.act | 3 + .../micro_benchmark/and2/and2.blif | 8 + .../micro_benchmark/and2/and2.eblif | 19 ++ .../micro_benchmark/and2/and2.v | 18 ++ .../and2/and2_frac_lut4_arith.eblif | 19 ++ .../micro_benchmark/and2/and2_verific.blif | 7 + .../micro_benchmark/blinking/blinking.v | 17 ++ 23 files changed, 1399 insertions(+) create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif create mode 100644 openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif create mode 100644 openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v diff --git a/openfpga.sh b/openfpga.sh index a00b8adbd..107ea4406 100755 --- a/openfpga.sh +++ b/openfpga.sh @@ -31,6 +31,21 @@ run-task-with-modelsim () { $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_modelsim.py "$@" } +create-task () { + if [ -z $1 ]; then + echo "requires task name create-task " + return + fi + if [ -d $1 ]; then + echo "Task $1 already exists" + return + fi + flow="yosys_vpr" + if [ -z $1 ]; then flow=$2; fi + mkdir $1 + cp -r $OPENFPGA_PATH/openfpga_flow/tasks/template_tasks/${flow}_template/* $1/ +} + run-task () { $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@" } diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml new file mode 100644 index 000000000..b045a0c39 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/openfpga_arch.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml new file mode 100644 index 000000000..a11010a4f --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/arch/vpr_arch.xml @@ -0,0 +1,288 @@ + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf b/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf new file mode 100644 index 000000000..f3a65f25d --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = None +power_analysis = false +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +# fpga_flow= vpr_blif If input in in .blif format +# fpga_flow= yosys_vpr If input in in .v format +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/example_script.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml + +[BENCHMARKS] +bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga new file mode 100644 index 000000000..a31f81948 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act new file mode 100644 index 000000000..0f77bc6b3 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.act @@ -0,0 +1,3 @@ +a 0.5 0.5 +b 0.5 0.5 +c 0.25 0.25 diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif new file mode 100644 index 000000000..d13bdc564 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.blif @@ -0,0 +1,8 @@ +.model and2 +.inputs a b +.outputs c + +.names a b c +11 1 + +.end diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif new file mode 100644 index 000000000..45d20d1c8 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.eblif @@ -0,0 +1,19 @@ +# This is an artificial microbenchmark +# which is designed to validate the support +# on using bitstream information from the .param +# attribute of hard macro of LUTs +# +.model and2 +.inputs a b +.outputs c + +.subckt adder_lut4 in[1]=a in[0]=b lut4_out[0]=c +.param LUT 1000100010001000 + +.end + +.model adder_lut4 +.inputs in[3] in[2] in[1] in[0] +.outputs lut2_out[1] lut2_out[0] lut4_out[0] +.blackbox +.end diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v new file mode 100644 index 000000000..a23293c58 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2.v @@ -0,0 +1,18 @@ +///////////////////////////////////////// +// Functionality: 2-input AND +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module and2( + a, + b, + c); + +input wire a; +input wire b; +output wire c; + +assign c = a & b; + +endmodule diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif new file mode 100644 index 000000000..1e591e999 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif @@ -0,0 +1,19 @@ +# This is an artificial microbenchmark +# which is designed to validate the support +# on using bitstream information from the .param +# attribute of hard macro of LUTs +# +.model and2 +.inputs a b +.outputs c + +.subckt adder_lut4 in[1]=a in[0]=b lut4_out[0]=c +.param LUT 1000100010001000 + +.end + +.model adder_lut4 +.inputs in[3] in[2] in[1] in[0] cin +.outputs lut4_out[0] cout +.blackbox +.end diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif new file mode 100644 index 000000000..a0448c08b --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/and2/and2_verific.blif @@ -0,0 +1,7 @@ +# Benchmark "and2" written by ABC on Wed Oct 27 18:22:37 2021 +.model and2 +.inputs a b +.outputs c +.names a b c +11 1 +.end diff --git a/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v new file mode 100644 index 000000000..b8587055c --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/vpr_blif_template/micro_benchmark/blinking/blinking.v @@ -0,0 +1,17 @@ +// ------------------------------ +// Design Name: Blinking +// Functionality: 1-bit blinking +// ------------------------------ +module blinking( + clk, + out +); + +input clk; +output out; + + always @(posedge clk) begin + out = ~out; + end + +endmodule diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml new file mode 100644 index 000000000..b045a0c39 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/openfpga_arch.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml new file mode 100644 index 000000000..a11010a4f --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/arch/vpr_arch.xml @@ -0,0 +1,288 @@ + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf new file mode 100644 index 000000000..8d42237db --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/config/task.conf @@ -0,0 +1,36 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +# fpga_flow= vpr_blif If input in in .blif format +# fpga_flow= yosys_vpr If input in in .v format +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:TASK_DIR}/example_script.openfpga +openfpga_arch_file=${PATH:TASK_DIR}/arch/openfpga_arch.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:TASK_DIR}/arch/vpr_arch.xml + +[BENCHMARKS] +bench0=${PATH:TASK_DIR}/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +# end_flow_with_test= +# vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga new file mode 100644 index 000000000..a31f81948 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/example_script.openfpga @@ -0,0 +1,76 @@ +# Run VPR for the 'and' design +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route + +# Read OpenFPGA architecture definition +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} + +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} + +# Annotate the OpenFPGA architecture to VPR data base +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges + +# Check and correct any naming conflicts in the BLIF netlist +check_netlist_naming_conflict --fix --report ./netlist_renaming.xml + +# Apply fix-up to clustering nets based on routing results +pb_pin_fixup --verbose + +# Apply fix-up to Look-Up Table truth tables based on packing results +lut_truth_table_fixup + +# Build the module graph +# - Enabled compression on routing architecture modules +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt + +# Repack the netlist to physical pbs +# This must be done before bitstream generator and testbench generation +# Strongly recommend it is done after all the fix-up have been applied +repack #--verbose + +# Build the bitstream +# - Output the fabric-independent bitstream to a file +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml + +# Build fabric-dependent bitstream +build_fabric_bitstream --verbose + +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.bit --format plain_text + +# Write the Verilog netlist for FPGA fabric +# - Enable the use of explicit port mapping in Verilog netlist +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --print_user_defined_template --verbose + +# Write the Verilog testbench for FPGA fabric +# - We suggest the use of same output directory as fabric Verilog netlists +# - Must specify the reference benchmark file if you want to output any testbenches +# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA +# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase +# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts +write_full_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping --include_signal_init --bitstream fabric_bitstream.bit +write_preconfigured_fabric_wrapper --embed_bitstream iverilog --file ./SRC --explicit_port_mapping +write_preconfigured_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --explicit_port_mapping + +# Write the SDC files for PnR backend +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc + +# Write the SDC to run timing analysis for a mapped FPGA fabric +write_analysis_sdc --file ./SDC_analysis + +# Finish and exit OpenFPGA +exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act new file mode 100644 index 000000000..0f77bc6b3 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.act @@ -0,0 +1,3 @@ +a 0.5 0.5 +b 0.5 0.5 +c 0.25 0.25 diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif new file mode 100644 index 000000000..d13bdc564 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.blif @@ -0,0 +1,8 @@ +.model and2 +.inputs a b +.outputs c + +.names a b c +11 1 + +.end diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif new file mode 100644 index 000000000..45d20d1c8 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.eblif @@ -0,0 +1,19 @@ +# This is an artificial microbenchmark +# which is designed to validate the support +# on using bitstream information from the .param +# attribute of hard macro of LUTs +# +.model and2 +.inputs a b +.outputs c + +.subckt adder_lut4 in[1]=a in[0]=b lut4_out[0]=c +.param LUT 1000100010001000 + +.end + +.model adder_lut4 +.inputs in[3] in[2] in[1] in[0] +.outputs lut2_out[1] lut2_out[0] lut4_out[0] +.blackbox +.end diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v new file mode 100644 index 000000000..a23293c58 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2.v @@ -0,0 +1,18 @@ +///////////////////////////////////////// +// Functionality: 2-input AND +// Author: Xifan Tang +//////////////////////////////////////// +`timescale 1ns / 1ps + +module and2( + a, + b, + c); + +input wire a; +input wire b; +output wire c; + +assign c = a & b; + +endmodule diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif new file mode 100644 index 000000000..1e591e999 --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_frac_lut4_arith.eblif @@ -0,0 +1,19 @@ +# This is an artificial microbenchmark +# which is designed to validate the support +# on using bitstream information from the .param +# attribute of hard macro of LUTs +# +.model and2 +.inputs a b +.outputs c + +.subckt adder_lut4 in[1]=a in[0]=b lut4_out[0]=c +.param LUT 1000100010001000 + +.end + +.model adder_lut4 +.inputs in[3] in[2] in[1] in[0] cin +.outputs lut4_out[0] cout +.blackbox +.end diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif new file mode 100644 index 000000000..a0448c08b --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/and2/and2_verific.blif @@ -0,0 +1,7 @@ +# Benchmark "and2" written by ABC on Wed Oct 27 18:22:37 2021 +.model and2 +.inputs a b +.outputs c +.names a b c +11 1 +.end diff --git a/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v new file mode 100644 index 000000000..b8587055c --- /dev/null +++ b/openfpga_flow/tasks/template_tasks/yosys_vpr_template/micro_benchmark/blinking/blinking.v @@ -0,0 +1,17 @@ +// ------------------------------ +// Design Name: Blinking +// Functionality: 1-bit blinking +// ------------------------------ +module blinking( + clk, + out +); + +input clk; +output out; + + always @(posedge clk) begin + out = ~out; + end + +endmodule From 42567d81788320a78e13cb56ba164402080e693f Mon Sep 17 00:00:00 2001 From: Ganesh Gore Date: Mon, 2 May 2022 12:46:07 -0600 Subject: [PATCH 3/4] Updated docuementation --- Dockerfile | 3 ++- .../getting_started/shell_shortcuts.rst | 20 +++++++++++++++---- openfpga.sh | 2 +- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/Dockerfile b/Dockerfile index 348c96d80..c92f60a4c 100644 --- a/Dockerfile +++ b/Dockerfile @@ -37,4 +37,5 @@ RUN jupyter labextension install @jupyterlab/server-proxy RUN jupyter lab build # Set up terminal -RUN echo 'export PS1="\[$(tput bold)\]\[\033[38;5;220m\]\u\[$(tput sgr0)\]:\[$(tput sgr0)\]\[$(tput bold)\]\[\033[38;5;14m\]\W\[$(tput sgr0)\]\\$\[$(tput sgr0)\]"' >> ~/.bashrc \ No newline at end of file +RUN echo 'export PS1="\[$(tput bold)\]\[\033[38;5;220m\]\u\[$(tput sgr0)\]:\[$(tput sgr0)\]\[$(tput bold)\]\[\033[38;5;14m\]\W\[$(tput sgr0)\]\\$\[$(tput sgr0) \]"' >> ~/.bashrc +RUN mkdir -p .vscode && echo '{"files.associations": {"*.openfpga": "tcl"},"workbench.colorTheme": "Monokai"}' > .vscode/settings.json diff --git a/docs/source/tutorials/getting_started/shell_shortcuts.rst b/docs/source/tutorials/getting_started/shell_shortcuts.rst index 8671d9208..aad34c812 100644 --- a/docs/source/tutorials/getting_started/shell_shortcuts.rst +++ b/docs/source/tutorials/getting_started/shell_shortcuts.rst @@ -1,19 +1,19 @@ OpenFPGA shortcuts ------------------ -OpenFPGA provides bash/zsh shell-based shortcuts to perform all essential functions and navigating through the directories. Go to the OpenFPGA directory and source ``openfpga.sh`` +OpenFPGA provides `bash`/`zsh` shell-based shortcuts to perform all essential functions and navigate through the directories. Go to the OpenFPGA directory and source ``openfpga.sh`` .. code-block:: bash cd ${OPENFPGA_PATH} && source openfpga.sh .. note:: - The OpenFPGA shortcuts are designed to work with only bash based shells. e.g. bash/zsh/fish etc. + The OpenFPGA shortcut works with only a bash-like shell. e.g., `bash`/`zsh`/`fish,` etc. Shortcut Commands ^^^^^^^^^^^^^^^^^ -Once the ``openfpga.sh`` script is sourced, you can run any of the following commands directly in the terminal. +Once the ``openfpga.sh`` script is sourced, you can run any following commands directly in the terminal. .. option:: list-tasks @@ -22,7 +22,19 @@ Once the ``openfpga.sh`` script is sourced, you can run any of the following com .. option:: run-task **kwarags - This command runs the specified task listed from the ``list-task`` command or from the existing directory. The command name is relative to the ``TASK_DIRECTORY``. Users can provide any additional arguments which are listed `here <_openfpga_task_args>`_ to this command. + This command runs the specified task. The script will first look for the task in the current working directory. + If it is not in the current directory, it will then search in ``TASK_DIRECTORY`` (relative to task directory). + You can also provide a path as a task_name, for example, ``run-task basic_tests/generate_fabric`` + The valid arguments listed here <_openfpga_task_args>`_, you can also run `run-task run-task` to get the list of command-line arguments. + + +.. option:: create-task