diff --git a/.github/workflows/basic_reg_test.sh b/.github/workflows/basic_reg_test.sh new file mode 100755 index 000000000..c988c9a21 --- /dev/null +++ b/.github/workflows/basic_reg_test.sh @@ -0,0 +1,107 @@ +#!/bin/bash + +set -e + +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "Basic regression tests"; + +echo -e "Testing configuration chain of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs + +echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs + +echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs + +echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs + +echo -e "Testing fixed device layout and routing channel width"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs + +echo -e "Testing fabric Verilog generation only"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs + +echo -e "Testing Verilog testbench generation only"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs + +echo -e "Testing separated Verilog fabric netlists and testbench locations"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs + +echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs + +echo -e "Testing Secured FPGA fabrics"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs + + +echo -e "Testing K4 series FPGA"; +echo -e "Testing K4N4 with facturable LUTs"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs +echo -e "Testing K4N4 with hard adders"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs +echo -e "Testing K4N4 without local routing architecture"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs +echo -e "Testing K4N4 with block RAM"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs +echo -e "Testing K4N4 with multiple lengths of routing segments"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs +echo -e "Testing K4N4 with 32-bit fracturable multiplier"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs +echo -e "Testing K4N5 with pattern based local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs + +echo -e "Testing different tile organizations"; +echo -e "Testing tiles with pins only on top and left sides"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs +echo -e "Testing tiles with pins only on top and right sides"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs +echo -e "Testing tiles with pins only on bottom and right sides"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs + +echo -e "Testing global port definition from tiles"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 000000000..2a698695e --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,201 @@ +name: linux_build + +# Run CI on +# - each push +# - each pull request +# - scheduled weekly +on: + push: + pull_request: + schedule: + - cron: '0 0 * * 0 ' # weekly + +# Environment variables +env: + # Customize the CMake build type here (Release, Debug, RelWithDebInfo, etc.) + BUILD_TYPE: Release + MAKEFLAGS: "-j8" + +# Multiple job to tests +jobs: + # Test the compilation compatibility + linux_build: + name: ${{ matrix.config.name }} + runs-on: ${{ matrix.config.os }} + + # Branch on different OS and settings + strategy: + fail-fast: false + matrix: + config: + - { + name: "Build Compatibility: GCC-5 (Ubuntu 18.04)", + artifact: "OpenFPGA-ubuntu-18.04-gcc5-build.7z", + os: ubuntu-18.04, + cc: "gcc-5", cxx: "g++-5" + } + + - { + name: "Build Compatibility: GCC-6 (Ubuntu 18.04)", + artifact: "OpenFPGA-ubuntu-18.04-gcc6-build.7z", + os: ubuntu-18.04, + cc: "gcc-6", cxx: "g++-6" + } + + - { + name: "Build Compatibility: GCC-7 (Ubuntu 18.04)", + artifact: "OpenFPGA-ubuntu-18.04-gcc7-build.7z", + os: ubuntu-18.04, + cc: "gcc-7", cxx: "g++-7" + } + + - { + name: "Build Compatibility: GCC-8 (Ubuntu 18.04)", + artifact: "OpenFPGA-ubuntu-18.04-gcc8-build.7z", + os: ubuntu-18.04, + cc: "gcc-8", cxx: "g++-8" + } + + - { + name: "Build Compatibility: GCC-9 (Ubuntu 18.04)", + artifact: "OpenFPGA-ubuntu-18.04-gcc9-build.7z", + os: ubuntu-18.04, + cc: "gcc-9", cxx: "g++-9" + } + + - { + name: "Build Compatibility: Clang-6 (Ubuntu 18.04)", + artifact: "OpenFPGA-ubuntu-18.04-clang6-build.7z", + os: ubuntu-18.04, + cc: "clang-6.0", cxx: "clang++-6.0" + } + + - { + name: "Build Compatibility: Clang-8 (Ubuntu 18.04)", + artifact: "OpenFPGA-ubuntu-18.04-clang8-build.7z", + os: ubuntu-18.04, + cc: "clang-8", cxx: "clang++-8" + } + + - { + name: "Basic Regression Tests: GCC-8 (Ubuntu 18.04)", + artifact: "OpenFPGA-basic-tests-ubuntu-18.04-gcc8-build.7z", + os: ubuntu-18.04, + cc: "gcc-8", cxx: "g++-8", + reg_script: "basic_reg_test.sh" + } + + - { + name: "FPGA-Verilog Regression Tests: GCC-8 (Ubuntu 18.04)", + artifact: "OpenFPGA-fpga-verilog-tests-ubuntu-18.04-gcc8-build.7z", + os: ubuntu-18.04, + cc: "gcc-8", cxx: "g++-8", + reg_script: "fpga_verilog_reg_test.sh" + } + + - { + name: "FPGA-Bitstream Regression Tests: GCC-8 (Ubuntu 18.04)", + artifact: "OpenFPGA-fpga-bitstream-tests-ubuntu-18.04-gcc8-build.7z", + os: ubuntu-18.04, + cc: "gcc-8", cxx: "g++-8", + reg_script: "fpga_bitstream_reg_test.sh" + } + + - { + name: "FPGA-SDC Regression Tests: GCC-8 (Ubuntu 18.04)", + artifact: "OpenFPGA-fpga-sdc-tests-ubuntu-18.04-gcc8-build.7z", + os: ubuntu-18.04, + cc: "gcc-8", cxx: "g++-8", + reg_script: "fpga_sdc_reg_test.sh" + } + + - { + name: "FPGA-SPICE Regression Tests: GCC-8 (Ubuntu 18.04)", + artifact: "OpenFPGA-fpga-spice-tests-ubuntu-18.04-gcc8-build.7z", + os: ubuntu-18.04, + cc: "gcc-8", cxx: "g++-8", + reg_script: "fpga_spice_reg_test.sh" + } + + + # Define the steps to run the build job + steps: + - name: Checkout OpenFPGA repo + uses: actions/checkout@v2 + + - name: Install dependency + run: source ./.github/workflows/install_dependency.sh + + - name: Checkout CMake version + run: cmake --version + + - name: Checkout iVerilog version + run: | + iverilog -V + vvp -V + + - name: Prepare ccache timestamp + id: ccache_cache_timestamp + shell: cmake -P {0} + run: | + string(TIMESTAMP current_date "%Y-%m-%d-%H;%M;%S" UTC) + message("::set-output name=timestamp::${current_date}") + + - name: Create CMake build environment + # Some projects don't allow in-source building, so create a separate build directory + # We'll use this as our working directory for all subsequent commands + run: cmake -E make_directory ${{runner.workspace}}/build + + - name: ccache cache files + uses: actions/cache@v2 + with: + path: ${{runner.workspace}}/.ccache + key: ${{ matrix.config.name }}-ccache-${{ steps.ccache_cache_timestamp.outputs.timestamp }} + restore-keys: | + ${{ matrix.config.name }}-ccache- + + # Set up the paths for ccache and control the size under 400MB + - name: Configure ccache + shell: cmake -P {0} + run: | + file(TO_CMAKE_PATH ${{runner.workspace}} ccache_basedir) + set(ENV{CCACHE_BASEDIR} "${ccache_basedir}") + set(ENV{CCACHE_DIR} "${ccache_basedir}/.ccache") + set(ENV{CCACHE_COMPRESS} "true") + set(ENV{CCACHE_COMPRESSLEVEL} "6") + set(ENV{CCACHE_MAXSIZE} "400M") + + execute_process(COMMAND ccache -p) + execute_process(COMMAND ccache -z) + + - name: Configure CMake + # Use a bash shell so we can use the same syntax for environment variable + # access regardless of the host operating system + shell: bash + working-directory: ${{runner.workspace}}/build + # Note the current convention is to use the -S and -B options here to specify source + # and build directories, but this is only available with CMake 3.13 and higher. + # The CMake binaries on the Github Actions machines are (as of this writing) 3.12 + run: | + export CC=${{ matrix.config.cc }} + export CXX=${{ matrix.config.cxx }} + cmake $GITHUB_WORKSPACE -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DCMAKE_C_COMPILER_LAUNCHER=ccache -DCMAKE_CXX_COMPILER_LAUNCHER=ccache + + - name: Build + working-directory: ${{runner.workspace}}/build + shell: bash + # Execute the build. You can specify a specific target with "--target " + run: | + cmake --build . --config $BUILD_TYPE + + # Check the cache size and see if it is over the limit + - name: Check ccache size + shell: cmake -P {0} + run: | + execute_process(COMMAND ccache -s) + + - name: ${{matrix.config.name}} + if: contains(matrix.config.name, 'Regression Test') + shell: bash + # Execute the test. + run: source ./.github/workflows/${{matrix.config.reg_script}} diff --git a/.github/workflows/fpga_bitstream_reg_test.sh b/.github/workflows/fpga_bitstream_reg_test.sh new file mode 100755 index 000000000..ce3693555 --- /dev/null +++ b/.github/workflows/fpga_bitstream_reg_test.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +set -e + +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "FPGA-Bitstream regression tests"; + +echo -e "Testing bitstream generation for an auto-sized device"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs + + +echo -e "Testing bitstream generation for an 48x48 FPGA device"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs + +echo -e "Testing bitstream generation for an 96x96 FPGA device"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs + +echo -e "Testing loading architecture bitstream from an external file"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs diff --git a/.github/workflows/fpga_sdc_reg_test.sh b/.github/workflows/fpga_sdc_reg_test.sh new file mode 100755 index 000000000..203106433 --- /dev/null +++ b/.github/workflows/fpga_sdc_reg_test.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e + +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "FPGA-SDC regression tests"; + +echo -e "Testing SDC generation with time units"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs diff --git a/.github/workflows/fpga_spice_reg_test.sh b/.github/workflows/fpga_spice_reg_test.sh new file mode 100755 index 000000000..defe17ec9 --- /dev/null +++ b/.github/workflows/fpga_spice_reg_test.sh @@ -0,0 +1,11 @@ +#!/bin/bash + +set -e + +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "FPGA-SPICE regression tests"; + +echo -e "Testing FPGA-SPICE with netlist generation"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs diff --git a/.github/workflows/fpga_verilog_reg_test.sh b/.github/workflows/fpga_verilog_reg_test.sh new file mode 100755 index 000000000..7fcf75b3e --- /dev/null +++ b/.github/workflows/fpga_verilog_reg_test.sh @@ -0,0 +1,115 @@ +#!/bin/bash + +set -e + +############################################### +# OpenFPGA Shell with VPR8 +############################################## +echo -e "FPGA-Verilog Feature Tests"; + +echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs + +echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs + +echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs + +echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs + +echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs + +echo -e "Testing Verilog generation with VPR's untileable routing architecture "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs + +echo -e "Testing Verilog generation with hard adder chain in CLBs "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs + +echo -e "Testing Verilog generation with 16k block RAMs "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs + +echo -e "Testing Verilog generation with 16k block RAMs spanning two columns "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs + +echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs + +echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs + +echo -e "Testing Verilog generation with embedded I/Os for an FPGA "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs + +echo -e "Testing Verilog generation with SoC I/Os for an FPGA "; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs + +echo -e "Testing Verilog generation with adder chain across an FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs + +echo -e "Testing Verilog generation with shift register chain across an FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs + +echo -e "Testing Verilog generation with scan chain across an FPGA"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers without buffers"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers with input buffers only"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers with output buffers only"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers with constant gnd input"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs + +echo -e "Testing Verilog generation with routing multiplexers without constant inputs"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs + +echo -e "Testing Verilog generation with behavioral description"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs + +echo -e "Testing implicit Verilog generation"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs + +echo -e "Testing Verilog generation with flatten routing modules"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs + +echo -e "Testing Verilog generation with duplicated grid output pins"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs + +echo -e "Testing Verilog generation with spy output pads"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs + + +echo -e "Testing Power-gating designs"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug + +echo -e "Testing Depopulated crossbar in local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs + +echo -e "Testing Fully connected output crossbar in local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs + +echo -e "Testing through channels in tileable routing"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs + +# Verify MCNC big20 benchmark suite with ModelSim +# Please make sure you have ModelSim installed in the environment +# Otherwise, it will fail +#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20 +#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim diff --git a/.github/workflows/install_dependency.sh b/.github/workflows/install_dependency.sh new file mode 100644 index 000000000..0e663ef26 --- /dev/null +++ b/.github/workflows/install_dependency.sh @@ -0,0 +1,48 @@ +# Install all the dependency for OpenFPGA in Ubuntu-18.04 +sudo apt-get update +sudo apt-get install autoconf +sudo apt-get install automake +sudo apt-get install bash +sudo apt-get install bison +sudo apt-get install build-essential +sudo apt-get install cmake +sudo apt-get install ccache +sudo apt-get install ctags +sudo apt-get install curl +sudo apt-get install doxygen +sudo apt-get install flex +sudo apt-get install fontconfig +sudo apt-get install gdb +sudo apt-get install git +sudo apt-get install gperf +sudo apt-get install iverilog +sudo apt-get install libcairo2-dev +sudo apt-get install libevent-dev +sudo apt-get install libfontconfig1-dev +sudo apt-get install liblist-moreutils-perl +sudo apt-get install libncurses5-dev +sudo apt-get install libx11-dev +sudo apt-get install libxft-dev +sudo apt-get install libxml++2.6-dev +sudo apt-get install perl +sudo apt-get install python +sudo apt-get install python-lxml +sudo apt-get install texinfo +sudo apt-get install time +sudo apt-get install valgrind +sudo apt-get install zip +sudo apt-get install qt5-default +sudo apt-get install clang-format-7 +# Add all the supported compilers +sudo apt-get install g++-5 +sudo apt-get install gcc-5 +sudo apt-get install g++-6 +sudo apt-get install gcc-6 +sudo apt-get install g++-7 +sudo apt-get install gcc-7 +sudo apt-get install g++-8 +sudo apt-get install gcc-8 +sudo apt-get install g++-9 +sudo apt-get install gcc-9 +sudo apt-get install clang-6.0 +sudo apt-get install clang-8 diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 207953644..c077b66fd 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -5,108 +5,6 @@ set -e start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd ${TRAVIS_BUILD_DIR} -############################################### -# OpenFPGA Shell with VPR8 -############################################## -echo -e "Basic regression tests"; - -echo -e "Testing configuration chain of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs - -echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_configuration_frame --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs - -echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/multi_region_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_multi_region_memory_bank --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs - -echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs - -echo -e "Testing fixed device layout and routing channel width"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs - -echo -e "Testing fabric Verilog generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs - -echo -e "Testing Verilog testbench generation only"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs - -echo -e "Testing separated Verilog fabric netlists and testbench locations"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/custom_fabric_netlist_location --debug --show_thread_logs - -echo -e "Testing user-defined simulation settings: clock frequency and number of cycles"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs - -echo -e "Testing Secured FPGA fabrics"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_multi_region_vanilla_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/generate_random_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs - - -echo -e "Testing K4 series FPGA"; -echo -e "Testing K4N4 with facturable LUTs"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs -echo -e "Testing K4N4 with hard adders"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs -echo -e "Testing K4N4 without local routing architecture"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs -echo -e "Testing K4N4 with block RAM"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs -echo -e "Testing K4N4 with multiple lengths of routing segments"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs -echo -e "Testing K4N4 with 32-bit fracturable multiplier"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs -echo -e "Testing K4N5 with pattern based local routing"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs - -echo -e "Testing different tile organizations"; -echo -e "Testing tiles with pins only on top and left sides"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_left_custom_pins --debug --show_thread_logs -echo -e "Testing tiles with pins only on top and right sides"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/top_right_custom_pins --debug --show_thread_logs -echo -e "Testing tiles with pins only on bottom and right sides"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bottom_right_custom_pins --debug --show_thread_logs - -echo -e "Testing global port definition from tiles"; -python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs +source .github/workflows/basic_reg_test.sh end_section "OpenFPGA.TaskTun" diff --git a/.travis/fpga_bitstream_reg_test.sh b/.travis/fpga_bitstream_reg_test.sh index 8b9b6c0f4..4d7c27ed6 100755 --- a/.travis/fpga_bitstream_reg_test.sh +++ b/.travis/fpga_bitstream_reg_test.sh @@ -5,22 +5,6 @@ set -e start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd ${TRAVIS_BUILD_DIR} -############################################### -# OpenFPGA Shell with VPR8 -############################################## -echo -e "FPGA-Bitstream regression tests"; - -echo -e "Testing bitstream generation for an auto-sized device"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs - - -echo -e "Testing bitstream generation for an 48x48 FPGA device"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs - -echo -e "Testing bitstream generation for an 96x96 FPGA device"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs - -echo -e "Testing loading architecture bitstream from an external file"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs +source .github/workflows/fpga_bitstream_reg_test.sh end_section "OpenFPGA.TaskTun" diff --git a/.travis/fpga_sdc_reg_test.sh b/.travis/fpga_sdc_reg_test.sh index 70dd34809..bd0e5ae1f 100755 --- a/.travis/fpga_sdc_reg_test.sh +++ b/.travis/fpga_sdc_reg_test.sh @@ -5,12 +5,6 @@ set -e start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd ${TRAVIS_BUILD_DIR} -############################################### -# OpenFPGA Shell with VPR8 -############################################## -echo -e "FPGA-SDC regression tests"; - -echo -e "Testing SDC generation with time units"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs +source .github/workflows/fpga_sdc_reg_test.sh end_section "OpenFPGA.TaskTun" diff --git a/.travis/fpga_spice_reg_test.sh b/.travis/fpga_spice_reg_test.sh index 8856d3ec8..bb2a9afe6 100755 --- a/.travis/fpga_spice_reg_test.sh +++ b/.travis/fpga_spice_reg_test.sh @@ -5,12 +5,6 @@ set -e start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd ${TRAVIS_BUILD_DIR} -############################################### -# OpenFPGA Shell with VPR8 -############################################## -echo -e "FPGA-SPICE regression tests"; - -echo -e "Testing FPGA-SPICE with netlist generation"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs +source .github/workflows/fpga_spice_reg_test.sh end_section "OpenFPGA.TaskTun" diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index f06ae29fe..34a5c9d55 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -5,116 +5,6 @@ set -e start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}" cd ${TRAVIS_BUILD_DIR} -############################################### -# OpenFPGA Shell with VPR8 -############################################## -echo -e "FPGA-Verilog Feature Tests"; - -echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs - -echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs - -echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 using AND gate to switch modes"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4_and_switch --debug --show_thread_logs - -echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs - -echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs - -echo -e "Testing Verilog generation with VPR's untileable routing architecture "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs - -echo -e "Testing Verilog generation with hard adder chain in CLBs "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs - -echo -e "Testing Verilog generation with 16k block RAMs "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs - -echo -e "Testing Verilog generation with 16k block RAMs spanning two columns "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs - -echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs - -echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs - -echo -e "Testing Verilog generation with embedded I/Os for an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/embedded_io --debug --show_thread_logs - -echo -e "Testing Verilog generation with SoC I/Os for an FPGA "; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/soc_io --debug --show_thread_logs - -echo -e "Testing Verilog generation with adder chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs - -echo -e "Testing Verilog generation with shift register chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs - -echo -e "Testing Verilog generation with scan chain across an FPGA"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers without buffers"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers with input buffers only"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers with output buffers only"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers with constant gnd input"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs - -echo -e "Testing Verilog generation with routing multiplexers without constant inputs"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs - -echo -e "Testing Verilog generation with behavioral description"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs - -echo -e "Testing implicit Verilog generation"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs - -echo -e "Testing Verilog generation with flatten routing modules"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs - -echo -e "Testing Verilog generation with duplicated grid output pins"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs - -echo -e "Testing Verilog generation with spy output pads"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs - - -echo -e "Testing Power-gating designs"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug - -echo -e "Testing Depopulated crossbar in local routing"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs - -echo -e "Testing Fully connected output crossbar in local routing"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs - -echo -e "Testing through channels in tileable routing"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs - -# Verify MCNC big20 benchmark suite with ModelSim -# Please make sure you have ModelSim installed in the environment -# Otherwise, it will fail -#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20 -#python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim +source .github/workflows/fpga_verilog_reg_test.sh end_section "OpenFPGA.TaskTun" diff --git a/README.md b/README.md index 5a8a9e960..c5e81b04b 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,5 @@ # Getting Started with OpenFPGA +![Github Actions Status](https://github.com/LNIS-Projects/OpenFPGA/workflows/OpenFPGA%20Tests/badge.svg) [![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.com/LNIS-Projects/OpenFPGA) [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)