From 8a5741b1ae761fe15cc590d65fc05168828f1d0c Mon Sep 17 00:00:00 2001
From: Lalit Sharma <lsharma@quicklogic.com>
Date: Fri, 8 Jan 2021 07:08:24 -0800
Subject: [PATCH] Bumping yosys submodule with the latest changes done in yosys
 repo related to OpenFPGA flow

---
 openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys | 2 +-
 yosys                                           | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
index 314a32324..cccd220b9 100644
--- a/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
+++ b/openfpga_flow/misc/quicklogic_yosys_flow_ap3.ys
@@ -2,5 +2,5 @@
 # Read verilog files
 ${READ_VERILOG_FILE}
 
-synth_quicklogic -blif ${OUTPUT_BLIF} -family ap3 -vpr -openfpga -top ${TOP_MODULE}
+synth_quicklogic -blif ${OUTPUT_BLIF} -openfpga -top ${TOP_MODULE}
 
diff --git a/yosys b/yosys
index aec2c4144..a0606e09f 160000
--- a/yosys
+++ b/yosys
@@ -1 +1 @@
-Subproject commit aec2c41441bffa981092095d25655e80dae6ef06
+Subproject commit a0606e09f57df456ba9bcfc6a7cf7b64d814b8e4