From e863333f2289c71e94eb37b106fc8d2b73e0cba7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 13 Nov 2024 19:01:55 -0800 Subject: [PATCH] [test] relax route W to bypass VPR bugs --- .../config/task.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf index 64ee22a50..13b05e715 100644 --- a/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_on_lut_pb_pin_fixup_msb/config/task.conf @@ -53,6 +53,8 @@ bench1_openfpga_vpr_route_chan_width=44 bench2_top = rst_and_clk_on_lut bench2_openfpga_pin_constraints_file = ${PATH:TASK_DIR}/config/pin_constraints_rst_and_clk.xml +# Triggered a bug in VPR, when route_chan_width=40, it failed +bench2_openfpga_vpr_route_chan_width=44 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test=