diff --git a/libopenfpga/libpcf/CMakeLists.txt b/libopenfpga/libpcf/CMakeLists.txt
index be7f12ffd..49314b259 100644
--- a/libopenfpga/libpcf/CMakeLists.txt
+++ b/libopenfpga/libpcf/CMakeLists.txt
@@ -2,6 +2,24 @@ cmake_minimum_required(VERSION 3.9)
 
 project("libpcf")
 
+# For CSV reader
+if(CSV_CXX_STANDARD)
+	set(CMAKE_CXX_STANDARD ${CSV_CXX_STANDARD})
+else()
+	set(CMAKE_CXX_STANDARD 17)
+endif(CSV_CXX_STANDARD)
+
+option(BUILD_PYTHON "Build Python Binding" OFF)
+
+message("Building CSV library using C++${CMAKE_CXX_STANDARD}")
+
+# Defines CSV_HAS_CXX17 in compatibility.hpp
+if (CMAKE_VERSION VERSION_LESS "3.12.0")
+	add_definitions(-DCMAKE_CXX_STANDARD=${CMAKE_CXX_STANDARD})
+else()
+	add_compile_definitions(CMAKE_CXX_STANDARD=${CMAKE_CXX_STANDARD})
+endif()
+
 file(GLOB_RECURSE EXEC_SOURCES test/*.cpp)
 file(GLOB_RECURSE LIB_SOURCES src/*/*.cpp)
 file(GLOB_RECURSE LIB_HEADERS src/*/*.h)
diff --git a/libopenfpga/libpcf/src/io/read_csv_io_pin_table.cpp b/libopenfpga/libpcf/src/io/read_csv_io_pin_table.cpp
index 5911e8b1f..3ed2de01e 100644
--- a/libopenfpga/libpcf/src/io/read_csv_io_pin_table.cpp
+++ b/libopenfpga/libpcf/src/io/read_csv_io_pin_table.cpp
@@ -8,6 +8,7 @@
 /* Headers from vtr util library */
 #include "vtr_assert.h"
 #include "vtr_time.h"
+#include "vtr_log.h"
 
 /* Headers from libopenfpga util library */
 #include "openfpga_port_parser.h"
@@ -27,6 +28,44 @@ IoPinTable read_csv_io_pin_table(const char* fname) {
 
   IoPinTable io_pin_table;
 
+  csv::CSVFormat format;
+  format.delimiter(',');
+  format.quote('~');
+  format.trim({'\t', ' '});
+  format.header_row(0);
+
+  csv::CSVReader reader(fname, format);
+
+  /* TODO: Move this to constants */
+  std::map<std::string, e_side> side_str_map { {"TOP", TOP}, {"RIGHT", RIGHT}, {"LEFT", LEFT}, {"BOTTOM", BOTTOM} };
+
+  for (csv::CSVRow& row : reader) {
+    IoPinTableId pin_id = io_pin_table.create_pin();
+    /* Fill pin-level information */
+    PortParser internal_pin_parser(row["port_name"].get<std::string>());
+    io_pin_table.set_internal_pin(pin_id, internal_pin_parser.port());
+
+    PortParser external_pin_parser(row["mapped_pin"].get<std::string>());
+    io_pin_table.set_external_pin(pin_id, external_pin_parser.port());
+
+    std::string pin_side_str = row["orientation"].get<std::string>();
+    if (side_str_map.end() == side_str_map.find(pin_side_str)) {
+      VTR_LOG("Invalid side defintion! Expect [TOP|RIGHT|LEFT|BOTTOM]\n");
+      exit(1);
+    } else {
+      io_pin_table.set_pin_side(pin_id, side_str_map[pin_side_str]);
+    }
+
+    /*This is not general purpose: we should have an explicit attribute in the csv file to decalare direction */
+    if (internal_pin_parser.port().get_name().find("A2F") != std::string::npos) {
+      io_pin_table.set_pin_direction(pin_id, IoPinTable::INPUT);
+    } else if (internal_pin_parser.port().get_name().find("F2A") != std::string::npos) {
+      io_pin_table.set_pin_direction(pin_id, IoPinTable::OUTPUT);
+    } else {
+      VTR_LOG("Invalid direction defintion! Expect [A2F|F2A] in the pin name\n");
+      exit(1);
+    }
+  }
 
   return io_pin_table;
 }
diff --git a/libopenfpga/libpinconstrain/data/pinmap_k4_N4_tileable_40nm.csv b/libopenfpga/libpinconstrain/data/pinmap_k4_N4_tileable_40nm.csv
index 2d9fcb6c3..edb8072dc 100644
--- a/libopenfpga/libpinconstrain/data/pinmap_k4_N4_tileable_40nm.csv
+++ b/libopenfpga/libpinconstrain/data/pinmap_k4_N4_tileable_40nm.csv
@@ -14,4 +14,4 @@ RIGHT,,,,gfpga_pad_IO_F2A[40],pad_fpga_io[5],,,
 BOTTOM,,,,gfpga_pad_IO_A2F[64],pad_fpga_io[6],,,
 BOTTOM,,,,gfpga_pad_IO_F2A[64],pad_fpga_io[6],,,
 LEFT,,,,gfpga_pad_IO_F2A[127],pad_fpga_io[7],,,
-LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,,
\ No newline at end of file
+LEFT,,,,gfpga_pad_IO_A2F[127],pad_fpga_io[7],,,