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Update regession tasks

This commit is contained in:
Ganesh Gore 2022-05-05 01:46:19 -06:00
parent f046224e5f
commit e845b62322
4 changed files with 22 additions and 16 deletions
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4
openfpga_flow/openfpga_shell_scripts/iwls_benchmark_example_script.openfpga
View File

@ -45,7 +45,9 @@ repack #--verbose
# Build the bitstream # Build the bitstream
# - Output the fabric-independent bitstream to a file # - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # # Skipped becasue it takes long time to run for bigger fabric
# --write_file fabric_independent_bitstream.xml
build_architecture_bitstream --verbose
# Build fabric-dependent bitstream # Build fabric-dependent bitstream
build_fabric_bitstream --verbose build_fabric_bitstream --verbose

4
openfpga_flow/openfpga_shell_scripts/quicklogic_flow_example_script.openfpga
View File

@ -38,7 +38,9 @@ repack #--verbose
# Build the bitstream # Build the bitstream
# - Output the fabric-independent bitstream to a file # - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Skipped becasue it takes long time to run for bigger fabric
# --write_file fabric_independent_bitstream.xml
build_architecture_bitstream --verbose
# Build fabric-dependent bitstream # Build fabric-dependent bitstream
build_fabric_bitstream --verbose build_fabric_bitstream --verbose

4
openfpga_flow/openfpga_shell_scripts/vtr_benchmark_example_script.openfpga
View File

@ -45,7 +45,9 @@ repack #--verbose
# Build the bitstream # Build the bitstream
# - Output the fabric-independent bitstream to a file # - Output the fabric-independent bitstream to a file
build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Skipped becasue it takes long time to run for bigger fabric
# --write_file fabric_independent_bitstream.xml
build_architecture_bitstream --verbose
# Build fabric-dependent bitstream # Build fabric-dependent bitstream
build_fabric_bitstream --verbose build_fabric_bitstream --verbose

26
openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf
View File

@ -30,7 +30,9 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_ch
# Official benchmarks from VTR benchmark release # Official benchmarks from VTR benchmark release
# Comment out due to high runtime # Comment out due to high runtime
#bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/bgm.v #bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/bgm.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v
# Failed due to an unknown error in VPR netlist parser # Failed due to an unknown error in VPR netlist parser
#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/boundtop.v
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
@ -48,11 +50,9 @@ bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkSMAdapter
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/or1200.v bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/or1200.v
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/raygentop.v
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/sha.v
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision0.v bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision1.v
# Comment out due to high runtime # Comment out due to high runtime
#bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision2.v
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/stereovision3.v
# Additional benchmarks after VTR benchmark release # Additional benchmarks after VTR benchmark release
#bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/arm_core.v
#bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/spree.v #bench20=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/spree.v
@ -68,10 +68,12 @@ bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36
bench_read_verilog_options_common = -nolatches bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_flow.ys
# Benchmark ch_intrinsics # Benchmark ch_intrinsics
bench0_top = bgm # bench0_top = bgm
bench1_top = RLE_BlobMerging bench0_top = sv_chip0_hierarchy_no_mem
bench2_top = paj_boundtop_hierarchy_no_mem bench1_top = sv_chip1_hierarchy_no_mem
bench3_top = memset bench2_top = sv_chip3_hierarchy_no_mem
# bench2_top = paj_boundtop_hierarchy_no_mem
# bench3_top = memset
bench4_top = diffeq_paj_convert bench4_top = diffeq_paj_convert
bench5_top = diffeq_f_systemC bench5_top = diffeq_f_systemC
bench6_top = LU8PEEng bench6_top = LU8PEEng
@ -83,14 +85,12 @@ bench11_top = mkSMAdapter4B
bench12_top = or1200_flat bench12_top = or1200_flat
bench13_top = paj_raygentop_hierarchy_no_mem bench13_top = paj_raygentop_hierarchy_no_mem
bench14_top = sha1 bench14_top = sha1
bench15_top = sv_chip0_hierarchy_no_mem bench15_top = RLE_BlobMerging
bench16_top = sv_chip1_hierarchy_no_mem
bench17_top = sv_chip2_hierarchy_no_mem bench17_top = sv_chip2_hierarchy_no_mem
bench18_top = sv_chip3_hierarchy_no_mem
bench19_top = arm_core bench19_top = arm_core
bench20_top = system bench20_top = system
bench21_top = LU64PEEng bench21_top = LU64PEEng
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
#end_flow_with_test= # end_flow_with_test=
#vpr_fpga_verilog_formal_verification_top_netlist= # vpr_fpga_verilog_formal_verification_top_netlist=