riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

plug in netlist manager and now the include_netlist appears in one unique file

This commit is contained in:
tangxifan 2020-04-23 20:42:11 -06:00
parent 87b17fc25f
commit e811f8bb21
28 changed files with 184 additions and 76 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
openfpga/src/base/netlist_manager.cpp
View File

@ -74,6 +74,17 @@ NetlistId NetlistManager::find_module_netlist(const ModuleId& module) const {
return module_netlist_map_.at(module);
}
std::vector<NetlistId> NetlistManager::netlists_by_type(const NetlistManager::e_netlist_type& netlist_type) const {
std::vector<NetlistId> nlists;
for (const NetlistId& nlist_id : netlist_ids_) {
if (netlist_type == netlist_types_[nlist_id]) {
nlists.push_back(nlist_id);
}
}
return nlists;
}
/* Find all the preprocessing flags that are included in a netlist */
std::vector<std::string> NetlistManager::netlist_preprocessing_flags(const NetlistId& netlist) const {

2
openfpga/src/base/netlist_manager.h
View File

@ -58,6 +58,8 @@ class NetlistManager {
std::string netlist_name(const NetlistId& netlist) const;
/* Find a netlist by its name */
NetlistId find_netlist(const std::string& netlist_name) const;
/* Find all the netlist in a given type */
std::vector<NetlistId> netlists_by_type(const e_netlist_type& netlist_type) const;
/* Get the type of a netlist */
e_netlist_type netlist_type(const NetlistId& netlist) const;
/* Find if a module belongs to a netlist */

8
openfpga/src/base/openfpga_context.h
View File

@ -12,6 +12,7 @@
#include "mux_library.h"
#include "tile_direct.h"
#include "module_manager.h"
#include "netlist_manager.h"
#include "openfpga_flow_manager.h"
#include "bitstream_manager.h"
#include "device_rr_gsb.h"
@ -61,6 +62,7 @@ class OpenfpgaContext : public Context {
const std::vector<openfpga::ConfigBitId>& fabric_bitstream() const { return fabric_bitstream_; }
const openfpga::IoLocationMap& io_location_map() const { return io_location_map_; }
const std::unordered_map<AtomNetId, t_net_power>& net_activity() const { return net_activity_; }
const openfpga::NetlistManager& verilog_netlists() const { return verilog_netlists_; }
public: /* Public mutators */
openfpga::Arch& mutable_arch() { return arch_; }
openfpga::VprDeviceAnnotation& mutable_vpr_device_annotation() { return vpr_device_annotation_; }
@ -77,6 +79,7 @@ class OpenfpgaContext : public Context {
std::vector<openfpga::ConfigBitId>& mutable_fabric_bitstream() { return fabric_bitstream_; }
openfpga::IoLocationMap& mutable_io_location_map() { return io_location_map_; }
std::unordered_map<AtomNetId, t_net_power>& mutable_net_activity() { return net_activity_; }
openfpga::NetlistManager& mutable_verilog_netlists() { return verilog_netlists_; }
private: /* Internal data */
/* Data structure to store information from read_openfpga_arch library */
openfpga::Arch arch_;
@ -113,6 +116,11 @@ class OpenfpgaContext : public Context {
openfpga::BitstreamManager bitstream_manager_;
std::vector<openfpga::ConfigBitId> fabric_bitstream_;
/* Netlist database
* TODO: Each format should have an independent entry
*/
openfpga::NetlistManager verilog_netlists_;
/* Net activities of users' implementation */
std::unordered_map<AtomNetId, t_net_power> net_activity_;

4
openfpga/src/base/openfpga_verilog.cpp
View File

@ -45,6 +45,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
options.set_compress_routing(openfpga_ctx.flow_manager().compress_routing());
fpga_fabric_verilog(openfpga_ctx.mutable_module_graph(),
openfpga_ctx.mutable_verilog_netlists(),
openfpga_ctx.arch().circuit_lib,
openfpga_ctx.mux_lib(),
g_vpr_ctx.device(),
@ -82,7 +83,8 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
options.set_print_simulation_ini(cmd_context.option_value(cmd, opt_print_simulation_ini));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
fpga_verilog_testbench(openfpga_ctx.module_graph(),
fpga_verilog_testbench(openfpga_ctx.verilog_netlists(),
openfpga_ctx.module_graph(),
openfpga_ctx.bitstream_manager(),
openfpga_ctx.fabric_bitstream(),
g_vpr_ctx.atom(),

22
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -51,6 +51,7 @@ namespace openfpga {
* We should think clearly about how to handle them for both Verilog and SPICE generators!
********************************************************************/
void fpga_fabric_verilog(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
const DeviceContext& device_ctx,
@ -88,33 +89,38 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
* the module manager.
* Without the modules in the module manager, core logic generation is not possible!!!
*/
print_verilog_submodule(module_manager, mux_lib, circuit_lib,
print_verilog_submodule(module_manager, netlist_manager,
mux_lib, circuit_lib,
src_dir_path, submodule_dir_path,
options);
/* Generate routing blocks */
if (true == options.compress_routing()) {
print_verilog_unique_routing_modules(const_cast<const ModuleManager&>(module_manager),
print_verilog_unique_routing_modules(netlist_manager,
const_cast<const ModuleManager&>(module_manager),
device_rr_gsb,
src_dir_path, rr_dir_path,
options.explicit_port_mapping());
} else {
VTR_ASSERT(false == options.compress_routing());
print_verilog_flatten_routing_modules(const_cast<const ModuleManager&>(module_manager),
print_verilog_flatten_routing_modules(netlist_manager,
const_cast<const ModuleManager&>(module_manager),
device_rr_gsb,
src_dir_path, rr_dir_path,
options.explicit_port_mapping());
}
/* Generate grids */
print_verilog_grids(const_cast<const ModuleManager&>(module_manager),
print_verilog_grids(netlist_manager,
const_cast<const ModuleManager&>(module_manager),
device_ctx, device_annotation,
src_dir_path, lb_dir_path,
options.explicit_port_mapping(),
options.verbose_output());
/* Generate FPGA fabric */
print_verilog_top_module(const_cast<const ModuleManager&>(module_manager),
print_verilog_top_module(netlist_manager,
const_cast<const ModuleManager&>(module_manager),
src_dir_path,
options.explicit_port_mapping());
@ -134,7 +140,8 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
* This testbench is created for quick verification and formal verification purpose.
* - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
********************************************************************/
void fpga_verilog_testbench(const ModuleManager& module_manager,
void fpga_verilog_testbench(const NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager,
const std::vector<ConfigBitId>& fabric_bitstream,
const AtomContext& atom_ctx,
@ -219,7 +226,8 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
}
/* Generate a Verilog file including all the netlists that have been generated */
print_include_netlists(src_dir_path,
print_include_netlists(netlist_manager,
src_dir_path,
netlist_name,
options.reference_benchmark_file_path(),
circuit_lib);

5
openfpga/src/fpga_verilog/verilog_api.h
View File

@ -12,6 +12,7 @@
#include "vpr_context.h"
#include "vpr_device_annotation.h"
#include "device_rr_gsb.h"
#include "netlist_manager.h"
#include "module_manager.h"
#include "bitstream_manager.h"
#include "simulation_setting.h"
@ -28,6 +29,7 @@
namespace openfpga {
void fpga_fabric_verilog(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const MuxLibrary& mux_lib,
const DeviceContext& device_ctx,
@ -35,7 +37,8 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const FabricVerilogOption& options);
void fpga_verilog_testbench(const ModuleManager& module_manager,
void fpga_verilog_testbench(const NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const BitstreamManager& bitstream_manager,
const std::vector<ConfigBitId>& fabric_bitstream,
const AtomContext& atom_ctx,

24
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -29,7 +29,8 @@ namespace openfpga {
* and user-defined.
* Some netlists are open to compile under specific preprocessing flags
*******************************************************************/
void print_include_netlists(const std::string& src_dir,
void print_include_netlists(const NetlistManager& netlist_manager,
const std::string& src_dir,
const std::string& circuit_name,
const std::string& reference_benchmark_file,
const CircuitLibrary& circuit_lib) {
@ -55,24 +56,37 @@ void print_include_netlists(const std::string& src_dir,
fp << std::endl;
/* Include all the user-defined netlists */
print_verilog_comment(fp, std::string("------ Include user-defined netlists -----"));
for (const std::string& user_defined_netlist : find_circuit_library_unique_verilog_netlists(circuit_lib)) {
print_verilog_include_netlist(fp, user_defined_netlist);
}
/* Include all the primitive modules */
print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_SUBMODULE_DIR_NAME) + std::string(SUBMODULE_VERILOG_FILE_NAME));
print_verilog_comment(fp, std::string("------ Include primitive module netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl;
/* Include all the CLB, heterogeneous block modules */
print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_LB_DIR_NAME) + std::string(LOGIC_BLOCK_VERILOG_FILE_NAME));
print_verilog_comment(fp, std::string("------ Include logic block netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl;
/* Include all the routing architecture modules */
print_verilog_include_netlist(fp, src_dir + std::string(DEFAULT_RR_DIR_NAME) + std::string(ROUTING_VERILOG_FILE_NAME));
print_verilog_comment(fp, std::string("------ Include routing module netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl;
/* Include FPGA top module */
print_verilog_include_netlist(fp, src_dir + generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX)));
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
print_verilog_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
}
fp << std::endl;
/* Include reference benchmark netlist only when auto-check flag is enabled */

4
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -7,6 +7,7 @@
#include <string>
#include "circuit_library.h"
#include "fabric_verilog_options.h"
#include "netlist_manager.h"
#include "verilog_testbench_options.h"
/********************************************************************
@ -16,7 +17,8 @@
/* begin namespace openfpga */
namespace openfpga {
void print_include_netlists(const std::string& src_dir,
void print_include_netlists(const NetlistManager& netlist_manager,
const std::string& src_dir,
const std::string& circuit_name,
const std::string& reference_benchmark_file,
const CircuitLibrary& circuit_lib);

6
openfpga/src/fpga_verilog/verilog_decoders.cpp
View File

@ -162,7 +162,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
* See more details in the function print_verilog_mux_local_decoder() for more details
***************************************************************************************/
void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
@ -223,7 +223,9 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
VTR_LOG("Done\n");
}

3
openfpga/src/fpga_verilog/verilog_decoders.h
View File

@ -12,6 +12,7 @@
#include "mux_graph.h"
#include "mux_library.h"
#include "module_manager.h"
#include "netlist_manager.h"
/********************************************************************
* Function declaration
@ -21,7 +22,7 @@
namespace openfpga {
void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

6
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -526,7 +526,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager
* etc.
***********************************************/
void print_verilog_submodule_essentials(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const std::string& verilog_dir,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib) {
@ -577,7 +577,9 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
VTR_LOG("Done\n");
}

4
openfpga/src/fpga_verilog/verilog_essential_gates.h
View File

@ -6,6 +6,8 @@
*******************************************************************/
#include <string>
#include "circuit_library.h"
#include "module_manager.h"
#include "netlist_manager.h"
/********************************************************************
* Function declaration
@ -15,7 +17,7 @@
namespace openfpga {
void print_verilog_submodule_essentials(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const std::string& verilog_dir,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib);

30
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -194,8 +194,8 @@ void rec_print_verilog_logical_tile(std::fstream& fp,
* for the logical tile (pb_graph/pb_type)
*****************************************************************************/
static
void print_verilog_logical_tile_netlist(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
void print_verilog_logical_tile_netlist(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const VprDeviceAnnotation& device_annotation,
const std::string& verilog_dir,
const std::string& subckt_dir,
@ -243,7 +243,9 @@ void print_verilog_logical_tile_netlist(const ModuleManager& module_manager,
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
VTR_LOG("Done\n");
VTR_LOG("\n");
@ -258,8 +260,8 @@ void print_verilog_logical_tile_netlist(const ModuleManager& module_manager,
* the I/O block locates at.
*****************************************************************************/
static
void print_verilog_physical_tile_netlist(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const std::string& subckt_dir,
t_physical_tile_type_ptr phy_block_type,
@ -319,7 +321,9 @@ void print_verilog_physical_tile_netlist(const ModuleManager& module_manager,
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
VTR_LOG("Done\n");
}
@ -330,7 +334,8 @@ void print_verilog_physical_tile_netlist(const ModuleManager& module_manager,
* 2. Only one module for each CLB (FILL_TYPE)
* 3. Only one module for each heterogeneous block
****************************************************************************/
void print_verilog_grids(const ModuleManager& module_manager,
void print_verilog_grids(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const std::string& verilog_dir,
@ -354,7 +359,8 @@ void print_verilog_grids(const ModuleManager& module_manager,
if (nullptr == logical_tile.pb_graph_head) {
continue;
}
print_verilog_logical_tile_netlist(module_manager, netlist_names,
print_verilog_logical_tile_netlist(netlist_manager,
module_manager,
device_annotation,
verilog_dir, subckt_dir,
logical_tile.pb_graph_head,
@ -387,7 +393,8 @@ void print_verilog_grids(const ModuleManager& module_manager,
std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
&physical_tile);
for (const e_side& io_type_side : io_type_sides) {
print_verilog_physical_tile_netlist(module_manager, netlist_names,
print_verilog_physical_tile_netlist(netlist_manager,
module_manager,
verilog_dir, subckt_dir,
&physical_tile,
io_type_side,
@ -396,7 +403,8 @@ void print_verilog_grids(const ModuleManager& module_manager,
continue;
} else {
/* For CLB and heterogenenous blocks */
print_verilog_physical_tile_netlist(module_manager, netlist_names,
print_verilog_physical_tile_netlist(netlist_manager,
module_manager,
verilog_dir, subckt_dir,
&physical_tile,
NUM_SIDES,
@ -408,6 +416,7 @@ void print_verilog_grids(const ModuleManager& module_manager,
VTR_LOG("\n");
/* Output a header file for all the logic blocks */
/*
std::string grid_verilog_fname(LOGIC_BLOCK_VERILOG_FILE_NAME);
VTR_LOG("Writing header file for grid Verilog modules '%s' ...",
grid_verilog_fname.c_str());
@ -415,6 +424,7 @@ void print_verilog_grids(const ModuleManager& module_manager,
subckt_dir.c_str(),
grid_verilog_fname.c_str());
VTR_LOG("Done\n");
*/
}
} /* end namespace openfpga */

4
openfpga/src/fpga_verilog/verilog_grid.h
View File

@ -7,6 +7,7 @@
#include <string>
#include "vpr_context.h"
#include "module_manager.h"
#include "netlist_manager.h"
#include "vpr_device_annotation.h"
/********************************************************************
@ -16,7 +17,8 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_grids(const ModuleManager& module_manager,
void print_verilog_grids(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceContext& device_ctx,
const VprDeviceAnnotation& device_annotation,
const std::string& verilog_dir,

6
openfpga/src/fpga_verilog/verilog_lut.cpp
View File

@ -30,7 +30,7 @@ namespace openfpga {
* in the circuit library
********************************************************************/
void print_verilog_submodule_luts(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,
@ -70,7 +70,9 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
VTR_LOG("Done\n");
}

3
openfpga/src/fpga_verilog/verilog_lut.h
View File

@ -9,6 +9,7 @@
#include "circuit_library.h"
#include "module_manager.h"
#include "netlist_manager.h"
/********************************************************************
* Function declaration
@ -18,7 +19,7 @@
namespace openfpga {
void print_verilog_submodule_luts(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir,

6
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -97,7 +97,7 @@ void print_verilog_mux_memory_module(const ModuleManager& module_manager,
* memory-bank organization for the memories.
********************************************************************/
void print_verilog_submodule_memories(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
@ -187,7 +187,9 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
VTR_LOG("Done\n");
}

3
openfpga/src/fpga_verilog/verilog_memory.h
View File

@ -10,6 +10,7 @@
#include "mux_graph.h"
#include "mux_library.h"
#include "module_manager.h"
#include "netlist_manager.h"
/********************************************************************
* Function declaration
@ -19,7 +20,7 @@
namespace openfpga {
void print_verilog_submodule_memories(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

6
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -1224,7 +1224,7 @@ void generate_verilog_mux_module(ModuleManager& module_manager,
* multiplexers in the FPGA device
**********************************************/
void print_verilog_submodule_muxes(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
@ -1273,7 +1273,9 @@ void print_verilog_submodule_muxes(ModuleManager& module_manager,
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
VTR_LOG("Done\n");
}

3
openfpga/src/fpga_verilog/verilog_mux.h
View File

@ -11,6 +11,7 @@
#include "mux_graph.h"
#include "mux_library.h"
#include "module_manager.h"
#include "netlist_manager.h"
/********************************************************************
* Function declaration
@ -20,7 +21,7 @@
namespace openfpga {
void print_verilog_submodule_muxes(ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

49
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -75,8 +75,8 @@ namespace openfpga {
*
********************************************************************/
static
void print_verilog_routing_connection_box_unique_module(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const std::string& subckt_dir,
const RRGSB& rr_gsb,
@ -111,7 +111,9 @@ void print_verilog_routing_connection_box_unique_module(const ModuleManager& mod
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
}
/*********************************************************************
@ -178,8 +180,8 @@ void print_verilog_routing_connection_box_unique_module(const ModuleManager& mod
*
********************************************************************/
static
void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const std::string& subckt_dir,
const RRGSB& rr_gsb,
@ -210,7 +212,9 @@ void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
}
/********************************************************************
@ -218,8 +222,8 @@ void print_verilog_routing_switch_box_unique_module(const ModuleManager& module_
* and build a module for each of them
*******************************************************************/
static
void print_verilog_flatten_connection_block_modules(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
void print_verilog_flatten_connection_block_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
@ -238,7 +242,8 @@ void print_verilog_flatten_connection_block_modules(const ModuleManager& module_
if (true != rr_gsb.is_cb_exist(cb_type)) {
continue;
}
print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
print_verilog_routing_connection_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
rr_gsb, cb_type,
@ -256,7 +261,8 @@ void print_verilog_flatten_connection_block_modules(const ModuleManager& module_
* 1. Connection blocks
* 2. Switch blocks
*******************************************************************/
void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
@ -273,7 +279,8 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
if (true != rr_gsb.is_sb_exist()) {
continue;
}
print_verilog_routing_switch_box_unique_module(module_manager, netlist_names,
print_verilog_routing_switch_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
rr_gsb,
@ -281,10 +288,11 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
}
}
print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANX, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(module_manager, netlist_names, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
print_verilog_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, verilog_dir, subckt_dir, CHANY, use_explicit_port_map);
/*
VTR_LOG("Writing header file for routing submodules '%s'...",
ROUTING_VERILOG_FILE_NAME);
print_verilog_netlist_include_header_file(netlist_names,
@ -292,6 +300,7 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
ROUTING_VERILOG_FILE_NAME);
VTR_LOG("Done\n");
VTR_LOG("\n");
*/
}
@ -305,7 +314,8 @@ void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
* Note: this function SHOULD be called only when
* the option compact_routing_hierarchy is turned on!!!
*******************************************************************/
void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
@ -316,7 +326,8 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
/* Build unique switch block modules */
for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
print_verilog_routing_switch_box_unique_module(module_manager, netlist_names,
print_verilog_routing_switch_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
unique_mirror,
@ -327,7 +338,8 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
print_verilog_routing_connection_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
unique_mirror, CHANX,
@ -338,19 +350,22 @@ void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
print_verilog_routing_connection_box_unique_module(module_manager, netlist_names,
print_verilog_routing_connection_box_unique_module(netlist_manager,
module_manager,
verilog_dir,
subckt_dir,
unique_mirror, CHANY,
use_explicit_port_map);
}
/*
VTR_LOG("Writing header file for routing submodules '%s'...",
ROUTING_VERILOG_FILE_NAME);
print_verilog_netlist_include_header_file(netlist_names,
subckt_dir.c_str(),
ROUTING_VERILOG_FILE_NAME);
VTR_LOG("Done\n");
*/
VTR_LOG("\n");
}

7
openfpga/src/fpga_verilog/verilog_routing.h
View File

@ -7,6 +7,7 @@
#include "mux_library.h"
#include "module_manager.h"
#include "netlist_manager.h"
#include "device_rr_gsb.h"
/********************************************************************
@ -16,13 +17,15 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_flatten_routing_modules(const ModuleManager& module_manager,
void print_verilog_flatten_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,
const bool& use_explicit_port_map);
void print_verilog_unique_routing_modules(const ModuleManager& module_manager,
void print_verilog_unique_routing_modules(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const DeviceRRGSB& device_rr_gsb,
const std::string& verilog_dir,
const std::string& subckt_dir,

21
openfpga/src/fpga_verilog/verilog_submodule.cpp
View File

@ -32,6 +32,7 @@ namespace openfpga {
* 6. Verilog template
********************************************************************/
void print_verilog_submodule(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
@ -44,12 +45,8 @@ void print_verilog_submodule(ModuleManager& module_manager,
*/
//add_user_defined_verilog_modules(module_manager, circuit_lib);
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
std::vector<std::string> netlist_names;
print_verilog_submodule_essentials(const_cast<const ModuleManager&>(module_manager),
netlist_names,
netlist_manager,
verilog_dir,
submodule_dir,
circuit_lib);
@ -59,28 +56,28 @@ void print_verilog_submodule(ModuleManager& module_manager,
* because local decoders modules will be instanciated in the MUX modules
*/
print_verilog_submodule_mux_local_decoders(const_cast<const ModuleManager&>(module_manager),
netlist_names,
netlist_manager,
mux_lib, circuit_lib,
verilog_dir, submodule_dir);
print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, circuit_lib,
print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib,
verilog_dir, submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
/* LUTes */
print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
netlist_names, circuit_lib,
netlist_manager, circuit_lib,
verilog_dir, submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
/* Hard wires */
print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
netlist_names, circuit_lib,
netlist_manager, circuit_lib,
verilog_dir, submodule_dir);
/* 4. Memories */
print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
netlist_names,
netlist_manager,
mux_lib, circuit_lib,
verilog_dir, submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
@ -93,9 +90,11 @@ void print_verilog_submodule(ModuleManager& module_manager,
}
/* Create a header file to include all the subckts */
print_verilog_netlist_include_header_file(netlist_names,
/*
print_verilog_netlist_include_header_file(netlist_manager,
submodule_dir.c_str(),
SUBMODULE_VERILOG_FILE_NAME);
*/
}
} /* end namespace openfpga */

2
openfpga/src/fpga_verilog/verilog_submodule.h
View File

@ -5,6 +5,7 @@
* Include header files that are required by function declaration
*******************************************************************/
#include "module_manager.h"
#include "netlist_manager.h"
#include "mux_library.h"
#include "fabric_verilog_options.h"
@ -16,6 +17,7 @@
namespace openfpga {
void print_verilog_submodule(ModuleManager& module_manager,
NetlistManager& netlist_manager,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

8
openfpga/src/fpga_verilog/verilog_top_module.cpp
View File

@ -34,7 +34,8 @@ namespace openfpga {
* 4. Add module nets to connect datapath ports
* 5. Add module nets/submodules to connect configuration ports
*******************************************************************/
void print_verilog_top_module(const ModuleManager& module_manager,
void print_verilog_top_module(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const bool& use_explicit_mapping) {
/* Create a module as the top-level fabric, and add it to the module manager */
@ -69,6 +70,11 @@ void print_verilog_top_module(const ModuleManager& module_manager,
/* Close file handler */
fp.close();
/* Add fname to the netlist name list */
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::TOP_MODULE_NETLIST);
VTR_LOG("Done\n");
}

4
openfpga/src/fpga_verilog/verilog_top_module.h
View File

@ -6,6 +6,7 @@
*******************************************************************/
#include <string>
#include "module_manager.h"
#include "netlist_manager.h"
/********************************************************************
* Function declaration
@ -14,7 +15,8 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_top_module(const ModuleManager& module_manager,
void print_verilog_top_module(NetlistManager& netlist_manager,
const ModuleManager& module_manager,
const std::string& verilog_dir,
const bool& use_explicit_mapping);

6
openfpga/src/fpga_verilog/verilog_wire.cpp
View File

@ -93,7 +93,7 @@ void print_verilog_wire_module(const ModuleManager& module_manager,
* Top-level function to print wire modules
*******************************************************************/
void print_verilog_submodule_wires(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
@ -128,7 +128,9 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
fp.close();
/* Add fname to the netlist name list */
netlist_names.push_back(verilog_fname);
NetlistId nlist_id = netlist_manager.add_netlist(verilog_fname);
VTR_ASSERT(NetlistId::INVALID() != nlist_id);
netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
VTR_LOG("Done\n");
}

3
openfpga/src/fpga_verilog/verilog_wire.h
View File

@ -9,6 +9,7 @@
#include "circuit_library.h"
#include "module_manager.h"
#include "netlist_manager.h"
/********************************************************************
* Function declaration
@ -18,7 +19,7 @@
namespace openfpga {
void print_verilog_submodule_wires(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir);