From e7a3b48475f038b741c292326eb2d9cc30fc6c34 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 24 Jan 2023 15:24:17 -0800
Subject: [PATCH] [arch] comment on the wrong mode bits

---
 .../openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml          | 1 +
 1 file changed, 1 insertion(+)

diff --git a/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml
index ffcf9493d..9962461bf 100644
--- a/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_N4_frac_dsp16_40nm_cc_openfpga.xml
@@ -199,6 +199,7 @@
     <!-- physical pb_type binding in complex block dsp -->
     <pb_type name="mult_16" physical_mode_name="mult_16x16"/>
     <!-- Bind the primitive pb_type in the physical mode to a circuit model -->
+    <!-- IMPORTANT: the mode bits are intended to be wrong. Designed to validate the correctness of bitstream setting files. See correct mode bits in the openfpga_flow/openfpga_yosys_techlib/k4_N4_tileable_frac_dsp16_dsp_map.v -->
     <pb_type name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" circuit_model_name="frac_mult_16x16" mode_bits="1"/>
     <pb_type name="mult_16[mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_16[mult_16x16].mult_16x16_slice.mult_16x16" mode_bits="0" physical_pb_type_index_factor="0">
       <port name="A" physical_mode_port="A[0:7]" physical_mode_port_rotate_offset="8"/>