diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
index cd27e97eb..8c90e2c30 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
@@ -10,6 +10,7 @@ proc
 techmap -D NO_LUT -map ${YOSYS_DFF_MAP_VERILOG}
 
 # Synthesis
+flatten
 opt_expr
 opt_clean
 check
diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
index b4021a084..629211c88 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow.ys
@@ -8,6 +8,7 @@ proc
 techmap -D NO_LUT -map +/adff2dff.v
 
 # Synthesis
+flatten
 opt_expr
 opt_clean
 check
diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
index f614760dc..ad1549d25 100644
--- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
+++ b/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
@@ -8,6 +8,7 @@ proc
 techmap -D NO_LUT -map +/adff2dff.v
 
 # Synthesis
+flatten
 opt_expr
 opt_clean
 check