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update circuit model names in the example tree-like MUX architecture

This commit is contained in:
tangxifan 2020-04-07 11:27:16 -06:00
parent 0eeb8e5317
commit e61e7167b3
1 changed files with 4 additions and 4 deletions
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8
openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
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@ -75,7 +75,7 @@
10e-12 5e-12 10e-12 5e-12
</delay_matrix> </delay_matrix>
</circuit_model> </circuit_model>
<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true"> <circuit_model type="pass_gate" name="MUX2" prefix="MUX2" is_default="true">
<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/> <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
<input_buffer exist="false"/> <input_buffer exist="false"/>
<output_buffer exist="false"/> <output_buffer exist="false"/>
@ -110,7 +110,7 @@
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="INVTX1"/> <output_buffer exist="true" circuit_model_name="INVTX1"/>
<pass_gate_logic circuit_model_name="TGATE"/> <pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/> <port type="sram" prefix="sram" size="1"/>
@ -119,7 +119,7 @@
<design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/> <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
<input_buffer exist="true" circuit_model_name="INVTX1"/> <input_buffer exist="true" circuit_model_name="INVTX1"/>
<output_buffer exist="true" circuit_model_name="tap_buf4"/> <output_buffer exist="true" circuit_model_name="tap_buf4"/>
<pass_gate_logic circuit_model_name="TGATE"/> <pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="1"/> <port type="input" prefix="in" size="1"/>
<port type="output" prefix="out" size="1"/> <port type="output" prefix="out" size="1"/>
<port type="sram" prefix="sram" size="1"/> <port type="sram" prefix="sram" size="1"/>
@ -142,7 +142,7 @@
<lut_input_inverter exist="true" circuit_model_name="INVTX1"/> <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
<lut_input_buffer exist="true" circuit_model_name="buf4"/> <lut_input_buffer exist="true" circuit_model_name="buf4"/>
<lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/> <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
<pass_gate_logic circuit_model_name="TGATE"/> <pass_gate_logic circuit_model_name="MUX2"/>
<port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/> <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
<port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/> <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
<port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/> <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>