From e5facf88662a2ae40a908ea81d35eed449082b52 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 11:40:49 -0600 Subject: [PATCH] [Test] Deploy const gnd test case to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index d96917bd3..73a549bd1 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -70,6 +70,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_onl echo -e "Testing Verilog generation with routing multiplexers with output buffers only"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs +echo -e "Testing Verilog generation with routing multiplexers with constant gnd input"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs + echo -e "Testing Verilog generation with behavioral description"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs