From e58e1e86c2f24c38014f92bec999ca9278cd7e4c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 10 Jan 2021 11:09:10 -0700 Subject: [PATCH] [Test] Update test case to use new shell script --- .../tasks/fpga_verilog/io/registerable_io/config/task.conf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf index 3178d2d53..700f8e3c7 100644 --- a/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/io/registerable_io/config/task.conf @@ -16,9 +16,10 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_global_tile_clock_example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClk_registerable_io_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml