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add more tests

This commit is contained in:
tangxifan 2019-08-23 14:09:20 -06:00
parent 95f8fea299
commit e55c6d5b41
2 changed files with 1099 additions and 27 deletions
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1042
openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml Normal file
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84
run_test.sh
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@ -15,7 +15,6 @@
# --vpr_fpga_verilog_include_signal_init \ # --vpr_fpga_verilog_include_signal_init \
# --vpr_fpga_verilog_print_autocheck_top_testbench # --vpr_fpga_verilog_print_autocheck_top_testbench
# Test popular multi-mode architecture # Test popular multi-mode architecture
python3.5 openfpga_flow/scripts/run_fpga_flow.py \ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \ ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
@ -26,7 +25,8 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
--power \ --power \
--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
--fix_route_chan_width 300 \ #--fix_route_chan_width 300 \
--min_route_chan_width 1.3 \
--vpr_fpga_verilog \ --vpr_fpga_verilog \
--vpr_fpga_verilog_dir . \ --vpr_fpga_verilog_dir . \
--vpr_fpga_x2p_rename_illegal_port \ --vpr_fpga_x2p_rename_illegal_port \
@ -45,32 +45,33 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
--end_flow_with_test --end_flow_with_test
# Test Standard cell MUX2 # Test Standard cell MUX2
#python3.5 openfpga_flow/scripts/run_fpga_flow.py \ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
#./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \ ./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \ ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
#--fpga_flow vpr_blif \ --fpga_flow vpr_blif \
#--top_module test_modes \ --top_module test_modes \
#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \ --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \ --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
#--power \ --power \
#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \ --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
#--fix_route_chan_width 300 \ #--fix_route_chan_width 300 \
#--vpr_fpga_verilog \ --min_route_chan_width 1.3 \
#--vpr_fpga_verilog_dir . \ --vpr_fpga_verilog \
#--vpr_fpga_x2p_rename_illegal_port \ --vpr_fpga_verilog_dir . \
#--vpr_fpga_verilog_include_icarus_simulator \ --vpr_fpga_x2p_rename_illegal_port \
#--vpr_fpga_verilog_formal_verification_top_netlist \ --vpr_fpga_verilog_include_icarus_simulator \
#--vpr_fpga_verilog_include_timing \ --vpr_fpga_verilog_formal_verification_top_netlist \
#--vpr_fpga_verilog_include_signal_init \ --vpr_fpga_verilog_include_timing \
#--vpr_fpga_verilog_print_autocheck_top_testbench \ --vpr_fpga_verilog_include_signal_init \
#--debug \ --vpr_fpga_verilog_print_autocheck_top_testbench \
#--vpr_fpga_bitstream_generator \ --debug \
#--vpr_fpga_verilog_print_user_defined_template \ --vpr_fpga_bitstream_generator \
#--vpr_fpga_verilog_print_report_timing_tcl \ --vpr_fpga_verilog_print_user_defined_template \
#--vpr_fpga_verilog_print_sdc_pnr \ --vpr_fpga_verilog_print_report_timing_tcl \
#--vpr_fpga_verilog_print_sdc_analysis \ --vpr_fpga_verilog_print_sdc_pnr \
#--vpr_fpga_x2p_compact_routing_hierarchy \ --vpr_fpga_verilog_print_sdc_analysis \
#--end_flow_with_test --vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test
# Test local encoder feature # Test local encoder feature
python3.5 openfpga_flow/scripts/run_fpga_flow.py \ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
@ -100,4 +101,33 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
--vpr_fpga_x2p_compact_routing_hierarchy \ --vpr_fpga_x2p_compact_routing_hierarchy \
--end_flow_with_test --end_flow_with_test
# Test tileable routing feature
#python3.5 openfpga_flow/scripts/run_fpga_flow.py \
#./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \
#./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
#--fpga_flow vpr_blif \
#--top_module test_modes \
#--activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
#--base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
#--power \
#--power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
##--fix_route_chan_width 300 \
#--min_route_chan_width 1.3 \
#--vpr_fpga_verilog \
#--vpr_fpga_verilog_dir . \
#--vpr_fpga_x2p_rename_illegal_port \
#--vpr_fpga_verilog_include_icarus_simulator \
#--vpr_fpga_verilog_formal_verification_top_netlist \
#--vpr_fpga_verilog_include_timing \
#--vpr_fpga_verilog_include_signal_init \
#--vpr_fpga_verilog_print_autocheck_top_testbench \
#--debug \
#--vpr_fpga_bitstream_generator \
#--vpr_fpga_verilog_print_user_defined_template \
#--vpr_fpga_verilog_print_report_timing_tcl \
#--vpr_fpga_verilog_print_sdc_pnr \
#--vpr_fpga_verilog_print_sdc_analysis \
#--vpr_fpga_x2p_compact_routing_hierarchy \
#--vpr_use_tileable_route_chan_width \
#--end_flow_with_test