From e46e58527ac7c8467c2148a9bcde5ec6fc4affea Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 17 Sep 2023 23:16:38 -0700 Subject: [PATCH] [core] code format --- .../fpga_bitstream/build_device_bitstream.cpp | 17 +-- .../fpga_bitstream/build_grid_bitstream.cpp | 128 +++++++++--------- .../src/fpga_bitstream/build_grid_bitstream.h | 10 +- .../build_routing_bitstream.cpp | 85 ++++++------ 4 files changed, 112 insertions(+), 128 deletions(-) diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index f74c35acc..ecb9bad62 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -208,14 +208,15 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, /* Create bitstream from grids */ VTR_LOGV(verbose, "Building grid bitstream...\n"); - build_grid_bitstream(bitstream_manager, top_block, - openfpga_ctx.module_graph(), openfpga_ctx.module_name_map(), openfpga_ctx.fabric_tile(), - openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), - vpr_ctx.device().grid, 0, vpr_ctx.atom(), - openfpga_ctx.vpr_device_annotation(), - openfpga_ctx.vpr_clustering_annotation(), - openfpga_ctx.vpr_placement_annotation(), - openfpga_ctx.vpr_bitstream_annotation(), verbose); + build_grid_bitstream( + bitstream_manager, top_block, openfpga_ctx.module_graph(), + openfpga_ctx.module_name_map(), openfpga_ctx.fabric_tile(), + openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), + vpr_ctx.device().grid, 0, vpr_ctx.atom(), + openfpga_ctx.vpr_device_annotation(), + openfpga_ctx.vpr_clustering_annotation(), + openfpga_ctx.vpr_placement_annotation(), + openfpga_ctx.vpr_bitstream_annotation(), verbose); VTR_LOGV(verbose, "Done\n"); /* Create bitstream from routing architectures */ diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 2440a38ef..d8e4f17fb 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -180,11 +180,9 @@ static void build_physical_block_pin_interc_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, const PhysicalPb& physical_pb, t_pb_graph_pin* des_pb_graph_pin, t_mode* physical_mode, const bool& verbose) { @@ -381,11 +379,9 @@ static void build_physical_block_interc_port_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb, const e_circuit_pb_port_type& pb_port_type, t_mode* physical_mode, @@ -398,8 +394,9 @@ static void build_physical_block_interc_port_bitstream( ++ipin) { build_physical_block_pin_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, bitstream_annotation, physical_pb, + parent_configurable_block, module_manager, module_name_map, + circuit_lib, mux_lib, atom_ctx, device_annotation, + bitstream_annotation, physical_pb, &(physical_pb_graph_node->input_pins[iport][ipin]), physical_mode, verbose); } @@ -412,8 +409,9 @@ static void build_physical_block_interc_port_bitstream( ipin < physical_pb_graph_node->num_output_pins[iport]; ++ipin) { build_physical_block_pin_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, bitstream_annotation, physical_pb, + parent_configurable_block, module_manager, module_name_map, + circuit_lib, mux_lib, atom_ctx, device_annotation, + bitstream_annotation, physical_pb, &(physical_pb_graph_node->output_pins[iport][ipin]), physical_mode, verbose); } @@ -426,8 +424,9 @@ static void build_physical_block_interc_port_bitstream( ++ipin) { build_physical_block_pin_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, bitstream_annotation, physical_pb, + parent_configurable_block, module_manager, module_name_map, + circuit_lib, mux_lib, atom_ctx, device_annotation, + bitstream_annotation, physical_pb, &(physical_pb_graph_node->clock_pins[iport][ipin]), physical_mode, verbose); } @@ -447,11 +446,9 @@ static void build_physical_block_interc_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, t_pb_graph_node* physical_pb_graph_node, const PhysicalPb& physical_pb, t_mode* physical_mode, const bool& verbose) { @@ -473,9 +470,9 @@ static void build_physical_block_interc_bitstream( */ build_physical_block_interc_port_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, parent_configurable_block, - module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, - bitstream_annotation, physical_pb_graph_node, physical_pb, - CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose); + module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, + device_annotation, bitstream_annotation, physical_pb_graph_node, + physical_pb, CIRCUIT_PB_PORT_OUTPUT, physical_mode, verbose); /* We check input_pins of child_pb_graph_node and its the input_edges * Iterate over the interconnections between inputs of physical_pb_graph_node @@ -496,15 +493,17 @@ static void build_physical_block_interc_bitstream( /* For each child_pb_graph_node input pins*/ build_physical_block_interc_port_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node, - physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode, verbose); + parent_configurable_block, module_manager, module_name_map, circuit_lib, + mux_lib, atom_ctx, device_annotation, bitstream_annotation, + child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_INPUT, physical_mode, + verbose); /* For clock pins, we should do the same work */ build_physical_block_interc_port_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - parent_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, bitstream_annotation, child_pb_graph_node, - physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode, verbose); + parent_configurable_block, module_manager, module_name_map, circuit_lib, + mux_lib, atom_ctx, device_annotation, bitstream_annotation, + child_pb_graph_node, physical_pb, CIRCUIT_PB_PORT_CLOCK, physical_mode, + verbose); } } } @@ -707,11 +706,9 @@ static void rec_build_physical_block_bitstream( BitstreamManager& bitstream_manager, std::map& grouped_mem_inst_scoreboard, const ConfigBlockId& parent_configurable_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprBitstreamAnnotation& bitstream_annotation, const e_side& border_side, const PhysicalPb& physical_pb, const PhysicalPbId& pb_id, t_pb_graph_node* physical_pb_graph_node, const size_t& pb_graph_node_index, @@ -771,8 +768,9 @@ static void rec_build_physical_block_bitstream( /* Go recursively */ rec_build_physical_block_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, - module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, - bitstream_annotation, border_side, physical_pb, child_pb, + module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, + device_annotation, bitstream_annotation, border_side, physical_pb, + child_pb, &(physical_pb_graph_node ->child_pb_graph_nodes[physical_mode->index][ipb][jpb]), jpb, verbose); @@ -817,9 +815,9 @@ static void rec_build_physical_block_bitstream( /* Generate the bitstream for the interconnection in this physical block */ build_physical_block_interc_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, pb_configurable_block, - module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, - bitstream_annotation, physical_pb_graph_node, physical_pb, physical_mode, - verbose); + module_manager, module_name_map, circuit_lib, mux_lib, atom_ctx, + device_annotation, bitstream_annotation, physical_pb_graph_node, + physical_pb, physical_mode, verbose); } /******************************************************************** @@ -830,12 +828,10 @@ static void rec_build_physical_block_bitstream( *******************************************************************/ static void build_physical_block_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricTile& fabric_tile, - const FabricTileId& curr_tile, const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const FabricTileId& curr_tile, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, const VprBitstreamAnnotation& bitstream_annotation, const DeviceGrid& grids, @@ -932,10 +928,10 @@ static void build_physical_block_bitstream( /* Recursively traverse the pb_graph and generate bitstream */ rec_build_physical_block_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - grid_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, bitstream_annotation, border_side, - PhysicalPb(), PhysicalPbId::INVALID(), lb_type->pb_graph_head, z, - verbose); + grid_configurable_block, module_manager, module_name_map, circuit_lib, + mux_lib, atom_ctx, device_annotation, bitstream_annotation, + border_side, PhysicalPb(), PhysicalPbId::INVALID(), + lb_type->pb_graph_head, z, verbose); } else { const PhysicalPb& phy_pb = cluster_annotation.physical_pb( place_annotation.grid_blocks(grid_coord)[z]); @@ -948,9 +944,9 @@ static void build_physical_block_bitstream( /* Recursively traverse the pb_graph and generate bitstream */ rec_build_physical_block_bitstream( bitstream_manager, grouped_mem_inst_scoreboard, - grid_configurable_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, bitstream_annotation, border_side, - phy_pb, top_pb_id, pb_graph_head, z, verbose); + grid_configurable_block, module_manager, module_name_map, circuit_lib, + mux_lib, atom_ctx, device_annotation, bitstream_annotation, + border_side, phy_pb, top_pb_id, pb_graph_head, z, verbose); } } } @@ -964,12 +960,10 @@ static void build_physical_block_bitstream( *******************************************************************/ void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricTile& fabric_tile, - const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, const DeviceGrid& grids, const size_t& layer, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose) { @@ -1010,10 +1004,10 @@ void build_grid_bitstream( } build_physical_block_bitstream( - bitstream_manager, parent_block, module_manager, module_name_map, fabric_tile, curr_tile, - circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, bitstream_annotation, grids, layer, grid_coord, - NUM_SIDES, verbose); + bitstream_manager, parent_block, module_manager, module_name_map, + fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, + device_annotation, cluster_annotation, place_annotation, + bitstream_annotation, grids, layer, grid_coord, NUM_SIDES, verbose); } } VTR_LOGV(verbose, "Done\n"); @@ -1058,10 +1052,10 @@ void build_grid_bitstream( } build_physical_block_bitstream( - bitstream_manager, parent_block, module_manager, module_name_map, fabric_tile, curr_tile, - circuit_lib, mux_lib, atom_ctx, device_annotation, cluster_annotation, - place_annotation, bitstream_annotation, grids, layer, io_coordinate, - io_side, verbose); + bitstream_manager, parent_block, module_manager, module_name_map, + fabric_tile, curr_tile, circuit_lib, mux_lib, atom_ctx, + device_annotation, cluster_annotation, place_annotation, + bitstream_annotation, grids, layer, io_coordinate, io_side, verbose); } } VTR_LOGV(verbose, "Done\n"); diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.h b/openfpga/src/fpga_bitstream/build_grid_bitstream.h index c4b315253..36b297c98 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.h @@ -28,12 +28,10 @@ namespace openfpga { void build_grid_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const FabricTile& fabric_tile, - const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const DeviceGrid& grids, const size_t& layer, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, const DeviceGrid& grids, const size_t& layer, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprClusteringAnnotation& cluster_annotation, const VprPlacementAnnotation& place_annotation, const VprBitstreamAnnotation& bitstream_annotation, const bool& verbose); diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index dadeddb97..d299c635e 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -33,12 +33,11 @@ namespace openfpga { *******************************************************************/ static void build_switch_block_mux_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& mux_mem_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const RRGraphView& rr_graph, - const RRNodeId& cur_rr_node, const std::vector& drive_rr_nodes, - const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const RRGraphView& rr_graph, const RRNodeId& cur_rr_node, + const std::vector& drive_rr_nodes, const AtomContext& atom_ctx, + const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const bool& verbose) { /* Check current rr_node is CHANX or CHANY*/ VTR_ASSERT((CHANX == rr_graph.node_type(cur_rr_node)) || @@ -155,11 +154,10 @@ static void build_switch_block_mux_bitstream( static void build_switch_block_interc_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& sb_configurable_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const RRGraphView& rr_graph, - const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const RRGraphView& rr_graph, const AtomContext& atom_ctx, + const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGSB& rr_gsb, const e_side& chan_side, const size_t& chan_node_id, const bool& verbose) { std::vector driver_rr_nodes; @@ -195,9 +193,9 @@ static void build_switch_block_interc_bitstream( bitstream_manager.block_name(sb_configurable_block).c_str()); /* This is a routing multiplexer! Generate bitstream */ build_switch_block_mux_bitstream( - bitstream_manager, mux_mem_block, module_manager, module_name_map, circuit_lib, mux_lib, - rr_graph, cur_rr_node, driver_rr_nodes, atom_ctx, device_annotation, - routing_annotation, verbose); + bitstream_manager, mux_mem_block, module_manager, module_name_map, + circuit_lib, mux_lib, rr_graph, cur_rr_node, driver_rr_nodes, atom_ctx, + device_annotation, routing_annotation, verbose); } /*Nothing should be done else*/ } @@ -215,9 +213,8 @@ static void build_switch_block_interc_bitstream( static void build_switch_block_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& sb_config_block, const ModuleManager& module_manager, const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const bool& verbose) { /* Iterate over all the multiplexers */ @@ -235,9 +232,9 @@ static void build_switch_block_bitstream( continue; } build_switch_block_interc_bitstream( - bitstream_manager, sb_config_block, module_manager, module_name_map, circuit_lib, - mux_lib, rr_graph, atom_ctx, device_annotation, routing_annotation, - rr_gsb, side_manager.get_side(), itrack, verbose); + bitstream_manager, sb_config_block, module_manager, module_name_map, + circuit_lib, mux_lib, rr_graph, atom_ctx, device_annotation, + routing_annotation, rr_gsb, side_manager.get_side(), itrack, verbose); } } } @@ -251,11 +248,9 @@ static void build_switch_block_bitstream( *******************************************************************/ static void build_connection_block_mux_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& mux_mem_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const e_side& cb_ipin_side, const size_t& ipin_index, const bool& verbose) { @@ -377,11 +372,9 @@ static void build_connection_block_mux_bitstream( static void build_connection_block_interc_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& cb_configurable_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const e_side& cb_ipin_side, const size_t& ipin_index, const bool& verbose) { @@ -413,9 +406,9 @@ static void build_connection_block_interc_bitstream( bitstream_manager.block_name(cb_configurable_block).c_str()); /* This is a routing multiplexer! Generate bitstream */ build_connection_block_mux_bitstream( - bitstream_manager, mux_mem_block, module_manager, module_name_map, circuit_lib, mux_lib, - atom_ctx, device_annotation, routing_annotation, rr_graph, rr_gsb, - cb_ipin_side, ipin_index, verbose); + bitstream_manager, mux_mem_block, module_manager, module_name_map, + circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation, + rr_graph, rr_gsb, cb_ipin_side, ipin_index, verbose); } /*Nothing should be done else*/ } @@ -433,11 +426,9 @@ static void build_connection_block_interc_bitstream( static void build_connection_block_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& cb_configurable_block, - const ModuleManager& module_manager, - const ModuleNameMap& module_name_map, - const CircuitLibrary& circuit_lib, - const MuxLibrary& mux_lib, const AtomContext& atom_ctx, - const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, + const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, const bool& verbose) { /* Find routing multiplexers on the sides of a Connection block where IPIN @@ -452,9 +443,9 @@ static void build_connection_block_bitstream( VTR_LOGV(verbose, "\tGenerating bitstream for IPIN at '%s' side\n", side_manager.to_string().c_str()); build_connection_block_interc_bitstream( - bitstream_manager, cb_configurable_block, module_manager, module_name_map, circuit_lib, - mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph, - rr_gsb, cb_ipin_side, inode, verbose); + bitstream_manager, cb_configurable_block, module_manager, + module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, + routing_annotation, rr_graph, rr_gsb, cb_ipin_side, inode, verbose); } } } @@ -593,9 +584,9 @@ static void build_connection_block_bitstreams( } build_connection_block_bitstream( - bitstream_manager, cb_configurable_block, module_manager, module_name_map, circuit_lib, - mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph, - rr_gsb, cb_type, verbose); + bitstream_manager, cb_configurable_block, module_manager, + module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, + routing_annotation, rr_graph, rr_gsb, cb_type, verbose); VTR_LOGV(verbose, "\tDone\n"); } @@ -725,9 +716,9 @@ void build_routing_bitstream( } build_switch_block_bitstream( - bitstream_manager, sb_configurable_block, module_manager, module_name_map, circuit_lib, - mux_lib, atom_ctx, device_annotation, routing_annotation, rr_graph, - rr_gsb, verbose); + bitstream_manager, sb_configurable_block, module_manager, + module_name_map, circuit_lib, mux_lib, atom_ctx, device_annotation, + routing_annotation, rr_graph, rr_gsb, verbose); VTR_LOGV(verbose, "\tDone\n"); }