From e39e9b8c26b3b21ddd6f3e8109b792e70c7d1773 Mon Sep 17 00:00:00 2001 From: Andrew Pond Date: Fri, 23 Jul 2021 12:08:32 -0600 Subject: [PATCH] finishing touches for PR --- .../misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys | 102 ------------ ...ite_full_testbench_example_script.openfpga | 3 +- .../openfpga_timing_annotation/README.md | 1 + ...tileable_adder_chain_mem1K_40nm_cell_sim.v | 151 +----------------- ...eable_adder_chain_skywater130nm_cell_sim.v | 58 ------- 5 files changed, 3 insertions(+), 312 deletions(-) delete mode 100644 openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys delete mode 100644 openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v diff --git a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys b/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys deleted file mode 100644 index e41446605..000000000 --- a/openfpga_flow/misc/ys_tmpl_yosys_vpr_dsp_dff_flow.ys +++ /dev/null @@ -1,102 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -${READ_VERILOG_FILE} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt - -opt_expr -opt_clean -check -opt -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff -wreduce t:$mul -techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -select a:mul2dsp -setattr -unset mul2dsp -opt_expr -fine -wreduce -select -clear -chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -techmap -alumacc -share -opt -fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -opt -fast -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - - -######################### -# Map muxes to pmuxes -######################### -techmap -map +/pmux2mux.v - -######################### -# Map flip-flops -######################### -techmap -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_rmdff -opt_clean -opt - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} diff --git a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga index c8f8105fb..e3e74a409 100644 --- a/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +++ b/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga @@ -71,5 +71,4 @@ write_analysis_sdc --file ./SDC_analysis exit # Note : -# To run verification at the end of the flow maintain source in ./SRC directory -{"mode":"full","isActive":false} \ No newline at end of file +# To run verification at the end of the flow maintain source in ./SRC directory \ No newline at end of file diff --git a/openfpga_flow/openfpga_timing_annotation/README.md b/openfpga_flow/openfpga_timing_annotation/README.md index 29bce8fb4..ae75506db 100644 --- a/openfpga_flow/openfpga_timing_annotation/README.md +++ b/openfpga_flow/openfpga_timing_annotation/README.md @@ -25,3 +25,4 @@ Bottom-right (Br): the pins of a tile are placed on the bottom side and right si GlobalTileClk: How many clocks are defined through global ports from physical tiles. is the number of clocks Other features are used in naming should be listed here. +tt/ff/ss: timing coners specified at the end of the file name. Each file under the specific architecture is tied to a certain corner, as the timing values will change with the corner. \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v index bef1c4b11..83b44875c 100644 --- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v +++ b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_mem1K_40nm_cell_sim.v @@ -55,153 +55,4 @@ module dpram_128x8 ( .raddr (raddr), .data_out (data_out) ); -endmodule - -//----------------------------- -// Native D-type flip-flop -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dff( - output reg Q, - input D, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C) - Q <= D; - 1'b1: - always @(negedge C) - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-high asynchronous reset -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffr( - output reg Q, - input D, - input R, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or posedge R) - if (R == 1'b1) - Q <= 1'b0; - else - Q <= D; - 1'b1: - always @(negedge C or posedge R) - if (R == 1'b1) - Q <= 1'b0; - else - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-high asynchronous set -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffs( - output reg Q, - input D, - input S, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or posedge S) - if (S == 1'b1) - Q <= 1'b1; - else - Q <= D; - 1'b1: - always @(negedge C or posedge S) - if (S == 1'b1) - Q <= 1'b1; - else - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-low asynchronous reset -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffrn( - output reg Q, - input D, - input RN, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or negedge RN) - if (RN == 1'b0) - Q <= 1'b0; - else - Q <= D; - 1'b1: - always @(negedge C or negedge RN) - if (RN == 1'b0) - Q <= 1'b0; - else - Q <= D; - endcase -endmodule - -//----------------------------- -// D-type flip-flop with active-low asynchronous set -//----------------------------- -(* abc9_flop, lib_whitebox *) -module dffsn( - output reg Q, - input D, - input SN, - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C -); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - initial Q = INIT; - case(|IS_C_INVERTED) - 1'b0: - always @(posedge C or negedge SN) - if (SN == 1'b0) - Q <= 1'b1; - else - Q <= D; - 1'b1: - always @(negedge C or negedge SN) - if (SN == 1'b0) - Q <= 1'b1; - else - Q <= D; - endcase -endmodule - +endmodule \ No newline at end of file diff --git a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v b/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v deleted file mode 100644 index 9ec66e6ee..000000000 --- a/openfpga_flow/openfpga_yosys_techlib/k6_frac_N10_tileable_adder_chain_skywater130nm_cell_sim.v +++ /dev/null @@ -1,58 +0,0 @@ -//----------------------------- -// Dual-port RAM 128x8 bit (1Kbit) -// Core logic -//----------------------------- -module dpram_128x8_core ( - input wclk, - input wen, - input [0:6] waddr, - input [0:7] data_in, - input rclk, - input ren, - input [0:6] raddr, - output [0:7] data_out ); - - reg [0:7] ram[0:127]; - reg [0:7] internal; - - assign data_out = internal; - - always @(posedge wclk) begin - if(wen) begin - ram[waddr] <= data_in; - end - end - - always @(posedge rclk) begin - if(ren) begin - internal <= ram[raddr]; - end - end - -endmodule - -//----------------------------- -// Dual-port RAM 128x8 bit (1Kbit) wrapper -// where the read clock and write clock -// are combined to a unified clock -//----------------------------- -module dpram_128x8 ( - input clk, - input wen, - input ren, - input [0:6] waddr, - input [0:6] raddr, - input [0:7] data_in, - output [0:7] data_out ); - - dpram_128x8_core memory_0 ( - .wclk (clk), - .wen (wen), - .waddr (waddr), - .data_in (data_in), - .rclk (clk), - .ren (ren), - .raddr (raddr), - .data_out (data_out) ); - -endmodule