From 35af0dd676c478b97b106f376a9379552744b7fa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 16:34:43 -0600
Subject: [PATCH 001/148] streamline fabric bitstream file format

---
 .../src/bitstream_manager_utils.cpp           | 17 +++++++++++
 .../src/bitstream_manager_utils.h             |  3 ++
 .../write_xml_fabric_bitstream.cpp            | 28 ++++++++-----------
 3 files changed, 32 insertions(+), 16 deletions(-)

diff --git a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp
index 1225602ef..8968b8d1c 100644
--- a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp
+++ b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.cpp
@@ -55,4 +55,21 @@ std::vector<ConfigBlockId> find_bitstream_manager_top_blocks(const BitstreamMana
   return top_blocks;
 }
 
+/********************************************************************
+ * Find the index of a configuration bit in the children bits of its parent block
+ *******************************************************************/
+size_t find_bitstream_manager_config_bit_index_in_parent_block(const BitstreamManager& bitstream_manager,
+                                                               const ConfigBitId& bit_id) {
+  size_t curr_index = 0;
+  for (const ConfigBitId& cand_bit : bitstream_manager.block_bits(bitstream_manager.bit_parent_block(bit_id))) {
+    if (cand_bit == bit_id) {
+      break;
+    }
+    curr_index++;
+  }
+
+  return curr_index;
+}
+
+
 } /* end namespace openfpga */
diff --git a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h
index 4c8b26ad2..328394b01 100644
--- a/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h
+++ b/libopenfpga/libfpgabitstream/src/bitstream_manager_utils.h
@@ -19,6 +19,9 @@ std::vector<ConfigBlockId> find_bitstream_manager_block_hierarchy(const Bitstrea
 
 std::vector<ConfigBlockId> find_bitstream_manager_top_blocks(const BitstreamManager& bitstream_manager);
 
+size_t find_bitstream_manager_config_bit_index_in_parent_block(const BitstreamManager& bitstream_manager,
+                                                               const ConfigBitId& bit_id);
+
 } /* end namespace openfpga */
 
 #endif
diff --git a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
index b1d5aeebe..b4d9cbebd 100644
--- a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
@@ -77,30 +77,26 @@ int write_fabric_config_bit_to_xml_file(std::fstream& fp,
   }
 
   write_tab_to_file(fp, 1);
-  fp << "<bit id=\"" << size_t(fabric_bit) << "\" ";
-  fp << "value=\"";
+  fp << "<bit id=\"" << size_t(fabric_bit) << "\"";
+  fp << " value=\"";
   fp << bitstream_manager.bit_value(fabric_bitstream.config_bit(fabric_bit));
-  fp << "\">\n";
+  fp << "\"";
 
   /* Output hierarchy of this parent*/
   const ConfigBitId& config_bit = fabric_bitstream.config_bit(fabric_bit);
   const ConfigBlockId& config_block = bitstream_manager.bit_parent_block(config_bit);
   std::vector<ConfigBlockId> block_hierarchy = find_bitstream_manager_block_hierarchy(bitstream_manager, config_block); 
-  write_tab_to_file(fp, 2);
-  fp << "<hierarchy>\n";
-  size_t hierarchy_counter = 0;
+  std::string hie_path;
   for (const ConfigBlockId& temp_block : block_hierarchy) {
-    write_tab_to_file(fp, 3);
-    fp << "<instance level=\"" << hierarchy_counter << "\"";
-    if (0 < bitstream_manager.block_bits(temp_block).size()) {
-      fp << " width=\"" << bitstream_manager.block_bits(temp_block).size() << "\"";
-    }
-    fp << " name=\"" << bitstream_manager.block_name(temp_block) << "\"";
-    fp << "/>\n";
-    hierarchy_counter++;
+    hie_path += bitstream_manager.block_name(temp_block);
+    hie_path += std::string(".");
   }
-  write_tab_to_file(fp, 2);
-  fp << "</hierarchy>\n";
+  hie_path += generate_configurable_memory_data_out_name();
+  hie_path += std::string("[");
+  hie_path += std::to_string(find_bitstream_manager_config_bit_index_in_parent_block(bitstream_manager, config_bit));
+  hie_path += std::string("]");
+
+  fp << " path=\"" << hie_path << "\"/>\n";
 
   switch (config_type) {
   case CONFIG_MEM_STANDALONE: 

From f773491f871d19bd4d9132520e6fc8c66f01c14b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 16:37:10 -0600
Subject: [PATCH 002/148] update documentation to sync with the new fabric
 bitstream format

---
 .../fabric_dependent_bitstream.rst            | 35 +++----------------
 1 file changed, 4 insertions(+), 31 deletions(-)

diff --git a/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst b/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
index 131d0ce57..825760a5e 100644
--- a/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
+++ b/docs/source/manual/fpga_bitstream/fabric_dependent_bitstream.rst
@@ -67,26 +67,13 @@ In principle, the file consist a number of XML node ``<bit>``, each bit contains
 
 - ``value``: The configuration bit value.
 
-  - ``hierarchy`` represents the location of this block in FPGA fabric.
-    The hierachy includes the full hierarchy of this block
-
-    - ``instance`` denotes the instance name which you can find in the fabric netlists
-
-    - ``level`` denotes the depth of the block in the hierarchy
-
-    - ``width`` denotes the number of configuration bits under the instance. Typically, only leaf instance has this attribute.
+- ``path`` represents the location of this block in FPGA fabric, i.e., the full path in the hierarchy of FPGA fabric.
 
 A quick example:
 
 .. code-block:: xml
 
-  <bit id="0" value="1">
-    <hierarchy>
-      <instance level="0" name="fpga_top"/>
-      <instance level="1" name="grid_clb_1__2_"/>
-      <instance level="2" name="logical_tile_clb_mode_clb__0"/>
-      <instance level="3" width="10" name="mem_fle_9_in_5"/>
-    </hierarchy>
+  <bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
   </bit>
 
 Other information may depend on the type of configuration procotol.
@@ -101,14 +88,7 @@ Other information may depend on the type of configuration procotol.
 
   .. code-block:: xml
 
-    <bit id="0" value="1">
-      <hierarchy>
-        <instance level="0" name="fpga_top"/>
-        <instance level="1" name="grid_io_bottom_1__0_"/>
-        <instance level="2" name="logical_tile_io_mode_io__0"/>
-        <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-        <instance level="4" width="1" name="iopad_sram_blwl_mem"/>
-      </hierarchy>
+    <bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
       <bl address="000000"/>
       <wl address="000000"/>
     </bit>
@@ -121,13 +101,6 @@ Other information may depend on the type of configuration procotol.
 
   .. code-block:: xml
 
-    <bit id="0" value="1">
-      <hierarchy>
-        <instance level="0" name="fpga_top"/>
-        <instance level="1" name="grid_io_bottom_1__0_"/>
-        <instance level="2" name="logical_tile_io_mode_io__0"/>
-        <instance level="3" name="logical_tile_io_mode_physical__iopad_0"/>
-        <instance level="4" width="1" name="iopad_config_latch_mem"/>
-      </hierarchy>
+    <bit id="0" value="1" path="fpga_top.grid_clb_1__2_.logical_tile_clb_mode_clb__0.mem_fle_9_in_5.mem_out[0]"/>
       <frame address="0000000000000000"/>
     </bit>

From 5595ee9052f38347a4481076009e7056a713d41d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 16:53:29 -0600
Subject: [PATCH 003/148] refine the test case for load external arch bitstream

---
 .../config/task.conf                                | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
index 4db289d23..2d7eb177f 100644
--- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
@@ -13,7 +13,7 @@ power_analysis = true
 spice_output=false
 verilog_output=true
 timeout_each_job = 20*60
-fpga_flow=yosys_vpr
+fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga
@@ -25,10 +25,17 @@ openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_b
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = and2
+bench0_top = or2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act
+########################
+# Use a different verilog as reference here
+# This verilog is consistent with the external architecture bitstream generated above
+# As such, we can test if the bitstream database is indeed overwritten by another benchmark
+# which is different than the one given to VPR
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

From 9add82148f211a31a349f670b3340f405246ea05 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 17:05:46 -0600
Subject: [PATCH 004/148] refactored CI for split regression tests in terms of
 OpenFPGA tools

---
 .travis.yml                                   | 20 ++++++++++++++++++-
 .travis/basic_reg_test.sh                     |  9 ---------
 .travis/fpga_bitstream_reg_test.sh            | 16 +++++++++++++++
 .travis/fpga_sdc_reg_test.sh                  | 16 +++++++++++++++
 .travis/fpga_spice_reg_test.sh                | 16 +++++++++++++++
 ...g_reg_test.sh => fpga_verilog_reg_test.sh} |  8 ++++----
 6 files changed, 71 insertions(+), 14 deletions(-)
 create mode 100755 .travis/fpga_bitstream_reg_test.sh
 create mode 100755 .travis/fpga_sdc_reg_test.sh
 create mode 100755 .travis/fpga_spice_reg_test.sh
 rename .travis/{verilog_reg_test.sh => fpga_verilog_reg_test.sh} (94%)

diff --git a/.travis.yml b/.travis.yml
index ca370367a..bf9c42724 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -96,7 +96,25 @@ jobs:
       name: "FPGA-Verilog regression tests"
       script:
         - source .travis/build.sh
-        - source .travis/verilog_reg_test.sh
+        - source .travis/fpga_verilog_reg_test.sh
+
+    - stage: Test
+      name: "FPGA-Bitstream regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/fpga_bitstream_reg_test.sh
+
+    - stage: Test
+      name: "FPGA-SDC regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/fpga_sdc_reg_test.sh
+
+    - stage: Test
+      name: "FPGA-SPICE regression tests"
+      script:
+        - source .travis/build.sh
+        - source .travis/fpga_spice_reg_test.sh
 
 #after_failure:
 #  - .travis/after_failure.sh
diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index b794858d9..b8f6e2efd 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -35,16 +35,7 @@ python3 openfpga_flow/scripts/run_fpga_task.py generate_fabric --debug --show_th
 echo -e "Testing Verilog testbench generation only";
 python3 openfpga_flow/scripts/run_fpga_task.py generate_testbench --debug --show_thread_logs
 
-echo -e "Testing bitstream generation only";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs
-
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug --show_thread_logs
 
-echo -e "Testing SDC generation with time units";
-python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs
-
-echo -e "Testing FPGA-SPICE with netlist generation";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
-
 end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_bitstream_reg_test.sh b/.travis/fpga_bitstream_reg_test.sh
new file mode 100755
index 000000000..e2787f78f
--- /dev/null
+++ b/.travis/fpga_bitstream_reg_test.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+
+start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-Bitstream regression tests";
+
+echo -e "Testing bitstream generation only";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs
+
+end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_sdc_reg_test.sh b/.travis/fpga_sdc_reg_test.sh
new file mode 100755
index 000000000..984199312
--- /dev/null
+++ b/.travis/fpga_sdc_reg_test.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+
+start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-SDC regression tests";
+
+echo -e "Testing SDC generation with time units";
+python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs
+
+end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_spice_reg_test.sh b/.travis/fpga_spice_reg_test.sh
new file mode 100755
index 000000000..8856d3ec8
--- /dev/null
+++ b/.travis/fpga_spice_reg_test.sh
@@ -0,0 +1,16 @@
+#!/bin/bash
+
+set -e
+
+start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
+cd ${TRAVIS_BUILD_DIR}
+
+###############################################
+# OpenFPGA Shell with VPR8
+##############################################
+echo -e "FPGA-SPICE regression tests";
+
+echo -e "Testing FPGA-SPICE with netlist generation";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_spice/generate_spice --debug --show_thread_logs
+
+end_section "OpenFPGA.TaskTun"
diff --git a/.travis/verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
similarity index 94%
rename from .travis/verilog_reg_test.sh
rename to .travis/fpga_verilog_reg_test.sh
index 18ffe91e5..c9cab90f7 100755
--- a/.travis/verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -8,7 +8,7 @@ cd ${TRAVIS_BUILD_DIR}
 ###############################################
 # OpenFPGA Shell with VPR8
 ##############################################
-echo -e "OpenFPGA Feature Testing for Verilog-to-Verification";
+echo -e "FPGA-Verilog Feature Tests";
 
 echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
 python3 openfpga_flow/scripts/run_fpga_task.py lut_design/single_mode --debug --show_thread_logs
@@ -46,13 +46,13 @@ python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/register_chain --deb
 echo -e "Testing Verilog generation with scan chain across an FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/scan_chain --debug --show_thread_logs
 
-echo -e "Testing Verilog generation with routing mutliplexers implemented by tree structure";
+echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
 python3 openfpga_flow/scripts/run_fpga_task.py mux_design/tree_structure --debug --show_thread_logs
 
-echo -e "Testing Verilog generation with routing mutliplexers implemented by standard cell MUX2";
+echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
 python3 openfpga_flow/scripts/run_fpga_task.py mux_design/stdcell_mux2 --debug --show_thread_logs
 
-echo -e "Testing Verilog generation with routing mutliplexers implemented by local encoders";
+echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
 python3 openfpga_flow/scripts/run_fpga_task.py mux_design/local_encoder --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with behavioral description";

From 50cc4dfba3d6a835800538dc0ae65877af42346f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 17:18:59 -0600
Subject: [PATCH 005/148] classify regression test to dedicated categories

---
 .travis/basic_reg_test.sh                     | 28 +++++-----
 .travis/fpga_sdc_reg_test.sh                  |  2 +-
 .travis/fpga_verilog_reg_test.sh              | 52 +++++++++----------
 .../config/task.conf                          |  0
 .../configuration_chain/config/task.conf      |  0
 .../configuration_frame/config/task.conf      |  0
 .../fast_configuration_chain/config/task.conf |  0
 .../fast_configuration_frame/config/task.conf |  0
 .../fast_memory_bank/config/task.conf         |  0
 .../flatten_memory/config/task.conf           |  0
 .../memory_bank/config/task.conf              |  0
 .../generate_fabric/config/task.conf          |  0
 .../generate_testbench/config/task.conf       |  0
 .../configuration_chain/config/task.conf      |  0
 .../configuration_frame/config/task.conf      |  0
 .../flatten_memory/config/task.conf           |  0
 .../memory_bank/config/task.conf              |  0
 .../sdc_time_unit/config/task.conf            |  0
 .../behavioral_verilog/config/task.conf       |  0
 .../bram/dpram16k/config/task.conf            |  0
 .../bram/wide_dpram16k/config/task.conf       |  0
 .../depopulate_crossbar/config/task.conf      |  0
 .../duplicated_grid_pin/config/task.conf      |  0
 .../fabric_chain/adder_chain/config/task.conf |  0
 .../register_chain/config/task.conf           |  0
 .../fabric_chain/scan_chain/config/task.conf  |  0
 .../generate_random_key/config/task.conf      |  0
 .../generate_vanilla_key/config/task.conf     |  0
 .../load_external_key/config/task.conf        |  0
 .../config/task.conf                          | 19 +++----
 .../flatten_routing/config/task.conf          |  0
 .../hard_adder/config/task.conf               |  0
 .../implicit_verilog/config/task.conf         |  0
 .../io/aib/config/task.conf                   |  0
 .../io/multi_io_capacity/config/task.conf     |  0
 .../io/reduced_io/config/task.conf            |  0
 .../lut_design/frac_lut/config/task.conf      |  0
 .../intermediate_buffer/config/task.conf      |  0
 .../lut_design/single_mode/config/task.conf   |  0
 .../mux_design/local_encoder/config/task.conf |  0
 .../mux_design/stdcell_mux2/config/task.conf  |  0
 .../tree_structure/config/task.conf           |  0
 .../power_gated_inverter/config/task.conf     |  0
 .../spypad/config/task.conf                   |  0
 .../untileable/config/task.conf               |  0
 45 files changed, 51 insertions(+), 50 deletions(-)
 rename openfpga_flow/tasks/{ => basic_tests}/fixed_simulation_settings/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/configuration_chain/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/configuration_frame/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/fast_configuration_chain/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/fast_configuration_frame/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/fast_memory_bank/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/flatten_memory/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/full_testbench/memory_bank/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/generate_fabric/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/generate_testbench/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/configuration_chain/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/configuration_frame/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/flatten_memory/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => basic_tests}/preconfig_testbench/memory_bank/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_sdc}/sdc_time_unit/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/behavioral_verilog/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/bram/dpram16k/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/bram/wide_dpram16k/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/depopulate_crossbar/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/duplicated_grid_pin/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_chain/adder_chain/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_chain/register_chain/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_chain/scan_chain/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_key/generate_random_key/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_key/generate_vanilla_key/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/fabric_key/load_external_key/config/task.conf (100%)
 rename openfpga_flow/tasks/{ncounter => fpga_verilog/fabric_key/load_external_key_cc_fpga}/config/task.conf (57%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/flatten_routing/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/hard_adder/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/implicit_verilog/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/io/aib/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/io/multi_io_capacity/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/io/reduced_io/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/lut_design/frac_lut/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/lut_design/intermediate_buffer/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/lut_design/single_mode/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/mux_design/local_encoder/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/mux_design/stdcell_mux2/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/mux_design/tree_structure/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/power_gated_design/power_gated_inverter/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/spypad/config/task.conf (100%)
 rename openfpga_flow/tasks/{ => fpga_verilog}/untileable/config/task.conf (100%)

diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index b8f6e2efd..ff29f7b71 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -11,31 +11,31 @@ cd ${TRAVIS_BUILD_DIR}
 echo -e "Basic regression tests";
 
 echo -e "Testing configuration chain of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/configuration_chain --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_configuration_chain --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
 
 echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/configuration_frame --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_configuration_frame --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
 echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/fast_memory_bank --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
 
 echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py full_testbench/flatten_memory --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py preconfig_testbench/flatten_memory --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
 
 echo -e "Testing fabric Verilog generation only";
-python3 openfpga_flow/scripts/run_fpga_task.py generate_fabric --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs
 
 echo -e "Testing Verilog testbench generation only";
-python3 openfpga_flow/scripts/run_fpga_task.py generate_testbench --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --debug --show_thread_logs
 
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
-python3 openfpga_flow/scripts/run_fpga_task.py fixed_simulation_settings --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_sdc_reg_test.sh b/.travis/fpga_sdc_reg_test.sh
index 984199312..70dd34809 100755
--- a/.travis/fpga_sdc_reg_test.sh
+++ b/.travis/fpga_sdc_reg_test.sh
@@ -11,6 +11,6 @@ cd ${TRAVIS_BUILD_DIR}
 echo -e "FPGA-SDC regression tests";
 
 echo -e "Testing SDC generation with time units";
-python3 openfpga_flow/scripts/run_fpga_task.py sdc_time_unit --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_sdc/sdc_time_unit --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"
diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index c9cab90f7..7ee1a5095 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -11,80 +11,80 @@ cd ${TRAVIS_BUILD_DIR}
 echo -e "FPGA-Verilog Feature Tests";
 
 echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
-python3 openfpga_flow/scripts/run_fpga_task.py lut_design/single_mode --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
 
 echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
-python3 openfpga_flow/scripts/run_fpga_task.py lut_design/frac_lut --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut --debug --show_thread_logs
 
 echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
-python3 openfpga_flow/scripts/run_fpga_task.py lut_design/intermediate_buffer --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with VPR's untileable routing architecture ";
-python3 openfpga_flow/scripts/run_fpga_task.py untileable --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/untileable --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with hard adder chain in CLBs ";
-python3 openfpga_flow/scripts/run_fpga_task.py hard_adder --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/hard_adder --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with 16k block RAMs ";
-python3 openfpga_flow/scripts/run_fpga_task.py bram/dpram16k --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/dpram16k --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with 16k block RAMs spanning two columns ";
-python3 openfpga_flow/scripts/run_fpga_task.py bram/wide_dpram16k --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/bram/wide_dpram16k --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with different I/O capacities on each side of an FPGA ";
-python3 openfpga_flow/scripts/run_fpga_task.py io/multi_io_capacity --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/multi_io_capacity --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with I/Os only on left and right sides of an FPGA ";
-python3 openfpga_flow/scripts/run_fpga_task.py io/reduced_io --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/io/reduced_io --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with adder chain across an FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/adder_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/adder_chain --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with shift register chain across an FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/register_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/register_chain --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with scan chain across an FPGA";
-python3 openfpga_flow/scripts/run_fpga_task.py fabric_chain/scan_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_chain/scan_chain --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with routing multiplexers implemented by tree structure";
-python3 openfpga_flow/scripts/run_fpga_task.py mux_design/tree_structure --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/tree_structure --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with routing multiplexers implemented by standard cell MUX2";
-python3 openfpga_flow/scripts/run_fpga_task.py mux_design/stdcell_mux2 --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_mux2 --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
-python3 openfpga_flow/scripts/run_fpga_task.py mux_design/local_encoder --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with behavioral description";
-python3 openfpga_flow/scripts/run_fpga_task.py behavioral_verilog --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
 
 echo -e "Testing implicit Verilog generation";
-python3 openfpga_flow/scripts/run_fpga_task.py implicit_verilog --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/implicit_verilog --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with flatten routing modules";
-python3 openfpga_flow/scripts/run_fpga_task.py flatten_routing --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/flatten_routing --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with duplicated grid output pins";
-python3 openfpga_flow/scripts/run_fpga_task.py duplicated_grid_pin --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/duplicated_grid_pin --debug --show_thread_logs
 
 echo -e "Testing Verilog generation with spy output pads";
-python3 openfpga_flow/scripts/run_fpga_task.py spypad --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/spypad --debug --show_thread_logs
 
 echo -e "Testing Secured FPGA fabrics";
-python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_vanilla_key --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/generate_random_key --debug --show_thread_logs
-python3 openfpga_flow/scripts/run_fpga_task.py fabric_key/load_external_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_vanilla_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/generate_random_key --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fabric_key/load_external_key --debug --show_thread_logs
 
 echo -e "Testing Power-gating designs";
-python3 openfpga_flow/scripts/run_fpga_task.py power_gated_design/power_gated_inverter --show_thread_logs --debug
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/power_gated_inverter --show_thread_logs --debug
 
 echo -e "Testing Depopulated crossbar in local routing";
-python3 openfpga_flow/scripts/run_fpga_task.py depopulate_crossbar --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
 
 # Verify MCNC big20 benchmark suite with ModelSim 
 # Please make sure you have ModelSim installed in the environment
 # Otherwise, it will fail
-#python3 openfpga_flow/scripts/run_fpga_task.py mcnc_big20 --debug --show_thread_logs --maxthreads 20
+#python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mcnc_big20 --debug --show_thread_logs --maxthreads 20
 #python3 openfpga_flow/scripts/run_modelsim.py mcnc_big20 --run_sim 
 
 end_section "OpenFPGA.TaskTun"
diff --git a/openfpga_flow/tasks/fixed_simulation_settings/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fixed_simulation_settings/config/task.conf
rename to openfpga_flow/tasks/basic_tests/fixed_simulation_settings/config/task.conf
diff --git a/openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/full_testbench/configuration_chain/config/task.conf
rename to openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf
diff --git a/openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/full_testbench/configuration_frame/config/task.conf
rename to openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf
diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/full_testbench/fast_configuration_chain/config/task.conf
rename to openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf
diff --git a/openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/full_testbench/fast_configuration_frame/config/task.conf
rename to openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf
diff --git a/openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/full_testbench/fast_memory_bank/config/task.conf
rename to openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf
diff --git a/openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/full_testbench/flatten_memory/config/task.conf
rename to openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf
diff --git a/openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/full_testbench/memory_bank/config/task.conf
rename to openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf
diff --git a/openfpga_flow/tasks/generate_fabric/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/generate_fabric/config/task.conf
rename to openfpga_flow/tasks/basic_tests/generate_fabric/config/task.conf
diff --git a/openfpga_flow/tasks/generate_testbench/config/task.conf b/openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/generate_testbench/config/task.conf
rename to openfpga_flow/tasks/basic_tests/generate_testbench/config/task.conf
diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/preconfig_testbench/configuration_chain/config/task.conf
rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf
diff --git a/openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/preconfig_testbench/configuration_frame/config/task.conf
rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf
diff --git a/openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/preconfig_testbench/flatten_memory/config/task.conf
rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf
diff --git a/openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/preconfig_testbench/memory_bank/config/task.conf
rename to openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf
diff --git a/openfpga_flow/tasks/sdc_time_unit/config/task.conf b/openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/sdc_time_unit/config/task.conf
rename to openfpga_flow/tasks/fpga_sdc/sdc_time_unit/config/task.conf
diff --git a/openfpga_flow/tasks/behavioral_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/behavioral_verilog/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/behavioral_verilog/config/task.conf
diff --git a/openfpga_flow/tasks/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/bram/dpram16k/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf
diff --git a/openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/bram/wide_dpram16k/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf
diff --git a/openfpga_flow/tasks/depopulate_crossbar/config/task.conf b/openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/depopulate_crossbar/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/depopulate_crossbar/config/task.conf
diff --git a/openfpga_flow/tasks/duplicated_grid_pin/config/task.conf b/openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/duplicated_grid_pin/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/duplicated_grid_pin/config/task.conf
diff --git a/openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fabric_chain/adder_chain/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
diff --git a/openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fabric_chain/register_chain/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf
diff --git a/openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fabric_chain/scan_chain/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf
diff --git a/openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fabric_key/generate_random_key/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/fabric_key/generate_random_key/config/task.conf
diff --git a/openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fabric_key/generate_vanilla_key/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/fabric_key/generate_vanilla_key/config/task.conf
diff --git a/openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fabric_key/load_external_key/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf
diff --git a/openfpga_flow/tasks/ncounter/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf
similarity index 57%
rename from openfpga_flow/tasks/ncounter/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf
index 75af20185..5931a4a13 100644
--- a/openfpga_flow/tasks/ncounter/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf
@@ -16,22 +16,23 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/mcnc_example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml
-external_fabric_key_file=
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=/var/tmp/AA_SC/ncounter_task/Ncounter.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = Ncounter
-bench0_act = /var/tmp/AA_SC/ncounter_task/Ncounter.act
-bench0_verilog = /var/tmp/AA_SC/ncounter_task/Ncounter_output_verilog.v
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
 bench0_chan_width = 300
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
-vpr_fpga_verilog_formal_verification_top_netlist=
+#vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/flatten_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/flatten_routing/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf
diff --git a/openfpga_flow/tasks/hard_adder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/hard_adder/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/hard_adder/config/task.conf
diff --git a/openfpga_flow/tasks/implicit_verilog/config/task.conf b/openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/implicit_verilog/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/implicit_verilog/config/task.conf
diff --git a/openfpga_flow/tasks/io/aib/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/io/aib/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf
diff --git a/openfpga_flow/tasks/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/io/multi_io_capacity/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf
diff --git a/openfpga_flow/tasks/io/reduced_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/io/reduced_io/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf
diff --git a/openfpga_flow/tasks/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/lut_design/frac_lut/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf
diff --git a/openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/lut_design/intermediate_buffer/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/lut_design/intermediate_buffer/config/task.conf
diff --git a/openfpga_flow/tasks/lut_design/single_mode/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/lut_design/single_mode/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/lut_design/single_mode/config/task.conf
diff --git a/openfpga_flow/tasks/mux_design/local_encoder/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/mux_design/local_encoder/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/mux_design/local_encoder/config/task.conf
diff --git a/openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/mux_design/stdcell_mux2/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/mux_design/stdcell_mux2/config/task.conf
diff --git a/openfpga_flow/tasks/mux_design/tree_structure/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/mux_design/tree_structure/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/mux_design/tree_structure/config/task.conf
diff --git a/openfpga_flow/tasks/power_gated_design/power_gated_inverter/config/task.conf b/openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/power_gated_design/power_gated_inverter/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/power_gated_design/power_gated_inverter/config/task.conf
diff --git a/openfpga_flow/tasks/spypad/config/task.conf b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/spypad/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
diff --git a/openfpga_flow/tasks/untileable/config/task.conf b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/untileable/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf

From 9a7364c6e611c18079057bd61815808b21727211 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 19:22:36 -0600
Subject: [PATCH 006/148] bug fix in fabric bitstream XML syntax

---
 openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
index b4d9cbebd..32d5a209c 100644
--- a/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/write_xml_fabric_bitstream.cpp
@@ -96,7 +96,7 @@ int write_fabric_config_bit_to_xml_file(std::fstream& fp,
   hie_path += std::to_string(find_bitstream_manager_config_bit_index_in_parent_block(bitstream_manager, config_bit));
   hie_path += std::string("]");
 
-  fp << " path=\"" << hie_path << "\"/>\n";
+  fp << " path=\"" << hie_path << "\">\n";
 
   switch (config_type) {
   case CONFIG_MEM_STANDALONE: 

From 5d83abb2cf3b0b00a48c26d961a990f1682d13cb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 19:37:05 -0600
Subject: [PATCH 007/148] bug fix in read architecture bitstream and regression
 tests

---
 openfpga/src/base/openfpga_bitstream.cpp             |  2 +-
 .../micro_benchmark/or2/or2_load_bitstream.blif      | 12 ++++++++++++
 .../config/task.conf                                 |  6 ++++--
 3 files changed, 17 insertions(+), 3 deletions(-)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif

diff --git a/openfpga/src/base/openfpga_bitstream.cpp b/openfpga/src/base/openfpga_bitstream.cpp
index 138ee2032..c32e9ae87 100644
--- a/openfpga/src/base/openfpga_bitstream.cpp
+++ b/openfpga/src/base/openfpga_bitstream.cpp
@@ -38,7 +38,7 @@ int fpga_bitstream(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_read_file = cmd.option("read_file");
 
   if (true == cmd_context.option_enable(cmd, opt_read_file)) {
-    openfpga_ctx.mutable_bitstream_manager() = read_xml_architecture_bitstream(cmd_context.option_value(cmd, opt_write_file).c_str());
+    openfpga_ctx.mutable_bitstream_manager() = read_xml_architecture_bitstream(cmd_context.option_value(cmd, opt_read_file).c_str());
   } else {
     openfpga_ctx.mutable_bitstream_manager() = build_device_bitstream(g_vpr_ctx,
                                                                       openfpga_ctx,
diff --git a/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif b/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif
new file mode 100644
index 000000000..fc79555cb
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif
@@ -0,0 +1,12 @@
+# This BLIF is created to test the feature of
+# loading external bitstream files.
+# Therefore, its module name is and2 rather than or2
+# Please do NOT use this file is regular regression tests
+.model and2
+.inputs a b
+.outputs c
+
+.names a b c
+00 0
+
+.end
diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
index 2d7eb177f..d36f074ae 100644
--- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
@@ -25,10 +25,12 @@ openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_b
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2_load_bitstream.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = or2
+# We use a special BLIF file whose top module name is and2
+# in order to be consistent with the architecture bistream design name
+bench0_top = and2
 bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.act
 ########################
 # Use a different verilog as reference here

From 9809db01c52b0e8e60bec7331714cfd97cbe0bed Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 19:39:14 -0600
Subject: [PATCH 008/148] deploy load_arch_bitstream test case to CI

---
 .travis/fpga_bitstream_reg_test.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/fpga_bitstream_reg_test.sh b/.travis/fpga_bitstream_reg_test.sh
index e2787f78f..90044ed8e 100755
--- a/.travis/fpga_bitstream_reg_test.sh
+++ b/.travis/fpga_bitstream_reg_test.sh
@@ -13,4 +13,7 @@ echo -e "FPGA-Bitstream regression tests";
 echo -e "Testing bitstream generation only";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs
 
+echo -e "Testing loading architecture bitstream from an external file";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"

From a1568075596c3e945fb30d8a1ae3084abe651a2e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 27 Jul 2020 19:47:43 -0600
Subject: [PATCH 009/148] enrich basic regression tests to cover more critical
 microbenchmarks

---
 .../full_testbench/configuration_chain/config/task.conf   | 8 ++++++++
 .../full_testbench/configuration_frame/config/task.conf   | 8 ++++++++
 .../fast_configuration_chain/config/task.conf             | 8 ++++++++
 .../fast_configuration_frame/config/task.conf             | 8 ++++++++
 .../full_testbench/fast_memory_bank/config/task.conf      | 8 ++++++++
 .../full_testbench/flatten_memory/config/task.conf        | 8 ++++++++
 .../full_testbench/memory_bank/config/task.conf           | 8 ++++++++
 .../configuration_chain/config/task.conf                  | 8 ++++++++
 .../configuration_frame/config/task.conf                  | 8 ++++++++
 .../preconfig_testbench/flatten_memory/config/task.conf   | 8 ++++++++
 .../preconfig_testbench/memory_bank/config/task.conf      | 8 ++++++++
 11 files changed, 88 insertions(+)

diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf
index cb1eb9a5c..f2786dee3 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain/config/task.conf
@@ -25,10 +25,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf
index 04342ba43..ded20701d 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame/config/task.conf
@@ -25,10 +25,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf
index d0ab2bad6..0d98afa11 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf
@@ -26,10 +26,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf
index 5c1eed83a..3626d3e85 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf
@@ -25,10 +25,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf
index bfa88b66e..e669edf34 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf
@@ -25,10 +25,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf
index 00b210d8f..74cba9434 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/full_testbench/flatten_memory/config/task.conf
@@ -25,10 +25,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf
index 6e48c7da7..5da25a81e 100644
--- a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank/config/task.conf
@@ -25,10 +25,18 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf
index e6c0caea0..fd40bb331 100644
--- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain/config/task.conf
@@ -25,11 +25,19 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
 vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf
index ecf61f537..8a82fbb57 100644
--- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_frame/config/task.conf
@@ -25,11 +25,19 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
 vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf
index 5ce4abf20..513ac66d4 100644
--- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/flatten_memory/config/task.conf
@@ -25,11 +25,19 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
 vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf
index a99aa4e24..a8cfe8b50 100644
--- a/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/memory_bank/config/task.conf
@@ -25,11 +25,19 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
 
 [SYNTHESIS_PARAM]
 bench0_top = and2
 bench0_chan_width = 300
 
+bench1_top = or2
+bench1_chan_width = 300
+
+bench2_top = and2_latch
+bench2_chan_width = 300
+
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=
 vpr_fpga_verilog_formal_verification_top_netlist=

From 534c609e17dce1d07539b9e7729e444d7fd79814 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jul 2020 11:51:50 -0600
Subject: [PATCH 010/148] add fixed layouts to a flagship architecture to test
 bitstream generation runtime

---
 ...adder_register_scan_chain_depop50_40nm.xml | 28 +++++++++++++++----
 1 file changed, 22 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
index 174649d93..35079cc2d 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
@@ -143,18 +143,34 @@
     -->
   <layout tileable="true">
     <auto_layout aspect_ratio="1.0">
-    <!-- Apply a fixed layout of 2x2 core array.
-         VPR8 considers the I/O ring in the array size
-         Therefore the height and width are both 4
-      -->
-    <!-- fixed_layout name="32x32" width="34" height="34" -->
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
       <corners type="EMPTY" priority="101"/>
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
-    <!-- /fixed_layout -->
     </auto_layout>
+    <!-- Apply a fixed layout of 96x96 core array.
+         VPR8 considers the I/O ring in the array size
+         Therefore the height and width are both 34
+      -->
+    <fixed_layout name="96x96" width="98" height="98">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- Apply a fixed layout of 48x48 core array.
+         VPR8 considers the I/O ring in the array size
+         Therefore the height and width are both 34
+      -->
+    <fixed_layout name="48x48" width="50" height="50">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
   </layout>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>

From f33422d4d730d08a020b57e6c181f93b15593461 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jul 2020 12:38:42 -0600
Subject: [PATCH 011/148] add regression test to track runtime on big fpga
 devices using practical benchmarks

---
 .travis/fpga_bitstream_reg_test.sh            |  2 +-
 ...tstream_fix_device_example_script.openfpga | 51 +++++++++++++++++++
 .../RISC_posedge_clk/{ => rtl}/ALU.v          |  0
 .../RISC_posedge_clk/{ => rtl}/Controller.v   |  0
 .../RISC_posedge_clk/{ => rtl}/IR.v           |  0
 .../RISC_posedge_clk/{ => rtl}/Memory.v       |  0
 .../RISC_posedge_clk/{ => rtl}/Mux_31.v       |  0
 .../RISC_posedge_clk/{ => rtl}/Mux_51.v       |  0
 .../RISC_posedge_clk/{ => rtl}/PC.v           |  0
 .../{ => rtl}/RISC_core_mem_top.v             |  0
 .../{ => rtl}/RISC_core_top.v                 |  0
 .../RISC_posedge_clk/{ => rtl}/Reg_1bit.v     |  0
 .../RISC_posedge_clk/{ => rtl}/Reg_8bit.v     |  0
 .../{ => testbench}/RISC_testbench.v          |  0
 .../micro_benchmark/SAPone/{ => rtl}/ACC.v    |  0
 .../micro_benchmark/SAPone/{ => rtl}/ADDSUB.v |  0
 .../SAPone/{ => rtl}/BRegister.v              |  0
 .../SAPone/{ => rtl}/Controller.v             |  0
 .../micro_benchmark/SAPone/{ => rtl}/IR.v     |  0
 .../micro_benchmark/SAPone/{ => rtl}/MAR.v    |  0
 .../SAPone/{ => rtl}/OutputRegister.v         |  0
 .../micro_benchmark/SAPone/{ => rtl}/PC.v     |  0
 .../micro_benchmark/SAPone/{ => rtl}/ROM.v    |  0
 .../micro_benchmark/SAPone/{ => rtl}/SAPone.v |  0
 .../SAPone/{ => testbench}/testSAPone.v       |  0
 .../device_48x48/config/task.conf             | 35 +++++++++++++
 .../device_96x96/config/task.conf             | 35 +++++++++++++
 .../{ => device_auto}/config/task.conf        |  0
 28 files changed, 122 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/ALU.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/Controller.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/IR.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/Memory.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/Mux_31.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/Mux_51.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/PC.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/RISC_core_mem_top.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/RISC_core_top.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/Reg_1bit.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => rtl}/Reg_8bit.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/{ => testbench}/RISC_testbench.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/ACC.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/ADDSUB.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/BRegister.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/Controller.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/IR.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/MAR.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/OutputRegister.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/PC.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/ROM.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => rtl}/SAPone.v (100%)
 rename openfpga_flow/benchmarks/micro_benchmark/SAPone/{ => testbench}/testSAPone.v (100%)
 create mode 100644 openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
 create mode 100644 openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf
 rename openfpga_flow/tasks/fpga_bitstream/generate_bitstream/{ => device_auto}/config/task.conf (100%)

diff --git a/.travis/fpga_bitstream_reg_test.sh b/.travis/fpga_bitstream_reg_test.sh
index 90044ed8e..dcce57081 100755
--- a/.travis/fpga_bitstream_reg_test.sh
+++ b/.travis/fpga_bitstream_reg_test.sh
@@ -11,7 +11,7 @@ cd ${TRAVIS_BUILD_DIR}
 echo -e "FPGA-Bitstream regression tests";
 
 echo -e "Testing bitstream generation only";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
 
 echo -e "Testing loading architecture bitstream from an external file";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga
new file mode 100644
index 000000000..9558a5944
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga
@@ -0,0 +1,51 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enabled frame view creation to save runtime and memory
+#    Note that this is turned on when bitstream generation 
+#    is the ONLY purpose of the flow!!!
+build_fabric --compress_routing --frame_view #--verbose
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Skip outputting the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose #--write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose 
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.txt --format plain_text
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/ALU.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/ALU.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/ALU.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Controller.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Controller.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Controller.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/IR.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/IR.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/IR.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Memory.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Memory.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Memory.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Mux_31.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_31.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Mux_31.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Mux_51.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Mux_51.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Mux_51.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/PC.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/PC.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/PC.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/RISC_core_mem_top.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_mem_top.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/RISC_core_mem_top.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/RISC_core_top.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_core_top.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/RISC_core_top.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Reg_1bit.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_1bit.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Reg_1bit.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Reg_8bit.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/Reg_8bit.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/Reg_8bit.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v b/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench/RISC_testbench.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/RISC_testbench.v
rename to openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/testbench/RISC_testbench.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/ACC.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/ACC.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/ACC.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/ADDSUB.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/ADDSUB.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/ADDSUB.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/BRegister.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/BRegister.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/BRegister.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/Controller.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/Controller.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/Controller.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/IR.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/IR.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/IR.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/MAR.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/MAR.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/MAR.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/OutputRegister.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/OutputRegister.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/OutputRegister.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/PC.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/PC.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/PC.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/ROM.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/ROM.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/ROM.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/SAPone.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/SAPone.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/SAPone.v
diff --git a/openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v b/openfpga_flow/benchmarks/micro_benchmark/SAPone/testbench/testSAPone.v
similarity index 100%
rename from openfpga_flow/benchmarks/micro_benchmark/SAPone/testSAPone.v
rename to openfpga_flow/benchmarks/micro_benchmark/SAPone/testbench/testSAPone.v
diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
new file mode 100644
index 000000000..911239184
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
@@ -0,0 +1,35 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+# Runtime of this bitstream generation should not exceed 3 minutes as a QoR requirement
+timeout_each_job = 3*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_route_chan_width=50
+openfpga_vpr_device_layout=48x48
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/*
+
+[SYNTHESIS_PARAM]
+bench0_top = SAPone
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf
new file mode 100644
index 000000000..97dcc465b
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_96x96/config/task.conf
@@ -0,0 +1,35 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+# Runtime of this bitstream generation should not exceed 6 minutes as a QoR requirement
+timeout_each_job = 6*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_route_chan_width=100
+openfpga_vpr_device_layout=96x96
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/RISC_posedge_clk/rtl/*.v
+
+[SYNTHESIS_PARAM]
+bench0_top = RISC_core_top
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_auto/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fpga_bitstream/generate_bitstream/config/task.conf
rename to openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_auto/config/task.conf

From 1e53d79c570b35d16b0a8ca093d37cd89dcbff5e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jul 2020 12:41:58 -0600
Subject: [PATCH 012/148] deploy large bitstream regression tests to CI

---
 .travis/fpga_bitstream_reg_test.sh | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/.travis/fpga_bitstream_reg_test.sh b/.travis/fpga_bitstream_reg_test.sh
index dcce57081..8b9b6c0f4 100755
--- a/.travis/fpga_bitstream_reg_test.sh
+++ b/.travis/fpga_bitstream_reg_test.sh
@@ -10,9 +10,16 @@ cd ${TRAVIS_BUILD_DIR}
 ##############################################
 echo -e "FPGA-Bitstream regression tests";
 
-echo -e "Testing bitstream generation only";
+echo -e "Testing bitstream generation for an auto-sized device";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_auto --debug --show_thread_logs
 
+
+echo -e "Testing bitstream generation for an 48x48 FPGA device";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_48x48 --debug --show_thread_logs
+
+echo -e "Testing bitstream generation for an 96x96 FPGA device";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/generate_bitstream/device_96x96 --debug --show_thread_logs
+
 echo -e "Testing loading architecture bitstream from an external file";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_bitstream/load_external_architecture_bitstream --debug --show_thread_logs
 

From cadf29022ebea8dcbb97d659ba133a95d5aeb6a0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 28 Jul 2020 13:44:06 -0600
Subject: [PATCH 013/148] add README to explain the organization of regression
 tests

---
 openfpga_flow/tasks/README.md | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 openfpga_flow/tasks/README.md

diff --git a/openfpga_flow/tasks/README.md b/openfpga_flow/tasks/README.md
new file mode 100644
index 000000000..930a2d4dd
--- /dev/null
+++ b/openfpga_flow/tasks/README.md
@@ -0,0 +1,23 @@
+# Regression tests for OpenFPGA
+The regression tests are grouped in category of OpenFPGA tools as well as integrated flows.
+The principle is that each OpenFPGA tool should have a set of regression tests.
+
+- compilation\_verfication: a quicktest after compilation
+
+- Basic regression tests should focus on fundamental flow integration, such as
+
+  - Yosys + VPR + OpenFPGA for a Verilog-to-Verification flow-run
+
+- FPGA-Verilog regression tests should focus on testing fabric correctness, such as 
+
+  - VPR + OpenFPGA integration for a BLIF-to-Verification flow-run
+
+
+- FPGA-Bitstream regression tests should focus on testing bitstream correctness and runtime on large devices and benchmark suites
+
+- FPGA-SDC regression test should focus on SDC file generation and necessary syntax check
+
+- FPGA-SPICE regression test should focus on SPICE netlist generation / compilation and SPICE simulations qwith QoR checks.
+
+
+Please keep this README up-to-date on the OpenFPGA tools

From 1ca28298687c4f74c697f7cecf188de45706651a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Aug 2020 13:54:26 -0600
Subject: [PATCH 014/148] update readme for vpr architecture naming

---
 openfpga_flow/vpr_arch/README.md | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga_flow/vpr_arch/README.md b/openfpga_flow/vpr_arch/README.md
index e56ccca4b..aad2c1421 100644
--- a/openfpga_flow/vpr_arch/README.md
+++ b/openfpga_flow/vpr_arch/README.md
@@ -1,17 +1,17 @@
 # Naming convention for VPR architecture files
 Please reveal the following architecture features in the names to help quickly spot architecture files.
 
-- k<lut\_size>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size.
-- frac: If fracturable LUT is used or not.
+- k<lut\_size>\_<frac>: Look-Up Table (LUT) size of FPGA. If you have fracturable LUTs or multiple LUT circuits, this should be largest input size. The keyword 'frac' is to specify if fracturable LUT is used or not.
 - N<le\_size>: Number of logic elements for a CLB. If you have multiple CLB architectures, this should be largest number.
 - tileable: If the routing architecture is tileable or not.
 - adder\_chain: If hard adder/carry chain is used inside CLBs
 - register\_chain: If shift register chain is used inside CLBs
 - scan\_chain: If scan chain testing infrastructure is used inside CLBs
-- <wide>\_mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword wide is to specify if the BRAM spanns more than 1 column.
+- <wide>\_<frac>\_mem<mem\_size>: If block RAM (BRAM) is used or not. If used, the memory size should be clarified here. The keyword 'wide' is to specify if the BRAM spans more than 1 column. The keyword 'frac' is to specify if the BRAM is fracturable to operate in different modes.
+- <wide>\_<frac>\_dsp<dsp\_size>: If Digital Signal Processor (DSP) is used or not. If used, the input size should be clarified here. The keyword 'wide' is to specify if the DSP spans more than 1 column. The keyword 'frac' is to specify if the DSP is fracturable to operate in different modes.
 - aib: If the Advanced Interface Bus (AIB) is used in place of some I/Os.
 - multi\_io\_capacity: If I/O capacity is different on each side of FPGAs.
 - reduced\_io: If I/Os only appear a certain or multiple sides of FPGAs 
-- <feature_size>: The technology node which the delay numbers are extracted from.
+- <feature\_size>: The technology node which the delay numbers are extracted from.
 
 Other features are used in naming should be listed here.

From cfd035bf8f3a0c65634c02ffeff4373ef8012656 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Aug 2020 14:33:51 -0600
Subject: [PATCH 015/148] update tutorials about the verilog-to-verification

---
 docs/source/tutorials/design_flow/index.rst                 | 4 ++--
 .../design_flow/{verilog_to_gds2.rst => verilog2gds2.rst}   | 0
 .../{blif_to_verification.rst => verilog2verification.rst}  | 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)
 rename docs/source/tutorials/design_flow/{verilog_to_gds2.rst => verilog2gds2.rst} (100%)
 rename docs/source/tutorials/design_flow/{blif_to_verification.rst => verilog2verification.rst} (98%)

diff --git a/docs/source/tutorials/design_flow/index.rst b/docs/source/tutorials/design_flow/index.rst
index e854a08c6..82a9ed3e4 100644
--- a/docs/source/tutorials/design_flow/index.rst
+++ b/docs/source/tutorials/design_flow/index.rst
@@ -7,6 +7,6 @@ Design Flows
 .. toctree::
    :maxdepth: 2
 
-   blif_to_verification
+   verilog2verification
 
-   verilog_to_gds2
+   verilog2gds2
diff --git a/docs/source/tutorials/design_flow/verilog_to_gds2.rst b/docs/source/tutorials/design_flow/verilog2gds2.rst
similarity index 100%
rename from docs/source/tutorials/design_flow/verilog_to_gds2.rst
rename to docs/source/tutorials/design_flow/verilog2gds2.rst
diff --git a/docs/source/tutorials/design_flow/blif_to_verification.rst b/docs/source/tutorials/design_flow/verilog2verification.rst
similarity index 98%
rename from docs/source/tutorials/design_flow/blif_to_verification.rst
rename to docs/source/tutorials/design_flow/verilog2verification.rst
index 26a0b87cf..505aa39c7 100644
--- a/docs/source/tutorials/design_flow/blif_to_verification.rst
+++ b/docs/source/tutorials/design_flow/verilog2verification.rst
@@ -1,7 +1,7 @@
-.. _from_blif_to_verification:
+.. _from_verilog_to_verification:
 
-From BLIF to Verification
--------------------------
+From Verilog to Verification
+----------------------------
 
 This tutorial will show an example how to 
   - generate Verilog netlists for a FPGA fabric

From f833e0ec66df540ea108108dfb9e1e17b34e453b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 17 Aug 2020 17:49:51 -0600
Subject: [PATCH 016/148] add a flagship architecture using fracturable memory
 and dsp

---
 ...n_frac_mem32K_frac_dsp36_40nm_openfpga.xml |  451 +++++
 ...dder_chain_frac_mem32K_frac_dsp36_40nm.xml | 1578 +++++++++++++++++
 2 files changed, 2029 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
 create mode 100644 openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
new file mode 100644
index 000000000..d47e396ee
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -0,0 +1,451 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="mult_36x36" prefix="mult_36x36" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mult_36x36.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mult_36x36.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="36"/>
+      <port type="input" prefix="b" size="36"/>
+      <port type="output" prefix="out" size="72"/>
+      <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="frac_mem_32k" prefix="frac_mem_32k" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/frac_mem_32k.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/frac_mem_32k.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="addr1" lib_name="addr_a" size="15"/>
+      <port type="input" prefix="addr2" lib_name="addr_b" size="15"/>
+      <port type="input" prefix="data1" lib_name="data_a" size="32"/>
+      <port type="input" prefix="data2" lib_name="data_b" size="32"/>
+      <port type="input" prefix="we1" lib_name="we_a" size="1"/>
+      <port type="input" prefix="we2" lib_name="we_b" size="1"/>
+      <port type="output" prefix="out1" lib_name="q_a" size="32"/>
+      <port type="output" prefix="out2" lib_name="q_b" size="32"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+      <!-- As a fracturable memory, it requires 4 configuration bits to operate in 13 different modes -->
+      <port type="sram" prefix="mode" size="4" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'n2_lut5' -->
+    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble6' -->
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block clb -->
+
+    <!-- physical pb_type binding in complex block dsp -->
+    <pb_type name="mult_36" physical_mode_name="mult_36x36" idle_mode_name="mult_36x36"/>
+    <!-- Bind the primitive pb_type in the physical mode to a circuit model --> 
+    <pb_type name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" circuit_model_name="mult_36x36" mode_bits="00"/>
+    <!-- Bind the 9x9 multiplier to the physical 36x36 multiplier
+         There are four 9x9 multipliers, each of which occupies part
+         of the input/output of the 36x36 multiplier
+      -->
+    <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
+      <port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
+      <port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
+      <port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
+    </pb_type>
+    <!-- Bind the 18x18 multiplier to the physical 36x36 multiplier
+         There are two 18x18 multipliers, each of which occupies part
+         of the input/output of the 36x36 multiplier
+      -->
+    <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
+      <port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
+      <port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
+      <port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>
+    </pb_type>
+    <!-- END physical pb_type binding in complex block dsp -->
+
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory" physical_mode_name="physical" idle_mode_name="physical"/>
+    <pb_type name="memory[physical].frac_mem_32k" circuit_model_name="frac_mem_32k" mode_bits="0000"/>
+    <!-- Bind the 512x64 single port RAM to the physical implementation -->
+    <pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
+      <port name="addr" physical_mode_port="addr1[0:8]"/>
+      <port name="data" physical_mode_port="data1 data2"/>
+      <port name="we" physical_mode_port="we1"/>
+      <port name="out" physical_mode_port="out1 out2"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 1024x32 single port RAM to the physical implementation -->
+    <pb_type name="memory[mem_1024x32_sp].mem_1024x32_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
+      <port name="addr" physical_mode_port="addr1[0:9]"/>
+      <port name="data" physical_mode_port="data1"/>
+      <port name="we" physical_mode_port="we1"/>
+      <port name="out" physical_mode_port="out1"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 2048x16 single port RAM to the physical implementation -->
+    <pb_type name="memory[mem_2048x16_sp].mem_2048x16_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0001">
+      <port name="addr" physical_mode_port="addr1[0:10]"/>
+      <port name="data" physical_mode_port="data1[0:15]"/>
+      <port name="we" physical_mode_port="we1"/>
+      <port name="out" physical_mode_port="out1[0:15]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 4096x8 single port RAM to the physical implementation -->
+    <pb_type name="memory[mem_4096x8_sp].mem_4096x8_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0010">
+      <port name="addr" physical_mode_port="addr1[0:11]"/>
+      <port name="data" physical_mode_port="data1[0:7]"/>
+      <port name="we" physical_mode_port="we1"/>
+      <port name="out" physical_mode_port="out1[0:7]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 8192x4 single port RAM to the physical implementation -->
+    <pb_type name="memory[mem_8192x4_sp].mem_8192x4_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0011">
+      <port name="addr" physical_mode_port="addr1[0:12]"/>
+      <port name="data" physical_mode_port="data1[0:3]"/>
+      <port name="we" physical_mode_port="we1"/>
+      <port name="out" physical_mode_port="out1[0:3]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 16384x2 single port RAM to the physical implementation -->
+    <pb_type name="memory[mem_16384x2_sp].mem_16384x2_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0100">
+      <port name="addr" physical_mode_port="addr1[0:13]"/>
+      <port name="data" physical_mode_port="data1[0:1]"/>
+      <port name="we" physical_mode_port="we1"/>
+      <port name="out" physical_mode_port="out1[0:1]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 32768x1 single port RAM to the physical implementation -->
+    <pb_type name="memory[mem_32768x1_sp].mem_32768x1_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0101">
+      <port name="addr" physical_mode_port="addr1[0:14]"/>
+      <port name="data" physical_mode_port="data1[0:0]"/>
+      <port name="we" physical_mode_port="we1"/>
+      <port name="out" physical_mode_port="out1[0:0]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 1024x32 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0110">
+      <port name="addr1" physical_mode_port="addr1[0:9]"/>
+      <port name="addr2" physical_mode_port="addr2[0:9]"/>
+      <port name="data1" physical_mode_port="data1[0:31]"/>
+      <port name="data2" physical_mode_port="data2[0:31]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:31]"/>
+      <port name="out2" physical_mode_port="out2[0:31]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 1024x32 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0111">
+      <port name="addr1" physical_mode_port="addr1[0:9]"/>
+      <port name="addr2" physical_mode_port="addr2[0:9]"/>
+      <port name="data1" physical_mode_port="data1[0:31]"/>
+      <port name="data2" physical_mode_port="data2[0:31]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:31]"/>
+      <port name="out2" physical_mode_port="out2[0:31]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 2048x16 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
+      <port name="addr1" physical_mode_port="addr1[0:10]"/>
+      <port name="addr2" physical_mode_port="addr2[0:10]"/>
+      <port name="data1" physical_mode_port="data1[0:15]"/>
+      <port name="data2" physical_mode_port="data2[0:15]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:15]"/>
+      <port name="out2" physical_mode_port="out2[0:15]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 4096x8 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
+      <port name="addr1" physical_mode_port="addr1[0:11]"/>
+      <port name="addr2" physical_mode_port="addr2[0:11]"/>
+      <port name="data1" physical_mode_port="data1[0:7]"/>
+      <port name="data2" physical_mode_port="data2[0:7]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:7]"/>
+      <port name="out2" physical_mode_port="out2[0:7]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 8192x4 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
+      <port name="addr1" physical_mode_port="addr1[0:12]"/>
+      <port name="addr2" physical_mode_port="addr2[0:12]"/>
+      <port name="data1" physical_mode_port="data1[0:3]"/>
+      <port name="data2" physical_mode_port="data2[0:3]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:3]"/>
+      <port name="out2" physical_mode_port="out2[0:3]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 16384x2 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
+      <port name="addr1" physical_mode_port="addr1[0:13]"/>
+      <port name="addr2" physical_mode_port="addr2[0:13]"/>
+      <port name="data1" physical_mode_port="data1[0:1]"/>
+      <port name="data2" physical_mode_port="data2[0:1]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:1]"/>
+      <port name="out2" physical_mode_port="out2[0:1]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- Bind the 32768x1 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
+      <port name="addr1" physical_mode_port="addr1[0:14]"/>
+      <port name="addr2" physical_mode_port="addr2[0:14]"/>
+      <port name="data1" physical_mode_port="data1[0:0]"/>
+      <port name="data2" physical_mode_port="data2[0:0]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:0]"/>
+      <port name="out2" physical_mode_port="out2[0:0]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
+    <!-- END physical pb_type binding in complex block memory -->
+  </pb_type_annotations>
+</openfpga_architecture>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
new file mode 100644
index 000000000..6acc37ba2
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
@@ -0,0 +1,1578 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain maximum delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). Minimum delay values are calculated based on the
+  ratios between maximum and minimum values in Stratix IV GX device. For routing, we took the 
+  average delay of H4 and V4 wires.  Rmetal and Cmetal values for the routing wires were obtained 
+  from work done by Charles Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal 
+  stack 40 nm routing) and take the R and C data from the ITRS roadmap. 
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  We use 40 inputs and 20 feedback lines in 
+  the cluster and a full crossbar, leading to 53:1 multiplexers in front of each BLE input.
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We require 60 such multiplexers, while Stratix IV requires 88 for its more
+  complex fracturable BLEs + the extra control signals. We justify this rough approximation as follows: 
+  The Stratix IV crossbar has more inputs (72 vs. 60) and 
+  outputs (88 vs. 60) than our full crossbar which should increase its area and delay, but the 
+  Stratix IV crossbar is also 50% sparse (each mux is 36:1 instead of 53:1) which should reduce its 
+  area and delay.  The total number of crossbar switch points is roughly similar between the two 
+  architectures (3160 for SIV and 3600 for the academic architecture below), so we use the area 
+  & delay of the Stratix IV crossbar as a rough approximation of our crossbar.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="multiply">
+      <input_ports>
+        <port name="a" combinational_sink_ports="out"/>
+        <port name="b" combinational_sink_ports="out"/>
+      </input_ports>
+      <output_ports>
+        <port name="out"/>
+      </output_ports>
+    </model>
+    <model name="single_port_ram">
+      <input_ports>
+        <port name="we" clock="clk"/>
+        <!-- control -->
+        <port name="addr" clock="clk"/>
+        <!-- address lines -->
+        <port name="data" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="clk" is_clock="1"/>
+        <!-- memories are often clocked -->
+      </input_ports>
+      <output_ports>
+        <port name="out" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <port name="we1" clock="clk"/>
+        <!-- write enable -->
+        <port name="we2" clock="clk"/>
+        <!-- write enable -->
+        <port name="addr1" clock="clk"/>
+        <!-- address lines -->
+        <port name="addr2" clock="clk"/>
+        <!-- address lines -->
+        <port name="data1" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="data2" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="clk" is_clock="1"/>
+        <!-- memories are often clocked -->
+      </input_ports>
+      <output_ports>
+        <port name="out1" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="out2" clock="clk"/>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+      </output_ports>
+    </model>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- The original XML does have a default capacity (=1). Set 8 here for best architecture evaluation -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io" pin_mapping="direct"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb" pin_mapping="direct"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="mult_36" height="4" area="396000">
+      <equivalent_sites>
+        <site pb_type="mult_36" pin_mapping="direct"/>
+      </equivalent_sites>
+      <input name="a" num_pins="36"/>
+      <input name="b" num_pins="36"/>
+      <output name="out" num_pins="72"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+    <tile name="memory" height="6" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory" pin_mapping="direct"/>
+      </equivalent_sites>
+      <input name="addr1" num_pins="15"/>
+      <input name="addr2" num_pins="15"/>
+      <input name="data" num_pins="64"/>
+      <input name="we1" num_pins="1"/>
+      <input name="we2" num_pins="1"/>
+      <output name="out" num_pins="64"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="false">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="mult_36" startx="6" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="6" repeatx="8" starty="1" priority="19"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Maximum delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+
+		 Minimum delays are retrieved using a ratio of maximum and minimum times as seen in Quartus II
+		 in Stratix IV. The ratio of minimum value/maximum value is as follows:
+			inpad delay:  0.9239
+			outpad delay: 0.9545
+
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" min="3.92e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" min="1.331e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+       
+       <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+		   For the minimum delays, we have the delay through a connection block input mux +
+		   the crossbar in Stratix IV is 144. Subtracting the 72 ps leaves 72 ps remaining.
+           The max delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar. For the minimum delay,
+  		   the value in Stratix IV is 93 ps, subtracting the 24 ps leaves 69 ps.-->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" min="72e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" min="69e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+          </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" min="0.11e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define fracturable multiplier begin -->
+    <!-- This multiplier can operate as a 36x36 multiplier that can fracture to two 18x18 multipliers each of which can further fracture to two 9x9 multipliers 
+	   For delay modelling, the 36x36 DSP multiplier in Stratix IV has a maximum delay of 1.523 ns + 1.93 ns
+	    = 3.45 ns. The average difference between the maximum and minimum values of a dsp mac out in 36 bit multiply
+		mode is 0.51. Hence, the minimum delay is modeled as 0.776 ns + 0.984 ns = 1.760 ns.
+ 		The 18x18 mode doesn't need to sum four 18x18 multipliers, so it is a bit
+	   faster: 1.523 ns for the multiplier, and 1.09 ns for the multiplier output block.
+	    For the input and output interconnect delays, unlike Stratix IV, we don't
+	   have any routing/logic flexibility (crossbars) at the inputs.  There is some output muxing
+	   in Stratix IV and this architecture to select which multiplier outputs should go out (e.g.
+	   9x9 outputs, 18x18 or 36x36) so those are very close between the two architectures. 
+	   We take the conservative (slightly pessimistic)
+           approach modelling the input as the same as the Stratix IV input delay and the output delay the same as the Stratix IV DSP out delay.
+		   
+	   We estimate block area by using the published Stratix III data (which is architecturally identical to Stratix IV)
+	      (H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011) of 0.2623 
+		  mm^2 and scaling from 65 to 40 nm to obtain 0.0993 mm^2. That area is for a DSP block with approximately 2x the functionality of 
+		  the block we use (can implement two 36x36 multiplies instead of our 1, eight 18x18 multiplies instead of our 4, etc.). Hence we 
+		  divide the area by 2 to obtain 0.0497 mm^2. One minimum-width transistor units = 60 L^2 (where L = 40 nm), so is 518,000 MWTUS. 
+		  That area includes routing and the connection block input muxes.  Our DSP block is four 
+		  rows high, and hence includes four horizontal routing channel segments and four vertical ones, which is 4x the routing of a logic 
+		  block (single tile). It also includes 3.6x the outputs of a logic block, and 1.8x the inputs. Hence a slight overestimate of the routing
+		  area associated with our DSP block is four times that of a logic tile, where the routing area of a logic tile was calculated above (at W = 300)
+		  as 30481 MWTAs. Hence the (core, non-routing) area our DSP block is approximately 518,000 - 4 * 30,481 = 396,000 MWTUs.
+      -->
+    <pb_type name="mult_36">
+      <input name="a" num_pins="36"/>
+      <input name="b" num_pins="36"/>
+      <output name="out" num_pins="72"/>
+      <mode name="two_divisible_mult_18x18">
+        <pb_type name="divisible_mult_18x18" num_pb="2">
+          <input name="a" num_pins="18"/>
+          <input name="b" num_pins="18"/>
+          <output name="out" num_pins="36"/>
+          <!-- Model 9x9 delay and 18x18 delay as the same.  9x9 could be faster, but in Stratix IV
+	          isn't, presumably because the multiplier layout is really optimized for 18x18.
+		        -->
+          <mode name="two_mult_9x9">
+            <pb_type name="mult_9x9_slice" num_pb="2">
+              <input name="A_cfg" num_pins="9"/>
+              <input name="B_cfg" num_pins="9"/>
+              <output name="OUT_cfg" num_pins="18"/>
+              <pb_type name="mult_9x9" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="9"/>
+                <input name="b" num_pins="9"/>
+                <output name="out" num_pins="18"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_9x9.a" out_port="mult_9x9.out"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_9x9.b" out_port="mult_9x9.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_9x9_slice.A_cfg" output="mult_9x9.a">
+                </direct>
+                <direct name="b2b" input="mult_9x9_slice.B_cfg" output="mult_9x9.b">
+                </direct>
+                <direct name="out2out" input="mult_9x9.out" output="mult_9x9_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.45e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.45e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_9x9_slice[1:0].A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_9x9_slice[1:0].B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_9x9_slice[1:0].OUT_cfg" output="divisible_mult_18x18.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <mode name="mult_18x18">
+            <pb_type name="mult_18x18_slice" num_pb="1">
+              <input name="A_cfg" num_pins="18"/>
+              <input name="B_cfg" num_pins="18"/>
+              <output name="OUT_cfg" num_pins="36"/>
+              <pb_type name="mult_18x18" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="18"/>
+                <input name="b" num_pins="18"/>
+                <output name="out" num_pins="36"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_18x18.a" out_port="mult_18x18.out"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_18x18.b" out_port="mult_18x18.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_18x18_slice.A_cfg" output="mult_18x18.a">
+                </direct>
+                <direct name="b2b" input="mult_18x18_slice.B_cfg" output="mult_18x18.b">
+                </direct>
+                <direct name="out2out" input="mult_18x18.out" output="mult_18x18_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.09e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.09e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_18x18.a" output="mult_18x18_slice.A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_18x18.b" output="mult_18x18_slice.B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_18x18_slice.OUT_cfg" output="divisible_mult_18x18.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <power method="sum-of-children"/>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading 134 ps
+				The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps
+              -->
+          <direct name="a2a" input="mult_36.a" output="divisible_mult_18x18[1:0].a">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_36.a" out_port="divisible_mult_18x18[1:0].a"/>
+          </direct>
+          <direct name="b2b" input="mult_36.b" output="divisible_mult_18x18[1:0].b">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_36.b" out_port="divisible_mult_18x18[1:0].b"/>
+          </direct>
+          <direct name="out2out" input="divisible_mult_18x18[1:0].out" output="mult_36.out">
+            <delay_constant max="1.09e-9" min="74e-12" in_port="divisible_mult_18x18[1:0].out" out_port="mult_36.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mult_36x36">
+        <pb_type name="mult_36x36_slice" num_pb="1">
+          <input name="A_cfg" num_pins="36"/>
+          <input name="B_cfg" num_pins="36"/>
+          <output name="OUT_cfg" num_pins="72"/>
+          <pb_type name="mult_36x36" blif_model=".subckt multiply" num_pb="1">
+            <input name="a" num_pins="36"/>
+            <input name="b" num_pins="36"/>
+            <output name="out" num_pins="72"/>
+            <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_36x36.a" out_port="mult_36x36.out"/>
+            <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_36x36.b" out_port="mult_36x36.out"/>
+          </pb_type>
+          <interconnect>
+            <direct name="a2a" input="mult_36x36_slice.A_cfg" output="mult_36x36.a">
+            </direct>
+            <direct name="b2b" input="mult_36x36_slice.B_cfg" output="mult_36x36.b">
+            </direct>
+            <direct name="out2out" input="mult_36x36.out" output="mult_36x36_slice.OUT_cfg">
+            </direct>
+          </interconnect>
+          <power method="pin-toggle">
+            <port name="A_cfg" energy_per_toggle="2.13e-12"/>
+            <port name="B_cfg" energy_per_toggle="2.13e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
+		   to a 134 ps delay.
+				The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps
+              -->
+          <direct name="a2a" input="mult_36.a" output="mult_36x36_slice.A_cfg">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_36.a" out_port="mult_36x36_slice.A_cfg"/>
+          </direct>
+          <direct name="b2b" input="mult_36.b" output="mult_36x36_slice.B_cfg">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_36.b" out_port="mult_36x36_slice.B_cfg"/>
+          </direct>
+          <direct name="out2out" input="mult_36x36_slice.OUT_cfg" output="mult_36.out">
+            <delay_constant max="1.93e-9" min="74e-12" in_port="mult_36x36_slice.OUT_cfg" out_port="mult_36.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
+      <power method="sum-of-children"/>
+    </pb_type>
+    <!-- Define fracturable multiplier end -->
+    <!-- Define fracturable memory begin -->
+    <!-- 32 Kb Memory that can operate from 512x64 to 32Kx1 for single-port mode and 1024x32 to 32Kx1 for dual-port mode.  
+           Area and max delay based off Stratix IV 9K and 144K memories (delay from linear interpolation, Tsu(483 ps, 636 ps) Tco(1084ps, 1969ps)).  
+
+		   uTh/Tsu ratio = 0.468, uTco min/max ratio = 0.97
+           uTh = 226ps, 298ps
+           Min uTco = 1051ps, 1909ps
+           Max input delay = 204ps (from Stratix IV LAB line) - 72ps (this architecture does not lump connection box delay in internal delay)
+           Max output delay = M9K buffer 50ps. 
+		   Min input delay = 160ps (from Stratix IV Lab line) - 72ps
+		   Min output delay = 46ps (M9K buffer min/max ratio = 0.9286)
+		   
+		   Area is obtained by appropriately scaling and adjusting the published Stratix III (which is architecturally identical to Stratix IV)
+		   data from H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011.
+		   Linearly interpolating (by bit count) between the M9k and M144k areas to obtain an M32k (our RAM size) point yields a 65 nm area of
+		   of 0.153 mm^2. Interpolating based on port count between the RAMs would instead yield an area of 0.209 mm^2 for our 32 kB RAM; since 
+		   bit count accounts for more area than ports for a RAM this size we choose the bit count interpolation; however, since the port interpolation
+		   is not radically different this also gives us confidence that interpolating based on bits is OK, but slightly underpredicts area.
+		   Scaling to 40 nm^2 yields .0579 mm^2, and converting to MWTUs at 60 L^2 / MWTU yields 604,000 MWTUs. This includes routing. A Stratix IV
+		   M9K RAM is one row high and hence has one routing tile (one horizonal and one vertical routing segment area). An M144k RAM has 8 such tiles.
+		   Linearly interpolating on
+		   bits to 32 kb yields 2.2 routing tiles incorporated in the area number above. The inter-block routing represents 30% of the area of a logic 
+		   tile according to D. Lewis et al, "Architectural Enhancements in Stratix V," FPGA 2013. Hence we should subtract 0.3 * 2.2 * 84,375 MWTUs to
+		   obtain a RAM core area (not including inter-block routing) of 548,000 MWTU areas for our 32 kb RAM in a 40 nm process.
+      -->
+    <pb_type name="memory">
+      <input name="addr1" num_pins="15"/>
+      <input name="addr2" num_pins="15"/>
+      <input name="data" num_pins="64"/>
+      <input name="we1" num_pins="1"/>
+      <input name="we2" num_pins="1"/>
+      <output name="out" num_pins="64"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Physical mode of the fracturable memory -->
+      <mode name="physical">
+         <pb_type name="frac_mem_32k" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+           <input name="addr1" num_pins="15"/>
+           <input name="addr2" num_pins="15"/>
+           <input name="data1" num_pins="32"/>
+           <input name="data2" num_pins="32"/>
+           <input name="we1" num_pins="1"/>
+           <input name="we2" num_pins="1"/>
+           <output name="out1" num_pins="32"/>
+           <output name="out2" num_pins="32"/>
+           <clock name="clk" num_pins="1"/>
+         </pb_type>
+         <interconnect>
+          <direct name="address1" input="memory.addr1[14:0]" output="frac_mem_32k.addr1[14:0]"/>
+          <direct name="address2" input="memory.addr2[14:0]" output="frac_mem_32k.addr2[14:0]"/>
+          <direct name="data1" input="memory.data[31:0]" output="frac_mem_32k.data1"/>
+          <direct name="data2" input="memory.data[63:32]" output="frac_mem_32k.data2"/>
+          <direct name="writeen1" input="memory.we1" output="frac_mem_32k.we1"/>
+          <direct name="writeen2" input="memory.we2" output="frac_mem_32k.we2"/>
+          <direct name="dataout1" input="frac_mem_32k.out1" output="memory.out[31:0]"/>
+          <direct name="dataout2" input="frac_mem_32k.out2" output="memory.out[63:32]"/>
+          <direct name="clk" input="memory.clk" output="frac_mem_32k.clk"/>
+        </interconnect>
+      </mode>
+      <!-- Specify single port mode first -->
+      <mode name="mem_512x64_sp">
+        <pb_type name="mem_512x64_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="9" port_class="address"/>
+          <input name="data" num_pins="64" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="64" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x64_sp.we" clock="clk"/>
+          <T_hold value="238e-12" port="mem_512x64_sp.addr" clock="clk"/>
+          <T_hold value="238e-12" port="mem_512x64_sp.data" clock="clk"/>
+          <T_hold value="238e-12" port="mem_512x64_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_512x64_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[8:0]" output="mem_512x64_sp.addr">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[8:0]" out_port="mem_512x64_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[63:0]" output="mem_512x64_sp.data">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[63:0]" out_port="mem_512x64_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_512x64_sp.we">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_512x64_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_512x64_sp.out" output="memory.out[63:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_512x64_sp.out" out_port="memory.out[63:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x64_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_1024x32_sp">
+        <pb_type name="mem_1024x32_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="10" port_class="address"/>
+          <input name="data" num_pins="32" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_sp.we" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_sp.addr" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_sp.data" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_1024x32_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_sp.addr">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_sp.data">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_1024x32_sp.we">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_1024x32_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_1024x32_sp.out" output="memory.out[31:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_1024x32_sp.out" out_port="memory.out[31:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_1024x32_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x16_sp">
+        <pb_type name="mem_2048x16_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="11" port_class="address"/>
+          <input name="data" num_pins="16" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="16" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_sp.we" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_sp.addr" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_sp.data" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_2048x16_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_sp.addr">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_sp.data">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x16_sp.we">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_2048x16_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x16_sp.out" output="memory.out[15:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_2048x16_sp.out" out_port="memory.out[15:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x16_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_4096x8_sp">
+        <pb_type name="mem_4096x8_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="12" port_class="address"/>
+          <input name="data" num_pins="8" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="8" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_sp.we" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_sp.addr" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_sp.data" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_4096x8_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[11:0]" output="mem_4096x8_sp.addr">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[11:0]" out_port="mem_4096x8_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[7:0]" output="mem_4096x8_sp.data">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[7:0]" out_port="mem_4096x8_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_4096x8_sp.we">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_4096x8_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_4096x8_sp.out" output="memory.out[7:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_4096x8_sp.out" out_port="memory.out[7:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_4096x8_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_8192x4_sp">
+        <pb_type name="mem_8192x4_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="13" port_class="address"/>
+          <input name="data" num_pins="4" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="4" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_sp.we" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_sp.addr" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_sp.data" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_8192x4_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_sp.addr">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_sp.data">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_8192x4_sp.we">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_8192x4_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_8192x4_sp.out" output="memory.out[3:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_8192x4_sp.out" out_port="memory.out[3:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_8192x4_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_16384x2_sp">
+        <pb_type name="mem_16384x2_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="14" port_class="address"/>
+          <input name="data" num_pins="2" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="2" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_sp.we" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_sp.addr" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_sp.data" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_16384x2_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_sp.addr">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_sp.data">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_16384x2_sp.we">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_16384x2_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_16384x2_sp.out" output="memory.out[1:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_16384x2_sp.out" out_port="memory.out[1:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_16384x2_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_32768x1_sp">
+        <pb_type name="mem_32768x1_sp" blif_model=".subckt single_port_ram" class="memory" num_pb="1">
+          <input name="addr" num_pins="15" port_class="address"/>
+          <input name="data" num_pins="1" port_class="data_in"/>
+          <input name="we" num_pins="1" port_class="write_en"/>
+          <output name="out" num_pins="1" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.addr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.data" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_sp.we" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_sp.addr" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_sp.data" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_sp.we" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_32768x1_sp.out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="9.0e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_sp.addr">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_sp.addr"/>
+          </direct>
+          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_sp.data">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_sp.data"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_32768x1_sp.we">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_32768x1_sp.we"/>
+          </direct>
+          <direct name="dataout1" input="mem_32768x1_sp.out" output="memory.out[0:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_32768x1_sp.out" out_port="memory.out[0:0]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_32768x1_sp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Specify true dual port mode next -->
+      <mode name="mem_1024x32_dp">
+        <pb_type name="mem_1024x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="10" port_class="address1"/>
+          <input name="addr2" num_pins="10" port_class="address2"/>
+          <input name="data1" num_pins="32" port_class="data_in1"/>
+          <input name="data2" num_pins="32" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="32" port_class="data_out1"/>
+          <output name="out2" num_pins="32" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_1024x32_dp.we2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_dp.addr1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_dp.data1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_dp.we1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_dp.addr2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_dp.data2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_1024x32_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_1024x32_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_1024x32_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[9:0]" output="mem_1024x32_dp.addr1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[9:0]" out_port="mem_1024x32_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[9:0]" output="mem_1024x32_dp.addr2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr2[9:0]" out_port="mem_1024x32_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[31:0]" output="mem_1024x32_dp.data1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[31:0]" out_port="mem_1024x32_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[63:32]" output="mem_1024x32_dp.data2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[63:32]" out_port="mem_1024x32_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_1024x32_dp.we1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_1024x32_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_1024x32_dp.we2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we2" out_port="mem_1024x32_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_1024x32_dp.out1" output="memory.out[31:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_1024x32_dp.out1" out_port="memory.out[31:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_1024x32_dp.out2" output="memory.out[63:32]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_1024x32_dp.out2" out_port="memory.out[63:32]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_1024x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_2048x16_dp">
+        <pb_type name="mem_2048x16_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="11" port_class="address1"/>
+          <input name="addr2" num_pins="11" port_class="address2"/>
+          <input name="data1" num_pins="16" port_class="data_in1"/>
+          <input name="data2" num_pins="16" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="16" port_class="data_out1"/>
+          <output name="out2" num_pins="16" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_2048x16_dp.we2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_dp.addr1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_dp.data1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_dp.we1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_dp.addr2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_dp.data2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_2048x16_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_2048x16_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_2048x16_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[10:0]" output="mem_2048x16_dp.addr1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[10:0]" out_port="mem_2048x16_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[10:0]" output="mem_2048x16_dp.addr2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr2[10:0]" out_port="mem_2048x16_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[15:0]" output="mem_2048x16_dp.data1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[15:0]" out_port="mem_2048x16_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[31:16]" output="mem_2048x16_dp.data2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[31:16]" out_port="mem_2048x16_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_2048x16_dp.we1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_2048x16_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_2048x16_dp.we2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we2" out_port="mem_2048x16_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_2048x16_dp.out1" output="memory.out[15:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_2048x16_dp.out1" out_port="memory.out[15:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_2048x16_dp.out2" output="memory.out[31:16]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_2048x16_dp.out2" out_port="memory.out[31:16]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_2048x16_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_4096x8_dp">
+        <pb_type name="mem_4096x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="12" port_class="address1"/>
+          <input name="addr2" num_pins="12" port_class="address2"/>
+          <input name="data1" num_pins="8" port_class="data_in1"/>
+          <input name="data2" num_pins="8" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="8" port_class="data_out1"/>
+          <output name="out2" num_pins="8" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_4096x8_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_4096x8_dp.we2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_dp.addr1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_dp.data1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_dp.we1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_dp.addr2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_dp.data2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_4096x8_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_4096x8_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_4096x8_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[11:0]" output="mem_4096x8_dp.addr1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[11:0]" out_port="mem_4096x8_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[11:0]" output="mem_4096x8_dp.addr2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr2[11:0]" out_port="mem_4096x8_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[7:0]" output="mem_4096x8_dp.data1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[7:0]" out_port="mem_4096x8_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[15:8]" output="mem_4096x8_dp.data2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[15:8]" out_port="mem_4096x8_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_4096x8_dp.we1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_4096x8_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_4096x8_dp.we2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we2" out_port="mem_4096x8_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_4096x8_dp.out1" output="memory.out[7:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_4096x8_dp.out1" out_port="memory.out[7:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_4096x8_dp.out2" output="memory.out[15:8]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_4096x8_dp.out2" out_port="memory.out[15:8]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_4096x8_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_8192x4_dp">
+        <pb_type name="mem_8192x4_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="13" port_class="address1"/>
+          <input name="addr2" num_pins="13" port_class="address2"/>
+          <input name="data1" num_pins="4" port_class="data_in1"/>
+          <input name="data2" num_pins="4" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="4" port_class="data_out1"/>
+          <output name="out2" num_pins="4" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_8192x4_dp.we2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_dp.addr1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_dp.data1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_dp.we1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_dp.addr2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_dp.data2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_8192x4_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_8192x4_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_8192x4_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[12:0]" output="mem_8192x4_dp.addr1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[12:0]" out_port="mem_8192x4_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[12:0]" output="mem_8192x4_dp.addr2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr2[12:0]" out_port="mem_8192x4_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[3:0]" output="mem_8192x4_dp.data1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[3:0]" out_port="mem_8192x4_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[7:4]" output="mem_8192x4_dp.data2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[7:4]" out_port="mem_8192x4_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_8192x4_dp.we1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_8192x4_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_8192x4_dp.we2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we2" out_port="mem_8192x4_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_8192x4_dp.out1" output="memory.out[3:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_8192x4_dp.out1" out_port="memory.out[3:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_8192x4_dp.out2" output="memory.out[7:4]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_8192x4_dp.out2" out_port="memory.out[7:4]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_8192x4_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_16384x2_dp">
+        <pb_type name="mem_16384x2_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="14" port_class="address1"/>
+          <input name="addr2" num_pins="14" port_class="address2"/>
+          <input name="data1" num_pins="2" port_class="data_in1"/>
+          <input name="data2" num_pins="2" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="2" port_class="data_out1"/>
+          <output name="out2" num_pins="2" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_16384x2_dp.we2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_dp.addr1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_dp.data1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_dp.we1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_dp.addr2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_dp.data2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_16384x2_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_16384x2_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_16384x2_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[13:0]" output="mem_16384x2_dp.addr1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[13:0]" out_port="mem_16384x2_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[13:0]" output="mem_16384x2_dp.addr2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr2[13:0]" out_port="mem_16384x2_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[1:0]" output="mem_16384x2_dp.data1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[1:0]" out_port="mem_16384x2_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[3:2]" output="mem_16384x2_dp.data2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[3:2]" out_port="mem_16384x2_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_16384x2_dp.we1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_16384x2_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_16384x2_dp.we2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we2" out_port="mem_16384x2_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_16384x2_dp.out1" output="memory.out[1:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_16384x2_dp.out1" out_port="memory.out[1:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_16384x2_dp.out2" output="memory.out[3:2]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_16384x2_dp.out2" out_port="memory.out[3:2]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_16384x2_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mem_32768x1_dp">
+        <pb_type name="mem_32768x1_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="addr1" num_pins="15" port_class="address1"/>
+          <input name="addr2" num_pins="15" port_class="address2"/>
+          <input name="data1" num_pins="1" port_class="data_in1"/>
+          <input name="data2" num_pins="1" port_class="data_in2"/>
+          <input name="we1" num_pins="1" port_class="write_en1"/>
+          <input name="we2" num_pins="1" port_class="write_en2"/>
+          <output name="out1" num_pins="1" port_class="data_out1"/>
+          <output name="out2" num_pins="1" port_class="data_out2"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.addr1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.data1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.we1" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.addr2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.data2" clock="clk"/>
+          <T_setup value="509e-12" port="mem_32768x1_dp.we2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_dp.addr1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_dp.data1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_dp.we1" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_dp.addr2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_dp.data2" clock="clk"/>
+          <T_hold value="238e-12" port="mem_32768x1_dp.we2" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_32768x1_dp.out1" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="mem_32768x1_dp.out2" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="address1" input="memory.addr1[14:0]" output="mem_32768x1_dp.addr1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr1[14:0]" out_port="mem_32768x1_dp.addr1"/>
+          </direct>
+          <direct name="address2" input="memory.addr2[14:0]" output="mem_32768x1_dp.addr2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.addr2[14:0]" out_port="mem_32768x1_dp.addr2"/>
+          </direct>
+          <direct name="data1" input="memory.data[0:0]" output="mem_32768x1_dp.data1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[0:0]" out_port="mem_32768x1_dp.data1"/>
+          </direct>
+          <direct name="data2" input="memory.data[1:1]" output="mem_32768x1_dp.data2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.data[1:1]" out_port="mem_32768x1_dp.data2"/>
+          </direct>
+          <direct name="writeen1" input="memory.we1" output="mem_32768x1_dp.we1">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we1" out_port="mem_32768x1_dp.we1"/>
+          </direct>
+          <direct name="writeen2" input="memory.we2" output="mem_32768x1_dp.we2">
+            <delay_constant max="132e-12" min="88e-12" in_port="memory.we2" out_port="mem_32768x1_dp.we2"/>
+          </direct>
+          <direct name="dataout1" input="mem_32768x1_dp.out1" output="memory.out[0:0]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_32768x1_dp.out1" out_port="memory.out[0:0]"/>
+          </direct>
+          <direct name="dataout2" input="mem_32768x1_dp.out2" output="memory.out[1:1]">
+            <delay_constant max="50e-12" min="46e-12" in_port="mem_32768x1_dp.out2" out_port="memory.out[1:1]"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_32768x1_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this memory block every 8 columns from (and including) the second column -->
+      <power method="sum-of-children"/>
+    </pb_type>
+    <!-- Define fracturable memory end -->
+  </complexblocklist>
+</architecture>

From 2712c354a9ea80e194932c53341a54c221d480ec Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Aug 2020 12:38:56 -0600
Subject: [PATCH 017/148] now physical pb_port binding support multiple ports

---
 .../src/pb_type_annotation.cpp                | 63 ++++++------
 .../libarchopenfpga/src/pb_type_annotation.h  | 13 ++-
 .../src/read_xml_pb_type_annotation.cpp       | 38 +++++++-
 .../src/write_xml_pb_type_annotation.cpp      | 21 +++-
 .../libopenfpgautil/src/openfpga_port.cpp     | 10 ++
 .../libopenfpgautil/src/openfpga_port.h       |  1 +
 openfpga/src/annotation/annotate_pb_graph.cpp | 58 +++++------
 openfpga/src/annotation/annotate_pb_types.cpp | 50 +++++-----
 .../annotation/check_pb_type_annotation.cpp   |  2 +-
 .../src/annotation/vpr_device_annotation.cpp  | 97 +++++++++++--------
 .../src/annotation/vpr_device_annotation.h    | 30 +++---
 11 files changed, 239 insertions(+), 144 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
index b38796c9c..133ee000c 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -1,6 +1,7 @@
 /************************************************************************
  * Member functions for class PbTypeAnnotation
  ***********************************************************************/
+#include <algorithm>
 #include "vtr_log.h"
 #include "vtr_assert.h"
 #include "pb_type_annotation.h"
@@ -85,24 +86,15 @@ std::vector<std::string> PbTypeAnnotation::port_names() const {
   return keys;
 }
 
-BasicPort PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const {
-  std::map<std::string, BasicPort>::const_iterator it = operating_pb_type_ports_.find(port_name);
+std::map<BasicPort, int> PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const {
+  std::map<std::string, std::map<BasicPort, int>>::const_iterator it = operating_pb_type_ports_.find(port_name);
   if (it == operating_pb_type_ports_.end()) {
     /* Return an empty port */
-    return BasicPort();
+    return std::map<BasicPort, int>();
   }
   return operating_pb_type_ports_.at(port_name);
 }
 
-int PbTypeAnnotation::physical_pin_rotate_offset(const std::string& port_name) const {
-  std::map<std::string, int>::const_iterator it = physical_pin_rotate_offsets_.find(port_name);
-  if (it == physical_pin_rotate_offsets_.end()) {
-    /* Return a zero offset which is default */
-    return 0;
-  }
-  return physical_pin_rotate_offsets_.at(port_name);
-}
-
 std::vector<std::string> PbTypeAnnotation::interconnect_names() const {
   std::vector<std::string> keys;
   for (auto const& element : interconnect_circuit_model_names_) {
@@ -177,27 +169,42 @@ void PbTypeAnnotation::set_physical_pb_type_index_offset(const int& value) {
 void PbTypeAnnotation::add_pb_type_port_pair(const std::string& operating_pb_port_name,
                                              const BasicPort& physical_pb_port) {
   /* Give a warning if the operating_pb_port_name already exist */
-  std::map<std::string, BasicPort>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
-  /* Give a warning if the interconnection name already exist */
-  if (it != operating_pb_type_ports_.end()) {
-    VTR_LOG_WARN("Redefine operating pb type port '%s' with physical pb type port '%s'\n",
-                  operating_pb_port_name.c_str(), physical_pb_port.get_name().c_str());
-  }
+  std::map<std::string, std::map<BasicPort, int>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
 
-  operating_pb_type_ports_[operating_pb_port_name] = physical_pb_port;
-}
-
-void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
-                                                      const int& physical_pin_rotate_offset) {
-  std::map<std::string, BasicPort>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
-  /* Give a warning if the interconnection name already exist */
+  /* If not exist, initialize and set a default value */
   if (it == operating_pb_type_ports_.end()) {
-    VTR_LOG_ERROR("Operating pb type port '%s' does not exist! Ignore physical pin rotate offset '%d'\n",
-                  operating_pb_port_name.c_str(), physical_pin_rotate_offset);
+    operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = 0;
+    /* We can return early */
     return;
   }
 
-  physical_pin_rotate_offsets_[operating_pb_port_name] = physical_pin_rotate_offset;
+  /* If the physical port is not in the list, we create one and set a default value */
+  if (0 == operating_pb_type_ports_[operating_pb_port_name].count(physical_pb_port)) {
+    operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = 0;
+  }
+}
+
+void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
+                                                      const BasicPort& physical_pb_port,
+                                                      const int& physical_pin_rotate_offset) {
+  std::map<std::string, std::map<BasicPort, int>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
+
+  if (it == operating_pb_type_ports_.end()) {
+    VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n",
+                  operating_pb_port_name.c_str());
+    exit(1);
+  }
+
+  if (operating_pb_type_ports_[operating_pb_port_name].end() == operating_pb_type_ports_[operating_pb_port_name].find(physical_pb_port)) {
+    VTR_LOG_ERROR("The physical pb_type port '%s[%lu:%lu]' definition for operating pb_type port '%s' is not valid!\n",
+                  physical_pb_port.get_name().c_str(),
+                  physical_pb_port.get_lsb(),
+                  physical_pb_port.get_msb(),
+                  operating_pb_port_name.c_str());
+    exit(1);
+  }
+
+  operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = physical_pin_rotate_offset;
 }
 
 void PbTypeAnnotation::add_interconnect_circuit_model_pair(const std::string& interc_name,
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index e80acc3dc..4e1d4e8a2 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -48,8 +48,7 @@ class PbTypeAnnotation {
     float physical_pb_type_index_factor() const;
     int physical_pb_type_index_offset() const;
     std::vector<std::string> port_names() const;
-    BasicPort physical_pb_type_port(const std::string& port_name) const;
-    int physical_pin_rotate_offset(const std::string& port_name) const;
+    std::map<BasicPort, int> physical_pb_type_port(const std::string& port_name) const;
     std::vector<std::string> interconnect_names() const;
     std::string interconnect_circuit_model_name(const std::string& interc_name) const;
   public: /* Public mutators */
@@ -68,6 +67,7 @@ class PbTypeAnnotation {
     void add_pb_type_port_pair(const std::string& operating_pb_port_name,
                                const BasicPort& physical_pb_port);
     void set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
+                                        const BasicPort& physical_pb_port,
                                         const int& physical_pin_rotate_offset);
     void add_interconnect_circuit_model_pair(const std::string& interc_name,
                                              const std::string& circuit_model_name);
@@ -133,10 +133,9 @@ class PbTypeAnnotation {
      */
     int physical_pb_type_index_offset_;
 
-    /* Link from the pins under an operating pb_type to physical pb_type  */
-    std::map<std::string, BasicPort> operating_pb_type_ports_;
-
-    /* The offset aims to align the pin indices for port of pb_type 
+    /* Link from the pins under an operating pb_type to pairs of
+     * its physical pb_type and its pin rotating offset
+     * The offset aims to align the pin indices for port of pb_type 
      * between operating and physical modes, especially when an operating 
      * mode contains multiple pb_type (num_pb>1) that are linked to 
      * the same physical pb_type. 
@@ -148,7 +147,7 @@ class PbTypeAnnotation {
      * operating pb_type adder[0].pin[0] with a full path clb.fle[arith].adder[0]
      * to physical pb_type adder[0].pin[1] with a full path clb.fle[physical].adder[0]
      */
-    std::map<std::string, int> physical_pin_rotate_offsets_;
+    std::map<std::string, std::map<BasicPort, int>> operating_pb_type_ports_;
 
     /* Link between the interconnects under this pb_type and circuit model names */
     std::map<std::string, std::string> interconnect_circuit_model_names_;
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index 743e23741..a4d25e1cf 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -55,12 +55,40 @@ void read_xml_pb_port_annotation(pugi::xml_node& xml_port,
   const std::string& name_attr = get_attribute(xml_port, "name", loc_data).as_string();
   const std::string& physical_mode_port_attr = get_attribute(xml_port, "physical_mode_port", loc_data).as_string();
 
-  /* Parse the mode port using openfpga port parser */
-  openfpga::PortParser port_parser(physical_mode_port_attr); 
-  pb_type_annotation.add_pb_type_port_pair(name_attr, port_parser.port());
+  /* Split the physical mode port attributes with space */
+  openfpga::StringToken port_tokenizer(physical_mode_port_attr);
+  const std::vector<std::string> physical_mode_ports = port_tokenizer.split();
 
-  /* We have an optional attribute: physical_mode_pin_rotate_offset */
-  pb_type_annotation.set_physical_pin_rotate_offset(name_attr, get_attribute(xml_port, "physical_mode_pin_rotate_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_int(0));
+  /* Parse the mode port using openfpga port parser */
+  for (const auto& physical_mode_port : physical_mode_ports) {
+    openfpga::PortParser port_parser(physical_mode_port); 
+    pb_type_annotation.add_pb_type_port_pair(name_attr, port_parser.port());
+  }
+
+  /* We have an optional attribute: physical_mode_pin_rotate_offset
+   * Split based on the number of physical pb_type ports that have been defined
+   */
+  const std::string& physical_pin_rotate_offset_attr = get_attribute(xml_port, "physical_mode_pin_rotate_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
+
+  if (false == physical_pin_rotate_offset_attr.empty()) {
+    /* Split the physical mode port attributes with space */
+    openfpga::StringToken offset_tokenizer(physical_pin_rotate_offset_attr);
+    const std::vector<std::string> rotate_offsets = offset_tokenizer.split();
+   
+    /* Error out if the offset does not match the port definition */
+    if (physical_mode_ports.size() != rotate_offsets.size()) {
+      archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port),
+                     "Defined %lu physical mode ports but only %lu physical pin rotate offset are defined! Expect size matching.\n",
+                      physical_mode_ports.size(), rotate_offsets.size());
+    }
+
+    for (size_t iport = 0; iport < physical_mode_ports.size(); ++iport) {
+      openfpga::PortParser port_parser(physical_mode_ports[iport]); 
+      pb_type_annotation.set_physical_pin_rotate_offset(name_attr,
+                                                        port_parser.port(),
+                                                        std::stoi(rotate_offsets[iport]));
+    }
+  }
 }
 
 /********************************************************************
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
index 531e117f1..b013e5801 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
@@ -116,8 +116,25 @@ void write_xml_pb_port_annotation(std::fstream& fp,
   fp << "\t\t\t" << "<port";
  
   write_xml_attribute(fp, "name", port_name.c_str());
-  write_xml_attribute(fp, "physical_mode_port", generate_physical_pb_port_name(pb_type_annotation.physical_pb_type_port(port_name)).c_str());
-  write_xml_attribute(fp, "physical_mode_pin_rotate_offset", pb_type_annotation.physical_pin_rotate_offset(port_name));
+
+  std::string physical_mode_port_attr;
+  for (const auto& physical_pb_port_pair : pb_type_annotation.physical_pb_type_port(port_name)) {
+    if (false == physical_mode_port_attr.empty()) {
+      physical_mode_port_attr += " ";
+    }
+    physical_mode_port_attr += generate_physical_pb_port_name(physical_pb_port_pair.first);
+  }
+  write_xml_attribute(fp, "physical_mode_port", physical_mode_port_attr.c_str());
+
+
+  std::string physical_mode_pin_rotate_offset_attr;
+  for (const auto& physical_pb_port_pair : pb_type_annotation.physical_pb_type_port(port_name)) {
+    if (false == physical_mode_pin_rotate_offset_attr.empty()) {
+      physical_mode_pin_rotate_offset_attr += " ";
+    }
+    physical_mode_pin_rotate_offset_attr += std::to_string(physical_pb_port_pair.second);
+  }
+  write_xml_attribute(fp, "physical_mode_pin_rotate_offset", physical_mode_pin_rotate_offset_attr.c_str()); 
 
   fp << "/>" << "\n";
 }
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_port.cpp b/libopenfpga/libopenfpgautil/src/openfpga_port.cpp
index 7e7cc4007..023af7618 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_port.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_port.cpp
@@ -124,6 +124,16 @@ bool BasicPort::operator== (const BasicPort& portA) const {
   return false;
 }
 
+bool BasicPort::operator< (const BasicPort& portA) const {
+  if  ( (0 == this->get_name().compare(portA.get_name())) 
+     && (this->get_lsb() < portA.get_lsb())
+     && (this->get_msb() < portA.get_msb()) ) {
+    return true;
+  }
+  return false;
+}
+
+
 /************************************************************************
  * Mutators 
  ***********************************************************************/
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_port.h b/libopenfpga/libopenfpgautil/src/openfpga_port.h
index d870e94fc..ca1afb4a5 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_port.h
+++ b/libopenfpga/libopenfpgautil/src/openfpga_port.h
@@ -21,6 +21,7 @@ class BasicPort {
     BasicPort(const BasicPort& basic_port); /* Copy constructor */
   public: /* Overloaded operators */
     bool operator== (const BasicPort& portA) const;
+    bool operator< (const BasicPort& portA) const;
   public: /* Accessors */
     size_t get_width() const; /* get the port width */
     size_t get_msb() const; /* get the LSB */
diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 081acf900..93a154222 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -306,35 +306,37 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
                             t_pb_graph_pin* physical_pb_graph_pin,
                             const VprDeviceAnnotation& vpr_device_annotation) {
   /* If the parent ports of the two pins are not paired, fail */
-  if (physical_pb_graph_pin->port != vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
-    return false;
-  }
-  /* Check the pin number of physical pb_graph_pin matches the pin number of 
-   * operating pb_graph_pin plus a rotation offset 
-   *                                              operating port         physical port
-   *                      LSB  port_range.lsb()    pin_number              pin_number      MSB
-   *                                 |                  |                     |
-   *    Operating port     |         |                  +------               |
-   *                                 |                        |<----offset--->|
-   *    Physical port      |         +                        +               +
-   *
-   * Note: 
-   *   - accumulated offset is NOT the pin rotate offset specified by users
-   *     It is an aggregation of the offset during pin pairing
-   *     Each time, we manage to pair two pins, the accumulated offset will be incremented
-   *     by the pin rotate offset value
-   *     The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
-   */
-  int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port);
-  const BasicPort& physical_port_range = vpr_device_annotation.physical_pb_port_range(operating_pb_graph_pin->port);
-  if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number
-                                         + (int)physical_port_range.get_lsb() 
-                                         + acc_offset) {
-    return false;
-  }
+  for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
+    if (physical_pb_graph_pin->port != candidate_port) {
+      return false;
+    }
+    /* Check the pin number of physical pb_graph_pin matches the pin number of 
+     * operating pb_graph_pin plus a rotation offset 
+     *                                              operating port         physical port
+     *                      LSB  port_range.lsb()    pin_number              pin_number      MSB
+     *                                 |                  |                     |
+     *    Operating port     |         |                  +------               |
+     *                                 |                        |<----offset--->|
+     *    Physical port      |         +                        +               +
+     *
+     * Note: 
+     *   - accumulated offset is NOT the pin rotate offset specified by users
+     *     It is an aggregation of the offset during pin pairing
+     *     Each time, we manage to pair two pins, the accumulated offset will be incremented
+     *     by the pin rotate offset value
+     *     The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
+     */
+    int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port, candidate_port);
+    const BasicPort& physical_port_range = vpr_device_annotation.physical_pb_port_range(operating_pb_graph_pin->port, candidate_port);
+    if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number
+                                           + (int)physical_port_range.get_lsb() 
+                                           + acc_offset) {
+      return false;
+    }
 
-  /* Reach here, it means all the requirements have been met */
-  return true;
+    /* Reach here, it means all the requirements have been met */
+    return true;
+  }
 }
 
 /********************************************************************
diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
index d8701be78..cb6c9e9b3 100644
--- a/openfpga/src/annotation/annotate_pb_types.cpp
+++ b/openfpga/src/annotation/annotate_pb_types.cpp
@@ -211,32 +211,38 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
    * if not found, we assume that the physical port is the same as the operating pb_port
    */
   for (t_port* operating_pb_port : pb_type_ports(operating_pb_type)) {
-    /* Try to find the port in the pb_type_annotation */
-    BasicPort expected_physical_pb_port = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
-    if (true == expected_physical_pb_port.get_name().empty()) {
-      /* Not found, we reset the port information to be consistent as the operating pb_port */
+    std::map<BasicPort, int> expected_physical_pb_ports = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
+  
+    /* If not defined in the annotation, set the default pair:
+     * rotate_offset is 0 by default!
+     */
+    if (true == expected_physical_pb_ports.empty()) {
+      BasicPort expected_physical_pb_port;
       expected_physical_pb_port.set_name(std::string(operating_pb_port->name));
       expected_physical_pb_port.set_width(operating_pb_port->num_pins);
+      expected_physical_pb_ports[expected_physical_pb_port] = 0;
     }
 
-    /* Try to find the expected port in the physical pb_type */
-    t_port* physical_pb_port = find_pb_type_port(physical_pb_type, expected_physical_pb_port.get_name());
-    /* Not found, mapping fails */
-    if (nullptr == physical_pb_port) {
-      return false;
+    for (const auto& expected_physical_pb_port : expected_physical_pb_ports) {
+      /* Try to find the expected port in the physical pb_type */
+      t_port* physical_pb_port = find_pb_type_port(physical_pb_type, expected_physical_pb_port.first.get_name());
+      /* Not found, mapping fails */
+      if (nullptr == physical_pb_port) {
+        return false;
+      }
+      /* If the port range does not match, mapping fails */
+      if (false == BasicPort(physical_pb_port->name, physical_pb_port->num_pins).contained(expected_physical_pb_port.first)) {
+        return false;
+      }
+      /* Now, port mapping should succeed, we update the vpr_device_annotation 
+       * - port binding
+       * - port range
+       * - port pin rotate offset
+       */
+      vpr_device_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
+      vpr_device_annotation.add_physical_pb_port_range(operating_pb_port, physical_pb_port, expected_physical_pb_port.first);
+      vpr_device_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second);
     }
-    /* If the port range does not match, mapping fails */
-    if (false == BasicPort(physical_pb_port->name, physical_pb_port->num_pins).contained(expected_physical_pb_port)) {
-      return false;
-    }
-    /* Now, port mapping should succeed, we update the vpr_device_annotation 
-     * - port binding
-     * - port range
-     * - port pin rotate offset
-     */
-    vpr_device_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
-    vpr_device_annotation.add_physical_pb_port_range(operating_pb_port, expected_physical_pb_port);
-    vpr_device_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, pb_type_annotation.physical_pin_rotate_offset(std::string(operating_pb_port->name)));
   }
 
   /* Now, pb_type mapping should succeed, we update the vpr_device_annotation
@@ -365,7 +371,7 @@ bool self_pair_physical_pb_types(t_pb_type* physical_pb_type,
   for (t_port* physical_pb_port : pb_type_ports(physical_pb_type)) {
     BasicPort physical_port_range(physical_pb_port->name, physical_pb_port->num_pins);
     vpr_device_annotation.add_physical_pb_port(physical_pb_port, physical_pb_port);
-    vpr_device_annotation.add_physical_pb_port_range(physical_pb_port, physical_port_range);
+    vpr_device_annotation.add_physical_pb_port_range(physical_pb_port, physical_pb_port, physical_port_range);
   }
 
   /* Now, pb_type mapping should succeed, we update the vpr_device_annotation */
diff --git a/openfpga/src/annotation/check_pb_type_annotation.cpp b/openfpga/src/annotation/check_pb_type_annotation.cpp
index 5159ec064..d0709c81c 100644
--- a/openfpga/src/annotation/check_pb_type_annotation.cpp
+++ b/openfpga/src/annotation/check_pb_type_annotation.cpp
@@ -114,7 +114,7 @@ void check_vpr_physical_primitive_pb_type_annotation(t_pb_type* cur_pb_type,
 
   /* Now we need to check each port of the pb_type */ 
   for (t_port* pb_port : pb_type_ports(cur_pb_type)) {
-    if (nullptr == vpr_device_annotation.physical_pb_port(pb_port)) {
+    if (0 == vpr_device_annotation.physical_pb_port(pb_port).size()) {
       VTR_LOG_ERROR("Find a port '%s' of pb_type '%s' which has not been mapped to any physical port!\n",
                     pb_port->name, cur_pb_type->name);
       VTR_LOG_ERROR("Please specify in the OpenFPGA architecture\n");
diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index 0787e0225..71b3baf63 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -48,23 +48,28 @@ t_pb_type* VprDeviceAnnotation::physical_pb_type(t_pb_type* pb_type) const {
   return physical_pb_types_.at(pb_type);
 }
 
-t_port* VprDeviceAnnotation::physical_pb_port(t_port* pb_port) const {
+std::vector<t_port*> VprDeviceAnnotation::physical_pb_port(t_port* pb_port) const {
   /* Ensure that the pb_type is in the list */
-  std::map<t_port*, t_port*>::const_iterator it = physical_pb_ports_.find(pb_port);
+  std::map<t_port*, std::vector<t_port*>>::const_iterator it = physical_pb_ports_.find(pb_port);
   if (it == physical_pb_ports_.end()) {
-    return nullptr;
+    return std::vector<t_port*>();
   }
   return physical_pb_ports_.at(pb_port);
 }
 
-BasicPort VprDeviceAnnotation::physical_pb_port_range(t_port* pb_port) const {
+BasicPort VprDeviceAnnotation::physical_pb_port_range(t_port* operating_pb_port,
+                                                      t_port* physical_pb_port) const {
   /* Ensure that the pb_type is in the list */
-  std::map<t_port*, BasicPort>::const_iterator it = physical_pb_port_ranges_.find(pb_port);
+  std::map<t_port*, std::map<t_port*, BasicPort>>::const_iterator it = physical_pb_port_ranges_.find(operating_pb_port);
   if (it == physical_pb_port_ranges_.end()) {
     /* Return an invalid port. As such the port width will be 0, which is an invalid value */
     return BasicPort();
   }
-  return physical_pb_port_ranges_.at(pb_port);
+  if (0 == physical_pb_port_ranges_.at(operating_pb_port).count(physical_pb_port)) {
+    /* Return an invalid port. As such the port width will be 0, which is an invalid value */
+    return BasicPort();
+  }
+  return physical_pb_port_ranges_.at(operating_pb_port).at(physical_pb_port);
 }
 
 CircuitModelId VprDeviceAnnotation::pb_type_circuit_model(t_pb_type* physical_pb_type) const {
@@ -185,24 +190,34 @@ int VprDeviceAnnotation::physical_pb_type_index_offset(t_pb_type* pb_type) const
   return physical_pb_type_index_offsets_.at(pb_type);
 }
 
-int VprDeviceAnnotation::physical_pb_pin_rotate_offset(t_port* pb_port) const {
+int VprDeviceAnnotation::physical_pb_pin_rotate_offset(t_port* operating_pb_port,
+                                                       t_port* physical_pb_port) const {
   /* Ensure that the pb_type is in the list */
-  std::map<t_port*, int>::const_iterator it = physical_pb_pin_rotate_offsets_.find(pb_port);
+  std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_pin_rotate_offsets_.find(operating_pb_port);
   if (it == physical_pb_pin_rotate_offsets_.end()) {
     /* Default value is 0 */
     return 0;
   }
-  return physical_pb_pin_rotate_offsets_.at(pb_port);
+  if (0 == physical_pb_pin_rotate_offsets_.at(operating_pb_port).count(physical_pb_port)) {
+    /* Default value is 0 */
+    return 0;
+  }
+  return physical_pb_pin_rotate_offsets_.at(operating_pb_port).at(physical_pb_port);
 }
 
-int VprDeviceAnnotation::physical_pb_pin_offset(t_port* pb_port) const {
+int VprDeviceAnnotation::physical_pb_pin_offset(t_port* operating_pb_port,
+                                                t_port* physical_pb_port) const {
   /* Ensure that the pb_type is in the list */
-  std::map<t_port*, int>::const_iterator it = physical_pb_pin_offsets_.find(pb_port);
+  std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_pin_offsets_.find(operating_pb_port);
   if (it == physical_pb_pin_offsets_.end()) {
     /* Default value is 0 */
     return 0;
   }
-  return physical_pb_pin_offsets_.at(pb_port);
+  if (0 == physical_pb_pin_offsets_.at(operating_pb_port).count(physical_pb_port)) {
+    /* Default value is 0 */
+    return 0;
+  }
+  return physical_pb_pin_offsets_.at(operating_pb_port).at(physical_pb_port);
 }
 
 
@@ -274,29 +289,28 @@ void VprDeviceAnnotation::add_physical_pb_type(t_pb_type* operating_pb_type, t_p
   physical_pb_types_[operating_pb_type] = physical_pb_type;
 }
 
-void VprDeviceAnnotation::add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port) {
-  /* Warn any override attempt */
-  std::map<t_port*, t_port*>::const_iterator it = physical_pb_ports_.find(operating_pb_port);
-  if (it != physical_pb_ports_.end()) {
-    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port '%s'!\n",
-                 operating_pb_port->name, physical_pb_port->name);
-  }
-
-  physical_pb_ports_[operating_pb_port] = physical_pb_port;
+void VprDeviceAnnotation::add_physical_pb_port(t_port* operating_pb_port,
+                                               t_port* physical_pb_port) {
+  physical_pb_ports_[operating_pb_port].push_back(physical_pb_port);
 }
 
-void VprDeviceAnnotation::add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range) {
+void VprDeviceAnnotation::add_physical_pb_port_range(t_port* operating_pb_port,
+                                                     t_port* physical_pb_port,
+                                                     const BasicPort& port_range) {
   /* The port range must satify the port width*/
   VTR_ASSERT((size_t)operating_pb_port->num_pins == port_range.get_width());
 
   /* Warn any override attempt */
-  std::map<t_port*, BasicPort>::const_iterator it = physical_pb_port_ranges_.find(operating_pb_port);
-  if (it != physical_pb_port_ranges_.end()) {
-    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port range '[%ld:%ld]'!\n",
-                 operating_pb_port->name, port_range.get_lsb(), port_range.get_msb());
+  std::map<t_port*, std::map<t_port*, BasicPort>>::const_iterator it = physical_pb_port_ranges_.find(operating_pb_port);
+  if ( (it != physical_pb_port_ranges_.end())
+    && (0 < physical_pb_port_ranges_[operating_pb_port].count(physical_pb_port)) ) {
+    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port range '%s[%ld:%ld]'!\n",
+                 operating_pb_port->name,
+                 physical_pb_port->name,
+                 port_range.get_lsb(), port_range.get_msb());
   }
 
-  physical_pb_port_ranges_[operating_pb_port] = port_range;
+  physical_pb_port_ranges_[operating_pb_port][physical_pb_port] = port_range;
 }
 
 void VprDeviceAnnotation::add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model) {
@@ -396,17 +410,20 @@ void VprDeviceAnnotation::add_physical_pb_type_index_offset(t_pb_type* pb_type,
   physical_pb_type_index_offsets_[pb_type] = offset;
 }
 
-void VprDeviceAnnotation::add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset) {
+void VprDeviceAnnotation::add_physical_pb_pin_rotate_offset(t_port* operating_pb_port,
+                                                            t_port* physical_pb_port,
+                                                            const int& offset) {
   /* Warn any override attempt */
-  std::map<t_port*, int>::const_iterator it = physical_pb_pin_rotate_offsets_.find(pb_port);
-  if (it != physical_pb_pin_rotate_offsets_.end()) {
-    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port pin rotate offset '%d'!\n",
-                 pb_port->name, offset);
+  std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_pin_rotate_offsets_.find(operating_pb_port);
+  if ( (it != physical_pb_pin_rotate_offsets_.end())
+    && (0 < physical_pb_pin_rotate_offsets_[operating_pb_port].count(physical_pb_port)) ) {
+    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port '%s' pin rotate offset '%d'!\n",
+                 operating_pb_port->name, offset);
   }
 
-  physical_pb_pin_rotate_offsets_[pb_port] = offset;
+  physical_pb_pin_rotate_offsets_[operating_pb_port][physical_pb_port] = offset;
   /* We initialize the accumulated offset to 0 */
-  physical_pb_pin_offsets_[pb_port] = 0;
+  physical_pb_pin_offsets_[operating_pb_port][physical_pb_port] = 0;
 }
 
 void VprDeviceAnnotation::add_physical_pb_graph_pin(const t_pb_graph_pin* operating_pb_graph_pin, 
@@ -432,17 +449,17 @@ void VprDeviceAnnotation::add_physical_pb_graph_pin(const t_pb_graph_pin* operat
    *    Physical port      |         +                        +               +
    *
    */
-  if (0 == physical_pb_pin_rotate_offset(operating_pb_graph_pin->port)) {
+  if (0 == physical_pb_pin_rotate_offset(operating_pb_graph_pin->port, physical_pb_graph_pin->port)) {
     return;
   }
 
-  physical_pb_pin_offsets_[operating_pb_graph_pin->port] += physical_pb_pin_rotate_offset(operating_pb_graph_pin->port);
+  physical_pb_pin_offsets_[operating_pb_graph_pin->port][physical_pb_graph_pin->port] += physical_pb_pin_rotate_offset(operating_pb_graph_pin->port, physical_pb_graph_pin->port);
 
-  if ((size_t)physical_pb_port(operating_pb_graph_pin->port)->num_pins - 1 
+  if ((size_t)physical_pb_graph_pin->port->num_pins - 1 
     < operating_pb_graph_pin->pin_number
-    + physical_pb_port_range(operating_pb_graph_pin->port).get_lsb() 
-    + physical_pb_pin_offsets_[operating_pb_graph_pin->port]) {
-    physical_pb_pin_offsets_[operating_pb_graph_pin->port] = 0;
+    + physical_pb_port_range(operating_pb_graph_pin->port, physical_pb_graph_pin->port).get_lsb() 
+    + physical_pb_pin_offsets_[operating_pb_graph_pin->port][physical_pb_graph_pin->port]) {
+    physical_pb_pin_offsets_[operating_pb_graph_pin->port][physical_pb_graph_pin->port] = 0;
   }
 }
 
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 00209df5c..6ac9ab4b5 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -45,8 +45,9 @@ class VprDeviceAnnotation {
     bool is_physical_pb_type(t_pb_type* pb_type) const;
     t_mode* physical_mode(t_pb_type* pb_type) const;
     t_pb_type* physical_pb_type(t_pb_type* pb_type) const;
-    t_port* physical_pb_port(t_port* pb_port) const;
-    BasicPort physical_pb_port_range(t_port* pb_port) const;
+    std::vector<t_port*> physical_pb_port(t_port* pb_port) const;
+    BasicPort physical_pb_port_range(t_port* operating_pb_port,
+                                     t_port* physical_pb_port) const;
     CircuitModelId pb_type_circuit_model(t_pb_type* physical_pb_type) const;
     CircuitModelId interconnect_circuit_model(t_interconnect* pb_interconnect) const;
     e_interconnect interconnect_physical_type(t_interconnect* pb_interconnect) const;
@@ -60,7 +61,8 @@ class VprDeviceAnnotation {
     float physical_pb_type_index_factor(t_pb_type* pb_type) const;
     int physical_pb_type_index_offset(t_pb_type* pb_type) const;
 
-    int physical_pb_pin_rotate_offset(t_port* pb_port) const;
+    int physical_pb_pin_rotate_offset(t_port* operating_pb_port,
+                                      t_port* physical_pb_port) const;
 
     /**This function returns an accumulated offset. Note that the
      * accumulated offset is NOT the pin rotate offset specified by users
@@ -69,7 +71,8 @@ class VprDeviceAnnotation {
      * by the pin rotate offset value
      * The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
      */
-    int physical_pb_pin_offset(t_port* pb_port) const;
+    int physical_pb_pin_offset(t_port* operating_pb_port,
+                               t_port* physical_pb_port) const;
     t_pb_graph_pin* physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const;
     CircuitModelId rr_switch_circuit_model(const RRSwitchId& rr_switch) const;
     CircuitModelId rr_segment_circuit_model(const RRSegmentId& rr_segment) const;
@@ -78,8 +81,11 @@ class VprDeviceAnnotation {
   public:  /* Public mutators */
     void add_pb_type_physical_mode(t_pb_type* pb_type, t_mode* physical_mode);
     void add_physical_pb_type(t_pb_type* operating_pb_type, t_pb_type* physical_pb_type);
-    void add_physical_pb_port(t_port* operating_pb_port, t_port* physical_pb_port);
-    void add_physical_pb_port_range(t_port* operating_pb_port, const BasicPort& port_range);
+    void add_physical_pb_port(t_port* operating_pb_port,
+                              t_port* physical_pb_port);
+    void add_physical_pb_port_range(t_port* operating_pb_port,
+                                    t_port* physical_pb_port,
+                                    const BasicPort& port_range);
     void add_pb_type_circuit_model(t_pb_type* physical_pb_type, const CircuitModelId& circuit_model);
     void add_interconnect_circuit_model(t_interconnect* pb_interconnect, const CircuitModelId& circuit_model);
     void add_interconnect_physical_type(t_interconnect* pb_interconnect, const e_interconnect& physical_type);
@@ -90,7 +96,9 @@ class VprDeviceAnnotation {
                                     t_pb_graph_node* physical_pb_graph_node);
     void add_physical_pb_type_index_factor(t_pb_type* pb_type, const float& factor);
     void add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset);
-    void add_physical_pb_pin_rotate_offset(t_port* pb_port, const int& offset);
+    void add_physical_pb_pin_rotate_offset(t_port* operating_pb_port,
+                                           t_port* physical_pb_port,
+                                           const int& offset);
     void add_physical_pb_graph_pin(const t_pb_graph_pin* operating_pb_graph_pin, t_pb_graph_pin* physical_pb_graph_pin);
     void add_rr_switch_circuit_model(const RRSwitchId& rr_switch, const CircuitModelId& circuit_model);
     void add_rr_segment_circuit_model(const RRSegmentId& rr_segment, const CircuitModelId& circuit_model);
@@ -139,17 +147,17 @@ class VprDeviceAnnotation {
      * Note:
      * - the parent of physical pb_port MUST be a physical pb_type
      */
-    std::map<t_port*, t_port*> physical_pb_ports_;
-    std::map<t_port*, int> physical_pb_pin_rotate_offsets_;
+    std::map<t_port*, std::vector<t_port*>> physical_pb_ports_;
+    std::map<t_port*, std::map<t_port*, int>> physical_pb_pin_rotate_offsets_;
 
     /* Accumulated offsets for a physical pb_type port, just for internal usage */
-    std::map<t_port*, int> physical_pb_pin_offsets_;
+    std::map<t_port*, std::map<t_port*, int>> physical_pb_pin_offsets_;
 
     /* Pair a pb_port to its LSB and MSB of a physical pb_port 
      * Note:
      * - the LSB and MSB MUST be in range of the physical pb_port
      */
-    std::map<t_port*, BasicPort> physical_pb_port_ranges_;
+    std::map<t_port*, std::map<t_port*, BasicPort>> physical_pb_port_ranges_;
 
     /* Pair a pb_port to a circuit port in circuit model
      * Note:

From 53f87f44b47ec19cc06cae2a92ed9d66376df1db Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Aug 2020 12:44:38 -0600
Subject: [PATCH 018/148] update documentation for the multi-port support in
 physical pb_pin

---
 docs/source/manual/arch_lang/annotate_vpr_arch.rst | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
index 39e02269c..5a6d77b14 100644
--- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
@@ -136,8 +136,12 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
 
   - ``physical_mode_pin="<string>" creates the link of ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every primitive ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match. 
 
+    .. note:: Users can define multiple ports. For example: ``physical_mode_pin="a[0:1] b[2:2]"``. When multiple ports are used, the ``physical_mode_pin_rotate_offset`` should also be adapt. For example: ``physical_mode_pin_rotate_offset="1 0"``)
+
   - ``physical_mode_pin_rotate_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. 
 
+    .. note:: If not defined, the default value of ``physical_mode_pin_rotate_offset`` is set to ``0``.
+
 .. note::
   It is highly recommended that only one physical mode is defined for a multi-mode configurable block. Try not to use nested physical mode definition. This will ease the debugging and lead to clean XML description. 
 

From 21c7eaa9cff380c45266cf0653961ed1018625c2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Aug 2020 14:06:08 -0600
Subject: [PATCH 019/148] add 36-bit fracturable multiplier Verilog

---
 openfpga_flow/VerilogNetlists/mult_36x36.v | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 openfpga_flow/VerilogNetlists/mult_36x36.v

diff --git a/openfpga_flow/VerilogNetlists/mult_36x36.v b/openfpga_flow/VerilogNetlists/mult_36x36.v
new file mode 100644
index 000000000..6fda49dd9
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/mult_36x36.v
@@ -0,0 +1,35 @@
+//-----------------------------------------------------
+// Design Name : mult_36x36
+// File Name   : mult_36x36.v
+// Function    : A 36-bit multiplier which can operate in fracturable modes:
+//               1. four 9-bit multipliers
+//               2. two 18-bit multipliers
+//               3. one 36-bit multipliers
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module mult_36x36 (
+	input [0:35] a,
+	input [0:35] b,
+	output [0:71] out,
+    input [0:1] mode);
+
+    reg [0:71] out_reg;
+
+    always @(mode, a, b) begin 
+       if (2'b01 == mode) begin
+         out_reg[0:17] <= a[0:8] * b[0:8];
+         out_reg[18:35] <= a[9:17] * b[9:17];
+         out_reg[36:53] <= a[18:26] * b[18:26];
+         out_reg[54:71] <= a[27:35] * b[27:35];
+       end else if (2'b10 == mode) begin
+         out_reg[0:35] <= a[0:17] * b[0:17];
+         out_reg[36:71] <= a[18:35] * b[18:35];
+       end else begin
+         out_reg <= a * b;
+       end
+    end
+
+    assign out = out_reg;
+
+endmodule

From 098859fe0671510fcb70e479c5fed75a49ac9e63 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Aug 2020 15:05:51 -0600
Subject: [PATCH 020/148] bug fix in the frac memory & DSP architecture

---
 ...n_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 46 +++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index d47e396ee..328ff7b57 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -315,7 +315,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 1024x32 single port RAM to the physical implementation -->
-    <pb_type name="memory[mem_1024x32_sp].mem_1024x32_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
+    <pb_type name="memory[mem_1024x32_sp].mem_1024x32_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0001">
       <port name="addr" physical_mode_port="addr1[0:9]"/>
       <port name="data" physical_mode_port="data1"/>
       <port name="we" physical_mode_port="we1"/>
@@ -323,7 +323,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 2048x16 single port RAM to the physical implementation -->
-    <pb_type name="memory[mem_2048x16_sp].mem_2048x16_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0001">
+    <pb_type name="memory[mem_2048x16_sp].mem_2048x16_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0010">
       <port name="addr" physical_mode_port="addr1[0:10]"/>
       <port name="data" physical_mode_port="data1[0:15]"/>
       <port name="we" physical_mode_port="we1"/>
@@ -331,7 +331,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 4096x8 single port RAM to the physical implementation -->
-    <pb_type name="memory[mem_4096x8_sp].mem_4096x8_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0010">
+    <pb_type name="memory[mem_4096x8_sp].mem_4096x8_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0011">
       <port name="addr" physical_mode_port="addr1[0:11]"/>
       <port name="data" physical_mode_port="data1[0:7]"/>
       <port name="we" physical_mode_port="we1"/>
@@ -339,7 +339,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 8192x4 single port RAM to the physical implementation -->
-    <pb_type name="memory[mem_8192x4_sp].mem_8192x4_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0011">
+    <pb_type name="memory[mem_8192x4_sp].mem_8192x4_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0100">
       <port name="addr" physical_mode_port="addr1[0:12]"/>
       <port name="data" physical_mode_port="data1[0:3]"/>
       <port name="we" physical_mode_port="we1"/>
@@ -347,7 +347,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 16384x2 single port RAM to the physical implementation -->
-    <pb_type name="memory[mem_16384x2_sp].mem_16384x2_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0100">
+    <pb_type name="memory[mem_16384x2_sp].mem_16384x2_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0101">
       <port name="addr" physical_mode_port="addr1[0:13]"/>
       <port name="data" physical_mode_port="data1[0:1]"/>
       <port name="we" physical_mode_port="we1"/>
@@ -355,7 +355,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 32768x1 single port RAM to the physical implementation -->
-    <pb_type name="memory[mem_32768x1_sp].mem_32768x1_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0101">
+    <pb_type name="memory[mem_32768x1_sp].mem_32768x1_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0110">
       <port name="addr" physical_mode_port="addr1[0:14]"/>
       <port name="data" physical_mode_port="data1[0:0]"/>
       <port name="we" physical_mode_port="we1"/>
@@ -363,18 +363,6 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 1024x32 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0110">
-      <port name="addr1" physical_mode_port="addr1[0:9]"/>
-      <port name="addr2" physical_mode_port="addr2[0:9]"/>
-      <port name="data1" physical_mode_port="data1[0:31]"/>
-      <port name="data2" physical_mode_port="data2[0:31]"/>
-      <port name="we1" physical_mode_port="we1"/>
-      <port name="we2" physical_mode_port="we2"/>
-      <port name="out1" physical_mode_port="out1[0:31]"/>
-      <port name="out2" physical_mode_port="out2[0:31]"/>
-      <port name="clk" physical_mode_port="clk"/>
-    </pb_type>
-    <!-- Bind the 1024x32 dual port RAM to the physical implementation -->
     <pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0111">
       <port name="addr1" physical_mode_port="addr1[0:9]"/>
       <port name="addr2" physical_mode_port="addr2[0:9]"/>
@@ -386,8 +374,20 @@
       <port name="out2" physical_mode_port="out2[0:31]"/>
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
+    <!-- Bind the 1024x32 dual port RAM to the physical implementation -->
+    <pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
+      <port name="addr1" physical_mode_port="addr1[0:9]"/>
+      <port name="addr2" physical_mode_port="addr2[0:9]"/>
+      <port name="data1" physical_mode_port="data1[0:31]"/>
+      <port name="data2" physical_mode_port="data2[0:31]"/>
+      <port name="we1" physical_mode_port="we1"/>
+      <port name="we2" physical_mode_port="we2"/>
+      <port name="out1" physical_mode_port="out1[0:31]"/>
+      <port name="out2" physical_mode_port="out2[0:31]"/>
+      <port name="clk" physical_mode_port="clk"/>
+    </pb_type>
     <!-- Bind the 2048x16 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
+    <pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
       <port name="addr1" physical_mode_port="addr1[0:10]"/>
       <port name="addr2" physical_mode_port="addr2[0:10]"/>
       <port name="data1" physical_mode_port="data1[0:15]"/>
@@ -399,7 +399,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 4096x8 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
+    <pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
       <port name="addr1" physical_mode_port="addr1[0:11]"/>
       <port name="addr2" physical_mode_port="addr2[0:11]"/>
       <port name="data1" physical_mode_port="data1[0:7]"/>
@@ -411,7 +411,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 8192x4 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
+    <pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
       <port name="addr1" physical_mode_port="addr1[0:12]"/>
       <port name="addr2" physical_mode_port="addr2[0:12]"/>
       <port name="data1" physical_mode_port="data1[0:3]"/>
@@ -423,7 +423,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 16384x2 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
+    <pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
       <port name="addr1" physical_mode_port="addr1[0:13]"/>
       <port name="addr2" physical_mode_port="addr2[0:13]"/>
       <port name="data1" physical_mode_port="data1[0:1]"/>
@@ -435,7 +435,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 32768x1 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
+    <pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1101">
       <port name="addr1" physical_mode_port="addr1[0:14]"/>
       <port name="addr2" physical_mode_port="addr2[0:14]"/>
       <port name="data1" physical_mode_port="data1[0:0]"/>

From 3ee4e10aa8b475aa9bb0831f8ec9a30b092dd139 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Aug 2020 17:25:45 -0600
Subject: [PATCH 021/148] bug fix in the frac mem & DSP vpr arch

---
 ...dder_chain_frac_mem32K_frac_dsp36_40nm.xml | 33 ++++++++++++++-----
 1 file changed, 24 insertions(+), 9 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
index 6acc37ba2..d34f3bba7 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
@@ -939,15 +939,30 @@
       <!-- Physical mode of the fracturable memory -->
       <mode name="physical">
          <pb_type name="frac_mem_32k" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-           <input name="addr1" num_pins="15"/>
-           <input name="addr2" num_pins="15"/>
-           <input name="data1" num_pins="32"/>
-           <input name="data2" num_pins="32"/>
-           <input name="we1" num_pins="1"/>
-           <input name="we2" num_pins="1"/>
-           <output name="out1" num_pins="32"/>
-           <output name="out2" num_pins="32"/>
-           <clock name="clk" num_pins="1"/>
+           <input name="addr1" num_pins="15" port_class="address1"/>
+           <input name="addr2" num_pins="15" port_class="address2"/>
+           <input name="data1" num_pins="32" port_class="data_in1"/>
+           <input name="data2" num_pins="32" port_class="data_in2"/>
+           <input name="we1" num_pins="1" port_class="write_en1"/>
+           <input name="we2" num_pins="1" port_class="write_en2"/>
+           <output name="out1" num_pins="32" port_class="data_out1"/>
+           <output name="out2" num_pins="32" port_class="data_out2"/>
+           <clock name="clk" num_pins="1" port_class="clock"/>
+
+           <T_setup value="509e-12" port="frac_mem_32k.addr1" clock="clk"/>
+           <T_setup value="509e-12" port="frac_mem_32k.addr2" clock="clk"/>
+           <T_setup value="509e-12" port="frac_mem_32k.data1" clock="clk"/>
+           <T_setup value="509e-12" port="frac_mem_32k.data2" clock="clk"/>
+           <T_setup value="509e-12" port="frac_mem_32k.we1" clock="clk"/>
+           <T_setup value="509e-12" port="frac_mem_32k.we2" clock="clk"/>
+           <T_hold value="238e-12" port="frac_mem_32k.addr1" clock="clk"/>
+           <T_hold value="238e-12" port="frac_mem_32k.addr2" clock="clk"/>
+           <T_hold value="238e-12" port="frac_mem_32k.data1" clock="clk"/>
+           <T_hold value="238e-12" port="frac_mem_32k.data2" clock="clk"/>
+           <T_hold value="238e-12" port="frac_mem_32k.we1" clock="clk"/>
+           <T_hold value="238e-12" port="frac_mem_32k.we2" clock="clk"/>
+           <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="frac_mem_32k.out1" clock="clk"/>
+           <T_clock_to_Q max="1.234e-9" min="1.196e-9" port="frac_mem_32k.out2" clock="clk"/>
          </pb_type>
          <interconnect>
           <direct name="address1" input="memory.addr1[14:0]" output="frac_mem_32k.addr1[14:0]"/>

From 42b5ea2cb10795c3771c53cf476996a088227bbd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Aug 2020 20:42:36 -0600
Subject: [PATCH 022/148] bug fix in openfpga arch for frac mem and dsp

---
 ...n_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 22 +++++--------------
 1 file changed, 5 insertions(+), 17 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index 328ff7b57..228271ce7 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -374,20 +374,8 @@
       <port name="out2" physical_mode_port="out2[0:31]"/>
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
-    <!-- Bind the 1024x32 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_1024x32_dp].mem_1024x32_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
-      <port name="addr1" physical_mode_port="addr1[0:9]"/>
-      <port name="addr2" physical_mode_port="addr2[0:9]"/>
-      <port name="data1" physical_mode_port="data1[0:31]"/>
-      <port name="data2" physical_mode_port="data2[0:31]"/>
-      <port name="we1" physical_mode_port="we1"/>
-      <port name="we2" physical_mode_port="we2"/>
-      <port name="out1" physical_mode_port="out1[0:31]"/>
-      <port name="out2" physical_mode_port="out2[0:31]"/>
-      <port name="clk" physical_mode_port="clk"/>
-    </pb_type>
     <!-- Bind the 2048x16 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
+    <pb_type name="memory[mem_2048x16_dp].mem_2048x16_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1000">
       <port name="addr1" physical_mode_port="addr1[0:10]"/>
       <port name="addr2" physical_mode_port="addr2[0:10]"/>
       <port name="data1" physical_mode_port="data1[0:15]"/>
@@ -399,7 +387,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 4096x8 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
+    <pb_type name="memory[mem_4096x8_dp].mem_4096x8_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1001">
       <port name="addr1" physical_mode_port="addr1[0:11]"/>
       <port name="addr2" physical_mode_port="addr2[0:11]"/>
       <port name="data1" physical_mode_port="data1[0:7]"/>
@@ -411,7 +399,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 8192x4 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
+    <pb_type name="memory[mem_8192x4_dp].mem_8192x4_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1010">
       <port name="addr1" physical_mode_port="addr1[0:12]"/>
       <port name="addr2" physical_mode_port="addr2[0:12]"/>
       <port name="data1" physical_mode_port="data1[0:3]"/>
@@ -423,7 +411,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 16384x2 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
+    <pb_type name="memory[mem_16384x2_dp].mem_16384x2_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1011">
       <port name="addr1" physical_mode_port="addr1[0:13]"/>
       <port name="addr2" physical_mode_port="addr2[0:13]"/>
       <port name="data1" physical_mode_port="data1[0:1]"/>
@@ -435,7 +423,7 @@
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 32768x1 dual port RAM to the physical implementation -->
-    <pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1101">
+    <pb_type name="memory[mem_32768x1_dp].mem_32768x1_dp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="1100">
       <port name="addr1" physical_mode_port="addr1[0:14]"/>
       <port name="addr2" physical_mode_port="addr2[0:14]"/>
       <port name="data1" physical_mode_port="data1[0:0]"/>

From 743167521a200c11e2ab32c711062c696a047f90 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 18 Aug 2020 21:13:46 -0600
Subject: [PATCH 023/148] add Verilog design for fracturable 32k memory

---
 openfpga_flow/VerilogNetlists/frac_mem_32k.v | 371 +++++++++++++++++++
 1 file changed, 371 insertions(+)
 create mode 100644 openfpga_flow/VerilogNetlists/frac_mem_32k.v

diff --git a/openfpga_flow/VerilogNetlists/frac_mem_32k.v b/openfpga_flow/VerilogNetlists/frac_mem_32k.v
new file mode 100644
index 000000000..2d0b8fd26
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/frac_mem_32k.v
@@ -0,0 +1,371 @@
+//-----------------------------------------------------
+// Design Name : frac_mem_32k
+// File Name   : frac_mem_32k.v
+// Function    : A fracturable BRAM which can operate in 13 modes
+//               - Single port RAM 512x64 bit 
+//               - Single port RAM 1024x32 bit 
+//               - Single port RAM 2048x16 bit 
+//               - Single port RAM 4096x8 bit 
+//               - Single port RAM 8192x4 bit 
+//               - Single port RAM 16384x2 bit 
+//               - Single port RAM 32768x1 bit 
+//               - Dual port RAM 1024x32
+//               - Dual port RAM 2048x16 bit 
+//               - Dual port RAM 4096x8 bit 
+//               - Dual port RAM 8192x4 bit 
+//               - Dual port RAM 16384x2 bit 
+//               - Dual port RAM 32768x1 bit 
+//               Inspired by the dual port ram Verilog from
+//               https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/design-software/vhdl/vhd-true-dual-port-ram-sclk.html
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module frac_mem_32k (
+  input [0:14] addr_a,
+  input [0:14] addr_b,
+  input [0:31] data_a,
+  input [0:31] data_b,
+  input we_a,
+  input we_b,
+  output reg [0:31] q_a,
+  output reg [0:31] q_b,
+  input clk,
+  input [0:3] mode);
+
+  reg [0:9] ram_a [0:31];
+  reg [0:9] ram_b [0:31];
+
+  always @(posedge clk) begin
+    // Operating mode: single port RAM 512 x 64
+    if (4'b0000 == mode) begin 
+      if (we_a) begin
+        ram_a[addr_a[0:8]] <= data_a;
+        ram_b[addr_a[0:8]] <= data_b;
+        q_a <= data_a;
+        q_b <= data_b;
+      end else begin
+        q_a <= ram_a[addr_a[0:8]];
+        q_b <= ram_b[addr_a[0:8]];
+      end 
+    // Operating mode: single port RAM 1024 x 32
+    end else if (4'b0001 == mode) begin
+      if (we_a) begin
+        ram_a[addr_a[0:9]] <= data_a;
+      end else begin
+        q_a <= ram_a[addr_a[0:9]];
+      end
+    // Operating mode: single port RAM 2048 x 16
+    end else if (4'b0010 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:10])
+          1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a[0:15];
+          1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a[0:15];
+        endcase
+      end else begin
+        case (addr_a[10:10])
+          1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
+          1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
+        endcase
+      end
+    // Operating mode: single port RAM 4096 x 8
+    end else if (4'b0011 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:11])
+          2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
+          2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
+          2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
+          2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
+        endcase
+      end else begin
+        case (addr_a[10:11])
+          2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
+          2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
+          2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
+          2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
+        endcase
+      end
+    // Operating mode: single port RAM 8192 x 4
+    end else if (4'b0100 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:12])
+          3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
+          3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
+          3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
+          3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
+          3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
+          3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
+          3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
+          3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
+        endcase
+      end else begin
+        case (addr_a[10:12])
+          3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
+          3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
+          3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
+          3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
+          3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
+          3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
+          3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
+          3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
+        endcase
+      end
+    // Operating mode: single port RAM 16384 x 2
+    end else if (4'b0101 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:13])
+          4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
+          4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
+          4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
+          4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
+          4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
+          4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
+          4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
+          4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
+          4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
+          4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
+          4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
+          4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
+          4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
+          4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
+          4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
+          4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
+        endcase
+      end else begin
+        case (addr_a[10:13])
+          4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
+          4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
+          4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
+          4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
+          4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
+          4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
+          4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
+          4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
+          4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
+          4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
+          4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
+          4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
+          4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
+          4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
+          4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
+          4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
+        endcase
+      end
+    // Operating mode: single port RAM 32768 x 1
+    end else if (4'b0110 == mode) begin
+      if (we_a) begin
+        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];
+      end else begin
+        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
+      end
+    // Operating mode: dual port RAM 1024 x 32
+    end else if (4'b0111 == mode) begin 
+      if (we_a) begin
+        ram_a[addr_a[0:9]] <= data_a;
+        ram_b[addr_b[0:9]] <= data_b;
+        q_a <= data_a;
+        q_b <= data_b;
+      end else begin
+        q_a <= ram_a[addr_a[0:9]];
+        q_b <= ram_b[addr_b[0:9]];
+      end 
+    // Operating mode: dual port RAM 2048 x 16
+    end else if (4'b1000 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:10])
+          1'b0 : ram_a[addr_a[0:9]][0:15] <= data_a;
+          1'b1 : ram_a[addr_a[0:9]][16:31] <= data_a;
+        endcase
+      end else begin
+        case (addr_a[10:10])
+          1'b0 : q_a <= ram_a[addr_a[0:9]][0:15];
+          1'b1 : q_a <= ram_a[addr_a[0:9]][16:31];
+        endcase
+      end
+
+      if (we_b) begin
+        case (addr_b[10:10])
+          1'b0 : ram_b[addr_b[0:9]][0:15] <= data_b;
+          1'b1 : ram_b[addr_b[0:9]][16:31] <= data_b;
+        endcase
+      end else begin
+        case (addr_b[10:10])
+          1'b0 : q_b <= ram_b[addr_b[0:9]][0:15];
+          1'b1 : q_b <= ram_b[addr_b[0:9]][16:31];
+        endcase
+      end
+    // Operating mode: dual port RAM 4096 x 8
+    end else if (4'b1001 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:11])
+          2'b00 : ram_a[addr_a[0:9]][0:7] <= data_a[0:7];
+          2'b01 : ram_a[addr_a[0:9]][8:15] <= data_a[0:7];
+          2'b10 : ram_a[addr_a[0:9]][16:23] <= data_a[0:7];
+          2'b11 : ram_a[addr_a[0:9]][24:31] <= data_a[0:7];
+        endcase
+      end else begin
+        case (addr_a[10:11])
+          2'b00 : q_a <= ram_a[addr_a[0:9]][0:7];
+          2'b01 : q_a <= ram_a[addr_a[0:9]][8:15];
+          2'b10 : q_a <= ram_a[addr_a[0:9]][16:23];
+          2'b11 : q_a <= ram_a[addr_a[0:9]][24:31];
+        endcase
+      end
+
+      if (we_b) begin
+        case (addr_b[10:11])
+          2'b00 : ram_b[addr_b[0:9]][0:7] <= data_b[0:7];
+          2'b01 : ram_b[addr_b[0:9]][8:15] <= data_b[0:7];
+          2'b10 : ram_b[addr_b[0:9]][16:23] <= data_b[0:7];
+          2'b11 : ram_b[addr_b[0:9]][24:31] <= data_b[0:7];
+        endcase
+      end else begin
+        case (addr_b[10:11])
+          2'b00 : q_b <= ram_b[addr_b[0:9]][0:7];
+          2'b01 : q_b <= ram_b[addr_b[0:9]][8:15];
+          2'b10 : q_b <= ram_b[addr_b[0:9]][16:23];
+          2'b11 : q_b <= ram_b[addr_b[0:9]][24:31];
+        endcase
+      end
+    // Operating mode: dual port RAM 8192 x 4
+    end else if (4'b1011 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:12])
+          3'b000 : ram_a[addr_a[0:9]][0:3] <= data_a[0:3];
+          3'b001 : ram_a[addr_a[0:9]][4:7] <= data_a[0:3];
+          3'b010 : ram_a[addr_a[0:9]][8:11] <= data_a[0:3];
+          3'b011 : ram_a[addr_a[0:9]][12:15] <= data_a[0:3];
+          3'b100 : ram_a[addr_a[0:9]][16:19] <= data_a[0:3];
+          3'b101 : ram_a[addr_a[0:9]][20:23] <= data_a[0:3];
+          3'b110 : ram_a[addr_a[0:9]][24:27] <= data_a[0:3];
+          3'b111 : ram_a[addr_a[0:9]][28:31] <= data_a[0:3];
+        endcase
+      end else begin
+        case (addr_a[10:12])
+          3'b000 : q_a <= ram_a[addr_a[0:9]][0:3];
+          3'b001 : q_a <= ram_a[addr_a[0:9]][4:7];
+          3'b010 : q_a <= ram_a[addr_a[0:9]][8:11];
+          3'b011 : q_a <= ram_a[addr_a[0:9]][12:15];
+          3'b100 : q_a <= ram_a[addr_a[0:9]][16:19];
+          3'b101 : q_a <= ram_a[addr_a[0:9]][20:23];
+          3'b110 : q_a <= ram_a[addr_a[0:9]][24:27];
+          3'b111 : q_a <= ram_a[addr_a[0:9]][28:31];
+        endcase
+      end
+      if (we_b) begin
+        case (addr_b[10:12])
+          3'b000 : ram_b[addr_b[0:9]][0:3] <= data_b[0:3];
+          3'b001 : ram_b[addr_b[0:9]][4:7] <= data_b[0:3];
+          3'b010 : ram_b[addr_b[0:9]][8:11] <= data_b[0:3];
+          3'b011 : ram_b[addr_b[0:9]][12:15] <= data_b[0:3];
+          3'b100 : ram_b[addr_b[0:9]][16:19] <= data_b[0:3];
+          3'b101 : ram_b[addr_b[0:9]][20:23] <= data_b[0:3];
+          3'b110 : ram_b[addr_b[0:9]][24:27] <= data_b[0:3];
+          3'b111 : ram_b[addr_b[0:9]][28:31] <= data_b[0:3];
+        endcase
+      end else begin
+        case (addr_b[10:12])
+          3'b000 : q_b <= ram_b[addr_b[0:9]][0:3];
+          3'b001 : q_b <= ram_b[addr_b[0:9]][4:7];
+          3'b010 : q_b <= ram_b[addr_b[0:9]][8:11];
+          3'b011 : q_b <= ram_b[addr_b[0:9]][12:15];
+          3'b100 : q_b <= ram_b[addr_b[0:9]][16:19];
+          3'b101 : q_b <= ram_b[addr_b[0:9]][20:23];
+          3'b110 : q_b <= ram_b[addr_b[0:9]][24:27];
+          3'b111 : q_b <= ram_b[addr_b[0:9]][28:31];
+        endcase
+      end
+    // Operating mode: dual port RAM 16384 x 2
+    end else if (4'b1100 == mode) begin
+      if (we_a) begin
+        case (addr_a[10:13])
+          4'b0000 : ram_a[addr_a[0:9]][0:1] <= data_a[0:1];
+          4'b0001 : ram_a[addr_a[0:9]][2:3] <= data_a[0:1];
+          4'b0010 : ram_a[addr_a[0:9]][4:5] <= data_a[0:1];
+          4'b0011 : ram_a[addr_a[0:9]][6:7] <= data_a[0:1];
+          4'b0100 : ram_a[addr_a[0:9]][8:9] <= data_a[0:1];
+          4'b0101 : ram_a[addr_a[0:9]][10:11] <= data_a[0:1];
+          4'b0110 : ram_a[addr_a[0:9]][12:13] <= data_a[0:1];
+          4'b0111 : ram_a[addr_a[0:9]][14:15] <= data_a[0:1];
+          4'b1000 : ram_a[addr_a[0:9]][16:17] <= data_a[0:1];
+          4'b1001 : ram_a[addr_a[0:9]][18:19] <= data_a[0:1];
+          4'b1010 : ram_a[addr_a[0:9]][20:21] <= data_a[0:1];
+          4'b1011 : ram_a[addr_a[0:9]][22:23] <= data_a[0:1];
+          4'b1100 : ram_a[addr_a[0:9]][24:25] <= data_a[0:1];
+          4'b1101 : ram_a[addr_a[0:9]][26:27] <= data_a[0:1];
+          4'b1110 : ram_a[addr_a[0:9]][28:29] <= data_a[0:1];
+          4'b1111 : ram_a[addr_a[0:9]][30:31] <= data_a[0:1];
+        endcase
+      end else begin
+        case (addr_a[10:13])
+          4'b0000 : q_a <= ram_a[addr_a[0:9]][0:1];
+          4'b0001 : q_a <= ram_a[addr_a[0:9]][2:3];
+          4'b0010 : q_a <= ram_a[addr_a[0:9]][4:5];
+          4'b0011 : q_a <= ram_a[addr_a[0:9]][6:7];
+          4'b0100 : q_a <= ram_a[addr_a[0:9]][8:9];
+          4'b0101 : q_a <= ram_a[addr_a[0:9]][10:11];
+          4'b0110 : q_a <= ram_a[addr_a[0:9]][12:13];
+          4'b0111 : q_a <= ram_a[addr_a[0:9]][14:15];
+          4'b1000 : q_a <= ram_a[addr_a[0:9]][16:17];
+          4'b1001 : q_a <= ram_a[addr_a[0:9]][18:19];
+          4'b1010 : q_a <= ram_a[addr_a[0:9]][20:21];
+          4'b1011 : q_a <= ram_a[addr_a[0:9]][22:23];
+          4'b1100 : q_a <= ram_a[addr_a[0:9]][24:25];
+          4'b1101 : q_a <= ram_a[addr_a[0:9]][26:27];
+          4'b1110 : q_a <= ram_a[addr_a[0:9]][28:29];
+          4'b1111 : q_a <= ram_a[addr_a[0:9]][30:31];
+        endcase
+      end
+      if (we_b) begin
+        case (addr_b[10:13])
+          4'b0000 : ram_b[addr_b[0:9]][0:1] <= data_b[0:1];
+          4'b0001 : ram_b[addr_b[0:9]][2:3] <= data_b[0:1];
+          4'b0010 : ram_b[addr_b[0:9]][4:5] <= data_b[0:1];
+          4'b0011 : ram_b[addr_b[0:9]][6:7] <= data_b[0:1];
+          4'b0100 : ram_b[addr_b[0:9]][8:9] <= data_b[0:1];
+          4'b0101 : ram_b[addr_b[0:9]][10:11] <= data_b[0:1];
+          4'b0110 : ram_b[addr_b[0:9]][12:13] <= data_b[0:1];
+          4'b0111 : ram_b[addr_b[0:9]][14:15] <= data_b[0:1];
+          4'b1000 : ram_b[addr_b[0:9]][16:17] <= data_b[0:1];
+          4'b1001 : ram_b[addr_b[0:9]][18:19] <= data_b[0:1];
+          4'b1010 : ram_b[addr_b[0:9]][20:21] <= data_b[0:1];
+          4'b1011 : ram_b[addr_b[0:9]][22:23] <= data_b[0:1];
+          4'b1100 : ram_b[addr_b[0:9]][24:25] <= data_b[0:1];
+          4'b1101 : ram_b[addr_b[0:9]][26:27] <= data_b[0:1];
+          4'b1110 : ram_b[addr_b[0:9]][28:29] <= data_b[0:1];
+          4'b1111 : ram_b[addr_b[0:9]][30:31] <= data_b[0:1];
+        endcase
+      end else begin
+        case (addr_b[10:13])
+          4'b0000 : q_b <= ram_b[addr_b[0:9]][0:1];
+          4'b0001 : q_b <= ram_b[addr_b[0:9]][2:3];
+          4'b0010 : q_b <= ram_b[addr_b[0:9]][4:5];
+          4'b0011 : q_b <= ram_b[addr_b[0:9]][6:7];
+          4'b0100 : q_b <= ram_b[addr_b[0:9]][8:9];
+          4'b0101 : q_b <= ram_b[addr_b[0:9]][10:11];
+          4'b0110 : q_b <= ram_b[addr_b[0:9]][12:13];
+          4'b0111 : q_b <= ram_b[addr_b[0:9]][14:15];
+          4'b1000 : q_b <= ram_b[addr_b[0:9]][16:17];
+          4'b1001 : q_b <= ram_b[addr_b[0:9]][18:19];
+          4'b1010 : q_b <= ram_b[addr_b[0:9]][20:21];
+          4'b1011 : q_b <= ram_b[addr_b[0:9]][22:23];
+          4'b1100 : q_b <= ram_b[addr_b[0:9]][24:25];
+          4'b1101 : q_b <= ram_b[addr_b[0:9]][26:27];
+          4'b1110 : q_b <= ram_b[addr_b[0:9]][28:29];
+          4'b1111 : q_b <= ram_b[addr_b[0:9]][30:31];
+        endcase
+      end
+    // Operating mode: dual port RAM 32768 x 1
+    end else if (4'b1101 == mode) begin
+      if (we_a) begin
+        ram_a[addr_a[0:9]][addr_a[10:14]] = data_a[0:0];
+      end else begin
+        q_a <= ram_a[addr_a[0:9]][addr_a[10:14]];
+      end
+      if (we_b) begin
+        ram_b[addr_b[0:9]][addr_b[10:14]] = data_b[0:0];
+      end else begin
+        q_b <= ram_b[addr_b[0:9]][addr_b[10:14]];
+      end
+    end
+  end
+endmodule

From dbd93e429d699d6509687669a425d7bf9a02c230 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 09:43:44 -0600
Subject: [PATCH 024/148] now pro_blif.pl can accept customized clock name

---
 openfpga_flow/scripts/pro_blif.pl | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/openfpga_flow/scripts/pro_blif.pl b/openfpga_flow/scripts/pro_blif.pl
index 40203e136..f3cb0e99b 100755
--- a/openfpga_flow/scripts/pro_blif.pl
+++ b/openfpga_flow/scripts/pro_blif.pl
@@ -25,8 +25,9 @@ sub print_usage()
   print "              -i <input_blif_path>\n";
   print "              -o <output_blif_path>\n";
   print "      Options: (Optional)\n";
-  print "              -remove_buffers\n";
-  print "              -add_default_clk\n";
+  print "              -remove_buffers: remove buffers in the blif\n";
+  print "              -add_default_clk: add a default clock using the default clock name 'clk', or set by users through the option '-default clk'\n";
+  print "              -default_clk <clk_name>: set the default clk name to be used by .latch\n";
   print "              -initial_blif <input_blif_path>\n";
   print "\n";
   return 0;
@@ -46,6 +47,8 @@ sub opts_read()
         $frpt = $ARGV[$iargv+1];
       } elsif ("-add_default_clk" eq $ARGV[$iargv]) {
         $add_default_clk = "on";
+      } elsif ("-default_clk" eq $ARGV[$iargv]) {
+        $default_clk_name = $ARGV[$iargv+1];
       } elsif ("-initial_blif" eq $ARGV[$iargv]) {
         $finitial = $ARGV[$iargv+1];
       } elsif ("-remove_buffers" eq $ARGV[$iargv]) {
@@ -219,7 +222,7 @@ sub scan_blif()
   my ($line_no) = (0);
 
   if (!defined($finitial)) {
-    $latch_token = "re clk";
+    $latch_token = "re $default_clk_name";
   } else {
     my $latch_token_found = 0;
     my $count = 0;

From d7efdf35b62b77a784c68935fdb69e4305222dca Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 11:15:25 -0600
Subject: [PATCH 025/148] add custom pin location to the flagship vpr arch with
 frac mem and dsp

---
 ...adder_chain_frac_mem32K_frac_dsp36_40nm.xml | 18 ++++++++++++++++--
 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
index d34f3bba7..c56ce6041 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
@@ -223,7 +223,14 @@
       <input name="b" num_pins="36"/>
       <output name="out" num_pins="72"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top"></loc>
+        <loc side="right">mult_36.a[0:17] mult_36.b[0:17] mult_36.out[0:35]</loc>
+        <loc side="bottom">mult_36.a[18:35] mult_36.b[18:35] mult_36.out[36:71]</loc>
+      </pinlocations>
     </tile>
     <tile name="memory" height="6" area="548000">
       <equivalent_sites>
@@ -237,7 +244,14 @@
       <output name="out" num_pins="64"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">memory.clk</loc>
+        <loc side="right">memory.addr1[0:14] memory.data[0:31] memory.we1 memory.out[0:31]</loc>
+        <loc side="bottom">memory.addr2[0:14] memory.data[32:63] memory.we2 memory.out[32:63]</loc>
+      </pinlocations>
     </tile>
   </tiles>
   <!-- ODIN II specific config ends -->

From af1c7c6f29900f2d02aee74d5ff6815808933e7b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 12:18:35 -0600
Subject: [PATCH 026/148] start fixing the bug in thru channels

---
 .../rr_graph_builder_utils.cpp                | 35 +++++++++++++++++--
 .../rr_graph_builder_utils.h                  |  6 ++--
 .../tileable_rr_graph_node_builder.cpp        | 13 ++++---
 3 files changed, 46 insertions(+), 8 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
index a599c8194..3bf54a6d5 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.cpp
@@ -172,7 +172,21 @@ size_t get_grid_num_classes(const t_grid_tile& cur_grid,
  *  When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block
  ***********************************************************************/
 bool is_chanx_exist(const DeviceGrid& grids,
-                    const vtr::Point<size_t>& chanx_coord) {
+                    const vtr::Point<size_t>& chanx_coord,
+                    const bool& through_channel) {
+
+  if ((1 > chanx_coord.x()) || (chanx_coord.x() > grids.width() - 2)) {
+    return false;
+  }
+
+  if (chanx_coord.y() > grids.height() - 2) {
+    return false;
+  }
+
+  if (true == through_channel) {
+    return true;
+  }
+
   return (grids[chanx_coord.x()][chanx_coord.y()].height_offset == grids[chanx_coord.x()][chanx_coord.y()].type->height - 1);
 }
 
@@ -192,9 +206,26 @@ bool is_chanx_exist(const DeviceGrid& grids,
  *  If the CHANY is in the middle of a multi-width and multi-height grid
  *  it should locate at a grid whose width_offset is lower than the its width defined in physical_tile
  *  When height_offset == height - 1, it means that the grid is at the top side of this multi-width and multi-height block
+ *
+ *  If through channel is allowed, the chany will always exists
+ *  unless it falls out of the grid array
  ***********************************************************************/
 bool is_chany_exist(const DeviceGrid& grids,
-                    const vtr::Point<size_t>& chany_coord) {
+                    const vtr::Point<size_t>& chany_coord,
+                    const bool& through_channel) {
+
+  if (chany_coord.x() > grids.width() - 2) {
+    return false;
+  }
+
+  if ((1 > chany_coord.y()) || (chany_coord.y() > grids.height() - 2)) {
+    return false;
+  }
+
+  if (true == through_channel) {
+    return true;
+  }
+
   return (grids[chany_coord.x()][chany_coord.y()].width_offset == grids[chany_coord.x()][chany_coord.y()].type->width - 1);
 }
 
diff --git a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
index 23e030d9b..6ff78412f 100644
--- a/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
+++ b/vpr/src/tileable_rr_graph/rr_graph_builder_utils.h
@@ -40,10 +40,12 @@ size_t get_grid_num_classes(const t_grid_tile& cur_grid,
                             const e_pin_type& pin_type);
 
 bool is_chanx_exist(const DeviceGrid& grids,
-                    const vtr::Point<size_t>& chanx_coord);
+                    const vtr::Point<size_t>& chanx_coord,
+                    const bool& through_channel=false);
 
 bool is_chany_exist(const DeviceGrid& grids,
-                    const vtr::Point<size_t>& chany_coord);
+                    const vtr::Point<size_t>& chany_coord,
+                    const bool& through_channel=false);
 
 bool is_chanx_right_to_multi_height_grid(const DeviceGrid& grids,
                                          const vtr::Point<size_t>& chanx_coord,
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 753c455ff..4107d4538 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -186,7 +186,8 @@ size_t estimate_num_chanx_rr_nodes(const DeviceGrid& grids,
       vtr::Point<size_t> chanx_coord(ix, iy);
 
       /* Bypass if the routing channel does not exist when through channels are not allowed */
-      if (false == is_chanx_exist(grids, chanx_coord)) {
+      if ( (false == through_channel)
+        && (false == is_chanx_exist(grids, chanx_coord))) {
         continue;
       }
 
@@ -237,11 +238,13 @@ size_t estimate_num_chany_rr_nodes(const DeviceGrid& grids,
     for (size_t iy = 1; iy < grids.height() - 1; ++iy) { 
       vtr::Point<size_t> chany_coord(ix, iy);
 
-      /* Bypass if the routing channel does not exist when through channels are not allowed */
-      if (false == is_chany_exist(grids, chany_coord)) {
+      /* Bypass if the routing channel does not exist when through channel are not allowed */
+      if ( (false == through_channel)
+        && (false == is_chany_exist(grids, chany_coord))) {
         continue;
       }
 
+
       bool force_start = false;
       bool force_end = false;
 
@@ -922,7 +925,9 @@ void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
 
       ChanNodeDetails chany_details = build_unidir_chan_node_details(chan_width, grids.height() - 2,
                                                                      force_start, force_end, segment_infs); 
-      /* Force node_ids from the previous chanx */
+      /* Force node_ids from the previous chany
+       * This will not be applied when the routing channel is cut off (force to start)
+       */
       if (0 < track_node_ids.size()) {
         /* Rotate should be done based on a typical case of routing tracks.
          * Tracks on the borders are not regularly started and ended, 

From f64079641d1ee4954a91572726af06434e795336 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 12:43:58 -0600
Subject: [PATCH 027/148] bug fix in flagship vpr arch with frac mem and dsp

---
 ...c_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index 228271ce7..b2fa706af 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -287,7 +287,7 @@
          There are four 9x9 multipliers, each of which occupies part
          of the input/output of the 36x36 multiplier
       -->
-    <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
+    <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[two_mult_9x9].mult_9x9_slice.mult_9x9" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="01" physical_pb_type_index_factor="0">
       <port name="a" physical_mode_port="a[0:8]" physical_mode_pin_rotate_offset="9"/>
       <port name="b" physical_mode_port="b[0:8]" physical_mode_pin_rotate_offset="9"/>
       <port name="out" physical_mode_port="out[0:17]" physical_mode_pin_rotate_offset="18"/>
@@ -296,7 +296,7 @@
          There are two 18x18 multipliers, each of which occupies part
          of the input/output of the 36x36 multiplier
       -->
-    <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
+    <pb_type name="mult_36[two_divisible_mult_18x18].divisible_mult_18x18[mult_18x18].mult_18x18_slice.mult_18x18" physical_pb_type_name="mult_36[mult_36x36].mult_36x36_slice.mult_36x36" mode_bits="10" physical_pb_type_index_factor="0">
       <port name="a" physical_mode_port="a[0:17]" physical_mode_pin_rotate_offset="18"/>
       <port name="b" physical_mode_port="b[0:17]" physical_mode_pin_rotate_offset="18"/>
       <port name="out" physical_mode_port="out[0:35]" physical_mode_pin_rotate_offset="36"/>

From 79b6ff3cb08b1c20612bf5c6d6755fb0966ad0b4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 12:44:51 -0600
Subject: [PATCH 028/148] relax checking for device annotation as we support
 multi-port during physical mode pin mapping

---
 openfpga/src/annotation/vpr_device_annotation.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index 71b3baf63..f196f50da 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -298,7 +298,7 @@ void VprDeviceAnnotation::add_physical_pb_port_range(t_port* operating_pb_port,
                                                      t_port* physical_pb_port,
                                                      const BasicPort& port_range) {
   /* The port range must satify the port width*/
-  VTR_ASSERT((size_t)operating_pb_port->num_pins == port_range.get_width());
+  VTR_ASSERT((size_t)operating_pb_port->num_pins >= port_range.get_width());
 
   /* Warn any override attempt */
   std::map<t_port*, std::map<t_port*, BasicPort>>::const_iterator it = physical_pb_port_ranges_.find(operating_pb_port);

From f631245b2b85f79376a475b668ee767ca82057fe Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 13:41:04 -0600
Subject: [PATCH 029/148] bug fix and enriched debugging info print out

---
 openfpga/src/annotation/annotate_pb_graph.cpp | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 93a154222..249cb5632 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -337,6 +337,9 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
     /* Reach here, it means all the requirements have been met */
     return true;
   }
+
+  /* If we reach here, we failed */
+  return false;
 }
 
 /********************************************************************
@@ -426,7 +429,7 @@ void annotate_physical_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
 
   /* If we reach here, it means that pin pairing fails, error out! */
   VTR_LOG_ERROR("Fail to match a physical pin for '%s' from pb_graph_node '%s'!\n",
-                operating_pb_graph_pin->port->name,
+                operating_pb_graph_pin->to_string().c_str(),
                 physical_pb_graph_node->hierarchical_type_name().c_str());
 }
 

From 3eea12ceaed12df0e6693310058d97dd3cce00d1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 14:43:44 -0600
Subject: [PATCH 030/148] added a new XML syntax: initial offset for physical
 mode pin mapping

---
 .../src/pb_type_annotation.cpp                | 45 ++++++++++++++-----
 .../libarchopenfpga/src/pb_type_annotation.h  | 32 ++++++++++---
 .../src/read_xml_pb_type_annotation.cpp       | 25 +++++++++++
 .../src/write_xml_pb_type_annotation.cpp      | 10 ++++-
 openfpga/src/annotation/annotate_pb_graph.cpp | 28 ++++++++----
 openfpga/src/annotation/annotate_pb_types.cpp |  7 +--
 .../src/annotation/vpr_device_annotation.cpp  | 30 ++++++++++++-
 .../src/annotation/vpr_device_annotation.h    |  7 +++
 8 files changed, 152 insertions(+), 32 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
index 133ee000c..9a369e742 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.cpp
@@ -86,11 +86,11 @@ std::vector<std::string> PbTypeAnnotation::port_names() const {
   return keys;
 }
 
-std::map<BasicPort, int> PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const {
-  std::map<std::string, std::map<BasicPort, int>>::const_iterator it = operating_pb_type_ports_.find(port_name);
+std::map<BasicPort, std::array<int, 2>> PbTypeAnnotation::physical_pb_type_port(const std::string& port_name) const {
+  std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(port_name);
   if (it == operating_pb_type_ports_.end()) {
     /* Return an empty port */
-    return std::map<BasicPort, int>();
+    return std::map<BasicPort, std::array<int, 2>>();
   }
   return operating_pb_type_ports_.at(port_name);
 }
@@ -169,25 +169,25 @@ void PbTypeAnnotation::set_physical_pb_type_index_offset(const int& value) {
 void PbTypeAnnotation::add_pb_type_port_pair(const std::string& operating_pb_port_name,
                                              const BasicPort& physical_pb_port) {
   /* Give a warning if the operating_pb_port_name already exist */
-  std::map<std::string, std::map<BasicPort, int>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
+  std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
 
   /* If not exist, initialize and set a default value */
   if (it == operating_pb_type_ports_.end()) {
-    operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = 0;
+    operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0};
     /* We can return early */
     return;
   }
 
   /* If the physical port is not in the list, we create one and set a default value */
   if (0 == operating_pb_type_ports_[operating_pb_port_name].count(physical_pb_port)) {
-    operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = 0;
+    operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = {0, 0};
   }
 }
 
-void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
-                                                      const BasicPort& physical_pb_port,
-                                                      const int& physical_pin_rotate_offset) {
-  std::map<std::string, std::map<BasicPort, int>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
+void PbTypeAnnotation::set_physical_pin_initial_offset(const std::string& operating_pb_port_name,
+                                                       const BasicPort& physical_pb_port,
+                                                       const int& physical_pin_initial_offset) {
+  std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
 
   if (it == operating_pb_type_ports_.end()) {
     VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n",
@@ -204,7 +204,30 @@ void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operati
     exit(1);
   }
 
-  operating_pb_type_ports_[operating_pb_port_name][physical_pb_port] = physical_pin_rotate_offset;
+  operating_pb_type_ports_[operating_pb_port_name][physical_pb_port][0] = physical_pin_initial_offset;
+}
+
+void PbTypeAnnotation::set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
+                                                      const BasicPort& physical_pb_port,
+                                                      const int& physical_pin_rotate_offset) {
+  std::map<std::string, std::map<BasicPort, std::array<int, 2>>>::const_iterator it = operating_pb_type_ports_.find(operating_pb_port_name);
+
+  if (it == operating_pb_type_ports_.end()) {
+    VTR_LOG_ERROR("The operating pb_type port '%s' is not valid!\n",
+                  operating_pb_port_name.c_str());
+    exit(1);
+  }
+
+  if (operating_pb_type_ports_[operating_pb_port_name].end() == operating_pb_type_ports_[operating_pb_port_name].find(physical_pb_port)) {
+    VTR_LOG_ERROR("The physical pb_type port '%s[%lu:%lu]' definition for operating pb_type port '%s' is not valid!\n",
+                  physical_pb_port.get_name().c_str(),
+                  physical_pb_port.get_lsb(),
+                  physical_pb_port.get_msb(),
+                  operating_pb_port_name.c_str());
+    exit(1);
+  }
+
+  operating_pb_type_ports_[operating_pb_port_name][physical_pb_port][1] = physical_pin_rotate_offset;
 }
 
 void PbTypeAnnotation::add_interconnect_circuit_model_pair(const std::string& interc_name,
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index 4e1d4e8a2..33941bce3 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -6,6 +6,7 @@
  *******************************************************************/
 #include <vector>
 #include <map>
+#include <array>
 
 #include "openfpga_port.h"
 
@@ -48,7 +49,7 @@ class PbTypeAnnotation {
     float physical_pb_type_index_factor() const;
     int physical_pb_type_index_offset() const;
     std::vector<std::string> port_names() const;
-    std::map<BasicPort, int> physical_pb_type_port(const std::string& port_name) const;
+    std::map<BasicPort, std::array<int, 2>> physical_pb_type_port(const std::string& port_name) const;
     std::vector<std::string> interconnect_names() const;
     std::string interconnect_circuit_model_name(const std::string& interc_name) const;
   public: /* Public mutators */
@@ -66,6 +67,9 @@ class PbTypeAnnotation {
     void set_physical_pb_type_index_offset(const int& value);
     void add_pb_type_port_pair(const std::string& operating_pb_port_name,
                                const BasicPort& physical_pb_port);
+    void set_physical_pin_initial_offset(const std::string& operating_pb_port_name,
+                                         const BasicPort& physical_pb_port,
+                                         const int& physical_pin_initial_offset);
     void set_physical_pin_rotate_offset(const std::string& operating_pb_port_name,
                                         const BasicPort& physical_pb_port,
                                         const int& physical_pin_rotate_offset);
@@ -134,8 +138,12 @@ class PbTypeAnnotation {
     int physical_pb_type_index_offset_;
 
     /* Link from the pins under an operating pb_type to pairs of
-     * its physical pb_type and its pin rotating offset
-     * The offset aims to align the pin indices for port of pb_type 
+     * its physical pb_type and its pin initial & rotating offset
+     *
+     * Note that initial offset is the first element of the std::array
+     * Note that rotating offset is the second element of the std::array
+     *
+     * The offsets aim to align the pin indices for port of pb_type 
      * between operating and physical modes, especially when an operating 
      * mode contains multiple pb_type (num_pb>1) that are linked to 
      * the same physical pb_type. 
@@ -143,11 +151,21 @@ class PbTypeAnnotation {
      * the pin index of pb_type (whose index is large than 1) 
      * will be shifted by the given offset.
      *
-     * For example, an offset of 1 is used to map 
-     * operating pb_type adder[0].pin[0] with a full path clb.fle[arith].adder[0]
-     * to physical pb_type adder[0].pin[1] with a full path clb.fle[physical].adder[0]
+     * For example, an initial offset of -32 is used to map 
+     *   operating pb_type bram[0].dout[32] with a full path memory[dual_port].bram[0]
+     *   operating pb_type bram[0].dout[33] with a full path memory[dual_port].bram[0]
+     * to 
+     *   physical pb_type bram[0].dout_a[0] with a full path memory[physical].bram[0]
+     *   physical pb_type bram[0].dout_a[1] with a full path memory[physical].bram[0]
+     *
+     * For example, a rotating offset of 1 is used to map 
+     *   operating pb_type mult_9x9[0].a[0:8] with a full path mult[frac].mult_9x9[0]
+     *   operating pb_type mult_9x9[1].a[0:8] with a full path mult[frac].mult_9x9[1]
+     * to 
+     *   physical pb_type mult_36x36.a[0:8] with a full path mult[physical].mult_36x36[0]
+     *   physical pb_type mult_36x36.a[9:17] with a full path mult[physical].mult_36x36[0]
      */
-    std::map<std::string, std::map<BasicPort, int>> operating_pb_type_ports_;
+    std::map<std::string, std::map<BasicPort, std::array<int, 2>>> operating_pb_type_ports_;
 
     /* Link between the interconnects under this pb_type and circuit model names */
     std::map<std::string, std::string> interconnect_circuit_model_names_;
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
index a4d25e1cf..9831f6e23 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_pb_type_annotation.cpp
@@ -65,6 +65,31 @@ void read_xml_pb_port_annotation(pugi::xml_node& xml_port,
     pb_type_annotation.add_pb_type_port_pair(name_attr, port_parser.port());
   }
 
+  /* We have an optional attribute: physical_mode_pin_initial_offset
+   * Split based on the number of physical pb_type ports that have been defined
+   */
+  const std::string& physical_pin_initial_offset_attr = get_attribute(xml_port, "physical_mode_pin_initial_offset", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string();
+
+  if (false == physical_pin_initial_offset_attr.empty()) {
+    /* Split the physical mode port attributes with space */
+    openfpga::StringToken offset_tokenizer(physical_pin_initial_offset_attr);
+    const std::vector<std::string> initial_offsets = offset_tokenizer.split();
+   
+    /* Error out if the offset does not match the port definition */
+    if (physical_mode_ports.size() != initial_offsets.size()) {
+      archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port),
+                     "Defined %lu physical mode ports but only %lu physical pin initial offset are defined! Expect size matching.\n",
+                      physical_mode_ports.size(), initial_offsets.size());
+    }
+
+    for (size_t iport = 0; iport < physical_mode_ports.size(); ++iport) {
+      openfpga::PortParser port_parser(physical_mode_ports[iport]); 
+      pb_type_annotation.set_physical_pin_initial_offset(name_attr,
+                                                         port_parser.port(),
+                                                         std::stoi(initial_offsets[iport]));
+    }
+  }
+
   /* We have an optional attribute: physical_mode_pin_rotate_offset
    * Split based on the number of physical pb_type ports that have been defined
    */
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
index b013e5801..2bc512d85 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_pb_type_annotation.cpp
@@ -126,13 +126,21 @@ void write_xml_pb_port_annotation(std::fstream& fp,
   }
   write_xml_attribute(fp, "physical_mode_port", physical_mode_port_attr.c_str());
 
+  std::string physical_mode_pin_initial_offset_attr;
+  for (const auto& physical_pb_port_pair : pb_type_annotation.physical_pb_type_port(port_name)) {
+    if (false == physical_mode_pin_initial_offset_attr.empty()) {
+      physical_mode_pin_initial_offset_attr += " ";
+    }
+    physical_mode_pin_initial_offset_attr += std::to_string(physical_pb_port_pair.second[0]);
+  }
+  write_xml_attribute(fp, "physical_mode_pin_initial_offset", physical_mode_pin_initial_offset_attr.c_str()); 
 
   std::string physical_mode_pin_rotate_offset_attr;
   for (const auto& physical_pb_port_pair : pb_type_annotation.physical_pb_type_port(port_name)) {
     if (false == physical_mode_pin_rotate_offset_attr.empty()) {
       physical_mode_pin_rotate_offset_attr += " ";
     }
-    physical_mode_pin_rotate_offset_attr += std::to_string(physical_pb_port_pair.second);
+    physical_mode_pin_rotate_offset_attr += std::to_string(physical_pb_port_pair.second[1]);
   }
   write_xml_attribute(fp, "physical_mode_pin_rotate_offset", physical_mode_pin_rotate_offset_attr.c_str()); 
 
diff --git a/openfpga/src/annotation/annotate_pb_graph.cpp b/openfpga/src/annotation/annotate_pb_graph.cpp
index 249cb5632..67a1baba8 100644
--- a/openfpga/src/annotation/annotate_pb_graph.cpp
+++ b/openfpga/src/annotation/annotate_pb_graph.cpp
@@ -308,16 +308,23 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
   /* If the parent ports of the two pins are not paired, fail */
   for (t_port* candidate_port : vpr_device_annotation.physical_pb_port(operating_pb_graph_pin->port)) {
     if (physical_pb_graph_pin->port != candidate_port) {
-      return false;
+      /* Not the one we want, try the next candidate */
+      continue;
     }
     /* Check the pin number of physical pb_graph_pin matches the pin number of 
-     * operating pb_graph_pin plus a rotation offset 
-     *                                              operating port         physical port
-     *                      LSB  port_range.lsb()    pin_number              pin_number      MSB
-     *                                 |                  |                     |
-     *    Operating port     |         |                  +------               |
-     *                                 |                        |<----offset--->|
-     *    Physical port      |         +                        +               +
+     * operating pb_graph_pin plus a rotation offset with an initial offset, 
+     * which is to align the lsb between operating and physical ports
+     *
+     * For example: 
+     *   We can align the operating_port[32] to physical_port[0] with an initial offset
+     *   which is -32
+     *
+     *                                              operating port            physical port
+     *                      LSB  port_range.lsb()    pin_number                 pin_number      MSB
+     *                                 |                  |           init_offset   |
+     *    Operating port     |         |                  +------         +         |
+     *                                 |                        |<----acc_offset--->|
+     *    Physical port      |         +                        +                   +
      *
      * Note: 
      *   - accumulated offset is NOT the pin rotate offset specified by users
@@ -327,11 +334,14 @@ bool try_match_pb_graph_pin(t_pb_graph_pin* operating_pb_graph_pin,
      *     The accumulated offset will be reset to 0 when it exceeds the msb() of the physical port
      */
     int acc_offset = vpr_device_annotation.physical_pb_pin_offset(operating_pb_graph_pin->port, candidate_port);
+    int init_offset = vpr_device_annotation.physical_pb_pin_initial_offset(operating_pb_graph_pin->port, candidate_port);
     const BasicPort& physical_port_range = vpr_device_annotation.physical_pb_port_range(operating_pb_graph_pin->port, candidate_port);
     if (physical_pb_graph_pin->pin_number != operating_pb_graph_pin->pin_number
                                            + (int)physical_port_range.get_lsb() 
+                                           + init_offset
                                            + acc_offset) {
-      return false;
+      /* Not the one we want, try the next candidate */
+      continue;
     }
 
     /* Reach here, it means all the requirements have been met */
diff --git a/openfpga/src/annotation/annotate_pb_types.cpp b/openfpga/src/annotation/annotate_pb_types.cpp
index cb6c9e9b3..92a6f6560 100644
--- a/openfpga/src/annotation/annotate_pb_types.cpp
+++ b/openfpga/src/annotation/annotate_pb_types.cpp
@@ -211,7 +211,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
    * if not found, we assume that the physical port is the same as the operating pb_port
    */
   for (t_port* operating_pb_port : pb_type_ports(operating_pb_type)) {
-    std::map<BasicPort, int> expected_physical_pb_ports = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
+    std::map<BasicPort, std::array<int, 2>> expected_physical_pb_ports = pb_type_annotation.physical_pb_type_port(std::string(operating_pb_port->name));
   
     /* If not defined in the annotation, set the default pair:
      * rotate_offset is 0 by default!
@@ -220,7 +220,7 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
       BasicPort expected_physical_pb_port;
       expected_physical_pb_port.set_name(std::string(operating_pb_port->name));
       expected_physical_pb_port.set_width(operating_pb_port->num_pins);
-      expected_physical_pb_ports[expected_physical_pb_port] = 0;
+      expected_physical_pb_ports[expected_physical_pb_port] = {0, 0};
     }
 
     for (const auto& expected_physical_pb_port : expected_physical_pb_ports) {
@@ -241,7 +241,8 @@ bool pair_operating_and_physical_pb_types(t_pb_type* operating_pb_type,
        */
       vpr_device_annotation.add_physical_pb_port(operating_pb_port, physical_pb_port);
       vpr_device_annotation.add_physical_pb_port_range(operating_pb_port, physical_pb_port, expected_physical_pb_port.first);
-      vpr_device_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second);
+      vpr_device_annotation.add_physical_pb_pin_initial_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[0]);
+      vpr_device_annotation.add_physical_pb_pin_rotate_offset(operating_pb_port, physical_pb_port, expected_physical_pb_port.second[1]);
     }
   }
 
diff --git a/openfpga/src/annotation/vpr_device_annotation.cpp b/openfpga/src/annotation/vpr_device_annotation.cpp
index f196f50da..f07378634 100644
--- a/openfpga/src/annotation/vpr_device_annotation.cpp
+++ b/openfpga/src/annotation/vpr_device_annotation.cpp
@@ -190,6 +190,21 @@ int VprDeviceAnnotation::physical_pb_type_index_offset(t_pb_type* pb_type) const
   return physical_pb_type_index_offsets_.at(pb_type);
 }
 
+int VprDeviceAnnotation::physical_pb_pin_initial_offset(t_port* operating_pb_port,
+                                                        t_port* physical_pb_port) const {
+  /* Ensure that the pb_type is in the list */
+  std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_pin_initial_offsets_.find(operating_pb_port);
+  if (it == physical_pb_pin_initial_offsets_.end()) {
+    /* Default value is 0 */
+    return 0;
+  }
+  if (0 == physical_pb_pin_initial_offsets_.at(operating_pb_port).count(physical_pb_port)) {
+    /* Default value is 0 */
+    return 0;
+  }
+  return physical_pb_pin_initial_offsets_.at(operating_pb_port).at(physical_pb_port);
+}
+
 int VprDeviceAnnotation::physical_pb_pin_rotate_offset(t_port* operating_pb_port,
                                                        t_port* physical_pb_port) const {
   /* Ensure that the pb_type is in the list */
@@ -220,7 +235,6 @@ int VprDeviceAnnotation::physical_pb_pin_offset(t_port* operating_pb_port,
   return physical_pb_pin_offsets_.at(operating_pb_port).at(physical_pb_port);
 }
 
-
 t_pb_graph_pin* VprDeviceAnnotation::physical_pb_graph_pin(const t_pb_graph_pin* pb_graph_pin) const {
   /* Ensure that the pb_type is in the list */
   std::map<const t_pb_graph_pin*, t_pb_graph_pin*>::const_iterator it = physical_pb_graph_pins_.find(pb_graph_pin);
@@ -410,6 +424,20 @@ void VprDeviceAnnotation::add_physical_pb_type_index_offset(t_pb_type* pb_type,
   physical_pb_type_index_offsets_[pb_type] = offset;
 }
 
+void VprDeviceAnnotation::add_physical_pb_pin_initial_offset(t_port* operating_pb_port,
+                                                             t_port* physical_pb_port,
+                                                             const int& offset) {
+  /* Warn any override attempt */
+  std::map<t_port*, std::map<t_port*, int>>::const_iterator it = physical_pb_pin_initial_offsets_.find(operating_pb_port);
+  if ( (it != physical_pb_pin_initial_offsets_.end())
+    && (0 < physical_pb_pin_initial_offsets_[operating_pb_port].count(physical_pb_port)) ) {
+    VTR_LOG_WARN("Override the annotation between operating pb_port '%s' and it physical pb_port '%s' pin rotate offset '%d'!\n",
+                 operating_pb_port->name, offset);
+  }
+
+  physical_pb_pin_initial_offsets_[operating_pb_port][physical_pb_port] = offset;
+}
+
 void VprDeviceAnnotation::add_physical_pb_pin_rotate_offset(t_port* operating_pb_port,
                                                             t_port* physical_pb_port,
                                                             const int& offset) {
diff --git a/openfpga/src/annotation/vpr_device_annotation.h b/openfpga/src/annotation/vpr_device_annotation.h
index 6ac9ab4b5..0e290f18e 100644
--- a/openfpga/src/annotation/vpr_device_annotation.h
+++ b/openfpga/src/annotation/vpr_device_annotation.h
@@ -61,6 +61,9 @@ class VprDeviceAnnotation {
     float physical_pb_type_index_factor(t_pb_type* pb_type) const;
     int physical_pb_type_index_offset(t_pb_type* pb_type) const;
 
+    int physical_pb_pin_initial_offset(t_port* operating_pb_port,
+                                       t_port* physical_pb_port) const;
+
     int physical_pb_pin_rotate_offset(t_port* operating_pb_port,
                                       t_port* physical_pb_port) const;
 
@@ -96,6 +99,9 @@ class VprDeviceAnnotation {
                                     t_pb_graph_node* physical_pb_graph_node);
     void add_physical_pb_type_index_factor(t_pb_type* pb_type, const float& factor);
     void add_physical_pb_type_index_offset(t_pb_type* pb_type, const int& offset);
+    void add_physical_pb_pin_initial_offset(t_port* operating_pb_port,
+                                            t_port* physical_pb_port,
+                                            const int& offset);
     void add_physical_pb_pin_rotate_offset(t_port* operating_pb_port,
                                            t_port* physical_pb_port,
                                            const int& offset);
@@ -148,6 +154,7 @@ class VprDeviceAnnotation {
      * - the parent of physical pb_port MUST be a physical pb_type
      */
     std::map<t_port*, std::vector<t_port*>> physical_pb_ports_;
+    std::map<t_port*, std::map<t_port*, int>> physical_pb_pin_initial_offsets_;
     std::map<t_port*, std::map<t_port*, int>> physical_pb_pin_rotate_offsets_;
 
     /* Accumulated offsets for a physical pb_type port, just for internal usage */

From 161d66083719415b381f6bc25f6f8cd426090395 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 15:00:46 -0600
Subject: [PATCH 031/148] update documentation for the initial offset when
 mapping physical pins

---
 .../manual/arch_lang/annotate_vpr_arch.rst    | 39 ++++++++++++++++---
 .../libarchopenfpga/src/pb_type_annotation.h  |  2 +-
 2 files changed, 35 insertions(+), 6 deletions(-)

diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
index 5a6d77b14..e2f22ae37 100644
--- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
@@ -103,8 +103,9 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
 
 .. note:: OpenFPGA will infer the physical mode for a single-mode ``pb_type`` defined in VPR architecture
 
-.. option:: <pb_type name="<string>" physical_pb_type_name="<string>" circuit_model_name="<string>" 
-  mode_bits="<int>" physical_pb_type_index_factor="<float>" physical_pb_type_index_offset="<int>">
+.. option:: <pb_type name="<string>" physical_pb_type_name="<string>"
+             circuit_model_name="<string>" mode_bits="<int>"
+             physical_pb_type_index_factor="<float>" physical_pb_type_index_offset="<int>">
 
   Specify the physical implementation for a primitive ``pb_type`` in VPR architecture
 
@@ -128,7 +129,8 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
 
   - ``circuit_model_name="<string>"`` For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case.
 
-.. option:: <port name="<string>" physical_mode_port="<string>" physical_mode_pin_rotate_offset="<int>"/>
+.. option:: <port name="<string>" physical_mode_port="<string>"
+             physical_mode_pin_initial_offset="<int>" physical_mode_pin_rotate_offset="<int>"/>
 
    Link a port of an operating ``pb_type`` to a port of a physical ``pb_type``
 
@@ -136,9 +138,36 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
 
   - ``physical_mode_pin="<string>" creates the link of ``port`` of ``pb_type`` between operating and physical modes. This syntax is mandatory for every primitive ``pb_type`` in an operating mode ``pb_type``. It should be a valid ``port`` name of leaf ``pb_type`` in physical mode and the port size should also match. 
 
-    .. note:: Users can define multiple ports. For example: ``physical_mode_pin="a[0:1] b[2:2]"``. When multiple ports are used, the ``physical_mode_pin_rotate_offset`` should also be adapt. For example: ``physical_mode_pin_rotate_offset="1 0"``)
+    .. note:: Users can define multiple ports. For example: ``physical_mode_pin="a[0:1] b[2:2]"``. When multiple ports are used, the ``physical_mode_pin_initial_offset`` and ``physical_mode_pin_rotate_offset`` should also be adapt. For example: ``physical_mode_pin_rotate_offset="1 0"``)
 
-  - ``physical_mode_pin_rotate_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. 
+
+  - ``physical_mode_pin_initial_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when part of port of operating mode is mapped to a port in physical ``pb_type``. When ``physical_mode_pin_initial_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset. 
+
+    .. note:: A quick example to understand the initial offset
+              For example, an initial offset of -32 is used to map 
+
+              - operating pb_type ``bram[0].dout[32]`` with a full path ``memory[dual_port].bram[0]``
+              - operating pb_type ``bram[0].dout[33]`` with a full path ``memory[dual_port].bram[0]``
+
+              to 
+
+              - physical pb_type ``bram[0].dout_a[0]`` with a full path ``memory[physical].bram[0]``
+              - physical pb_type ``bram[0].dout_a[1]`` with a full path ``memory[physical].bram[0]``
+
+    .. note:: If not defined, the default value of ``physical_mode_pin_initial_offset`` is set to ``0``.
+
+  - ``physical_mode_pin_rotate_offset="<int>"`` aims to align the pin indices for ``port`` of ``pb_type`` between operating and physical modes, especially when an operating mode contains multiple ``pb_type`` (``num_pb``>1) that are linked to the same physical ``pb_type``. When ``physical_mode_pin_rotate_offset`` is larger than zero, the pin index of ``pb_type`` (whose index is large than 1) will be shifted by the given offset.
+  
+    .. note:: A quick example to understand the rotate offset
+              For example, a rotating offset of 9 is used to map 
+
+              - operating pb_type ``mult_9x9[0].a[0:8]`` with a full path ``mult[frac].mult_9x9[0]``
+              - operating pb_type ``mult_9x9[1].a[0:8]`` with a full path ``mult[frac].mult_9x9[1]``
+
+               to 
+
+              - physical pb_type ``mult_36x36.a[0:8]`` with a full path ``mult[physical].mult_36x36[0]``
+              - physical pb_type ``mult_36x36.a[9:17]`` with a full path ``mult[physical].mult_36x36[0]``
 
     .. note:: If not defined, the default value of ``physical_mode_pin_rotate_offset`` is set to ``0``.
 
diff --git a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
index 33941bce3..96383679d 100644
--- a/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
+++ b/libopenfpga/libarchopenfpga/src/pb_type_annotation.h
@@ -158,7 +158,7 @@ class PbTypeAnnotation {
      *   physical pb_type bram[0].dout_a[0] with a full path memory[physical].bram[0]
      *   physical pb_type bram[0].dout_a[1] with a full path memory[physical].bram[0]
      *
-     * For example, a rotating offset of 1 is used to map 
+     * For example, a rotating offset of 9 is used to map 
      *   operating pb_type mult_9x9[0].a[0:8] with a full path mult[frac].mult_9x9[0]
      *   operating pb_type mult_9x9[1].a[0:8] with a full path mult[frac].mult_9x9[1]
      * to 

From aa4a9b28cce77a3f4ec7825c9bcb831d0601ec9b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 15:03:46 -0600
Subject: [PATCH 032/148] start testing the initial offset in the flagship
 architecture

---
 ...c_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index b2fa706af..1eddefe25 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -309,9 +309,9 @@
     <!-- Bind the 512x64 single port RAM to the physical implementation -->
     <pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
       <port name="addr" physical_mode_port="addr1[0:8]"/>
-      <port name="data" physical_mode_port="data1 data2"/>
+      <port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="0 -32"/>
       <port name="we" physical_mode_port="we1"/>
-      <port name="out" physical_mode_port="out1 out2"/>
+      <port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="0 -32"/>
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 1024x32 single port RAM to the physical implementation -->

From 3273f441fe4bd36cf3e83c5f8a696ef3c6aebdfb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 15:23:20 -0600
Subject: [PATCH 033/148] bug fix in the flagship vpr arch

---
 ...rac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
index c56ce6041..2f14a7c2f 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_frac_mem32K_frac_dsp36_40nm.xml
@@ -321,7 +321,7 @@
     <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
              With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
              reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <segment freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
       <mux name="0"/>
       <sb type="pattern">1 1 1 1 1</sb>
       <cb type="pattern">1 1 1 1</cb>

From 18735894f9ef167c2f30e7c927cdd29a83e08a22 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 15:27:30 -0600
Subject: [PATCH 034/148] bug fix in openfpga arch: data1 and out1 should have
 the same offset as the data2 and out2

---
 ...c_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index 1eddefe25..ef872ccbf 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -309,9 +309,9 @@
     <!-- Bind the 512x64 single port RAM to the physical implementation -->
     <pb_type name="memory[mem_512x64_sp].mem_512x64_sp" physical_pb_type_name="memory[physical].frac_mem_32k" mode_bits="0000">
       <port name="addr" physical_mode_port="addr1[0:8]"/>
-      <port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="0 -32"/>
+      <port name="data" physical_mode_port="data1 data2" physical_mode_pin_initial_offset="-32 -32"/>
       <port name="we" physical_mode_port="we1"/>
-      <port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="0 -32"/>
+      <port name="out" physical_mode_port="out1 out2" physical_mode_pin_initial_offset="-32 -32"/>
       <port name="clk" physical_mode_port="clk"/>
     </pb_type>
     <!-- Bind the 1024x32 single port RAM to the physical implementation -->

From f0bc6f83f1b0943fef95c81166196762c01974e6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 15:34:59 -0600
Subject: [PATCH 035/148] disable buffer absorbing in the template script for
 bitstream generation. This is applicable to a wide range of benchmarks

---
 .../generate_bitstream_example_script.openfpga                  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga
index ab79ce90a..d1b8b4ada 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_bitstream_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --absorb_buffer_luts off
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}

From f3ca1c0973237fe845476704c76879e47ece4ec8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 17:28:25 -0600
Subject: [PATCH 036/148] fix rr_graph on thru routing channel support

---
 vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
index 4107d4538..3e9004175 100644
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_node_builder.cpp
@@ -840,7 +840,7 @@ void load_chanx_rr_nodes_basic_info(RRGraph& rr_graph,
          *  track0 ----->+-----------------------------+----> track0
          *               |                             |
          */
-        if (true == is_chanx_exist(grids, chanx_coord)) {
+        if (true == is_chanx_exist(grids, chanx_coord, through_channel)) {
           /* Rotate the chanx_details by an offset of ix - 1, the distance to the most left channel */
           /* For INC_DIRECTION, we use clockwise rotation 
            * node_id A ---->   -----> node_id D
@@ -951,7 +951,7 @@ void load_chany_rr_nodes_basic_info(RRGraph& rr_graph,
          *               |                             |
          * we should rotate only once at the bottom side of a grid 
          */
-        if (true == is_chany_exist(grids, chany_coord)) {
+        if (true == is_chany_exist(grids, chany_coord, through_channel)) {
           /* Rotate the chany_details by an offset of 1*/
           /* For INC_DIRECTION, we use clockwise rotation 
            * node_id A ---->   -----> node_id D

From bf08e1841caed464f7efc8ea5bdd95adf59562cd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 17:58:34 -0600
Subject: [PATCH 037/148] add new test case using thru channels

---
 .../thru_channel/config/task.conf             | 36 +++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 openfpga_flow/tasks/fpga_verilog/thru_channel/config/task.conf

diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/config/task.conf
new file mode 100644
index 000000000..1e2941de1
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/config/task.conf
@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From d6d17675e26cf62bd9ef17aced1ab55f77fb9fa0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 18:01:32 -0600
Subject: [PATCH 038/148] update docoumentation about the constraints when
 using tileable rr_graph generator

---
 docs/source/manual/arch_lang/addon_vpr_syntax.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
index 18f61703a..4af72aa7c 100644
--- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
@@ -54,6 +54,8 @@ Layout
   
   .. warning:: Currently ``through_channel`` supports only a fixed routing channel width!
 
+  .. warning:: You must define custom pin location for the ``height > 1`` or ``width >1`` tiles when using the tileable routing resource graph!!! Otherwise, it will cause undriven pins in your device!!!
+
 
 A quick example to show tileable routing is enabled and through channels are disabled:
 

From 47f15729adda78734f5222071f044ae2b145bd6b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 18:37:28 -0600
Subject: [PATCH 039/148] update doc about the limitation on using tileable
 routing

---
 docs/source/manual/arch_lang/addon_vpr_syntax.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
index 4af72aa7c..dc7e868b6 100644
--- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
@@ -54,7 +54,7 @@ Layout
   
   .. warning:: Currently ``through_channel`` supports only a fixed routing channel width!
 
-  .. warning:: You must define custom pin location for the ``height > 1`` or ``width >1`` tiles when using the tileable routing resource graph!!! Otherwise, it will cause undriven pins in your device!!!
+  .. warning:: You cannot use ``spread`` pin location for the ``height > 1`` or ``width >1`` tiles when using the tileable routing resource graph!!! Otherwise, it will cause undriven pins in your device!!!
 
 
 A quick example to show tileable routing is enabled and through channels are disabled:

From 881672d46a7ef58abf908fb9213340ca657162d7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 19:52:35 -0600
Subject: [PATCH 040/148] update thru channel arch for avoid buggy pin
 locations

---
 ...N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
index 7e4cf8e7a..ffefc9146 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
@@ -188,7 +188,14 @@
       <output name="d_out" num_pins="32"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
+      <pinlocations pattern="perimeter"/>
+      <!--pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top">memory.clk</loc>
+        <loc side="right" yoffset="0">memory.waddr[0:4] memory.d_in[0:15] memory.wen</loc>
+        <loc side="right" yoffset="1">memory.raddr[0:4] memory.d_out[0:15]</loc>
+        <loc side="bottom">memory.waddr[5:9] memory.raddr[5:9] memory.d_in[16:31] memory.ren memory.d_out[16:31]</loc>
+      </pinlocations-->
     </tile>
   </tiles>
   <!-- ODIN II specific config ends -->

From 8041c90f127aceb35499fadc37aff1c4efee7a40 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 20:01:50 -0600
Subject: [PATCH 041/148] bug fix in through channel support in tileable
 routing

---
 vpr/src/route/route_common.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
index 8fd661d05..6ced2779f 100644
--- a/vpr/src/route/route_common.cpp
+++ b/vpr/src/route/route_common.cpp
@@ -292,7 +292,7 @@ bool try_route(int width_fac,
                     segment_inf,
                     router_opts.base_cost_type,
                     router_opts.trim_empty_channels,
-                    router_opts.trim_obs_channels,
+                    router_opts.trim_obs_channels || det_routing_arch->through_channel,
                     router_opts.clock_modeling,
                     directs, num_directs,
                     &warning_count);

From 1a3e0201749c2078cc8dacde28be0d1b1c9f02dc Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 20:04:01 -0600
Subject: [PATCH 042/148] deploy through channel test case to CI

---
 .travis/fpga_verilog_reg_test.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index 7ee1a5095..8424475fb 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -81,6 +81,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/p
 echo -e "Testing Depopulated crossbar in local routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
 
+echo -e "Testing through channels in tileable routing";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel --debug --show_thread_logs
+
 # Verify MCNC big20 benchmark suite with ModelSim 
 # Please make sure you have ModelSim installed in the environment
 # Otherwise, it will fail

From 6c925dcded560ac9b7525341830c26f12ad3661b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 20:11:37 -0600
Subject: [PATCH 043/148] [regression test] Add more tests for thru channels
 and deploy to CI

---
 .travis/fpga_verilog_reg_test.sh              |   3 +-
 .../{ => thru_narrow_tile}/config/task.conf   |   0
 .../thru_wide_tile/config/task.conf           |  36 +
 ..._tileable_adder_chain_wide_mem16K_40nm.xml |   2 +-
 ...u_channel_adder_chain_wide_mem16K_40nm.xml | 734 ++++++++++++++++++
 5 files changed, 773 insertions(+), 2 deletions(-)
 rename openfpga_flow/tasks/fpga_verilog/thru_channel/{ => thru_narrow_tile}/config/task.conf (100%)
 create mode 100644 openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf
 create mode 100644 openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index 8424475fb..fde145744 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -82,7 +82,8 @@ echo -e "Testing Depopulated crossbar in local routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
 
 echo -e "Testing through channels in tileable routing";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
 
 # Verify MCNC big20 benchmark suite with ModelSim 
 # Please make sure you have ModelSim installed in the environment
diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fpga_verilog/thru_channel/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf
diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf
new file mode 100644
index 000000000..5f6de1078
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf
@@ -0,0 +1,36 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
index f07f16c80..46b23c83e 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
@@ -188,7 +188,7 @@
       <output name="d_out" num_pins="32"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
+      <pinlocations pattern="perimeter"/>
     </tile>
   </tiles>
   <!-- ODIN II specific config ends -->
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
new file mode 100644
index 000000000..bc5c762b3
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
@@ -0,0 +1,734 @@
+<!-- 
+  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
+    with optionally registered outputs
+    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
+    Carry chain links to vertically adjacent logic blocks
+  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
+    Height = 6, found on every (8n+2)th column
+  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
+    Height = 4, found on every (8n+6)th column
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  The electrical design of the architecture described here is NOT from an 
+  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
+  architecture file by using an existing commercial FPGA to approximate the area, 
+  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
+  model of wiring and circuit design for low-level routing components, where available.
+  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
+  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
+  modified and you will still get reasonable delay results for the new architecture.
+  The following describes, in detail, how we obtained the various electrical values for this 
+  architecture.
+
+  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
+  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
+  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
+  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
+  match the overall target (a 40 nm FPGA).
+
+  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
+  memories, and multipliers from test circuits on a Stratix IV GX device 
+  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
+  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
+  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
+  take the R and C data from the ITRS roadmap.  
+
+  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
+  crossbar is close enough to the crossbar modelled here.  
+  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
+  36:1 multiplexers.  We match these parameters in this architecture.
+
+  For LUTs, we include LUT 
+  delays measured from Stratix IV which is dependant on the input used (ie. some 
+  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
+  not consider differences in LUT input delays.
+
+  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
+  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
+  all pins except clock virtual) then measuring the delays in chip-planner, 
+  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
+  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
+  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
+  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
+  overhead that we don't have, I'll approximate the delay of a simpler chain at 
+  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
+  can be justified).
+
+  Logic block area numbers obtained by scaling overall tile area of a 65nm 
+  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
+  routing area at a channel width of 300. We use a channel width of 300 because it can route 
+  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
+  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
+  choosing a width that provides high routability. The architecture can be routed at different channel
+  widths, but we estimate the tile size and hence the physical length of routing wires assuming
+  a channel width of 300.
+
+  Sanity checks employed:
+    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
+        common electrical design.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut6">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut4_out"/>
+        <port name="lut5_out"/>
+        <port name="lut6_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
+        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" width="2" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="perimeter"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true" through_channel="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	    -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+           book area formula. This means the mux transistors are about 5x minimum drive strength.
+           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+           2.5x when looking up in Jeff's tables.
+           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="40" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="20" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="10">
+        <input name="in" num_pins="6"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="6"/>
+              <output name="lut4_out" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
+                <input name="in" num_pins="6"/>
+                <output name="lut4_out" num_pins="4"/>
+                <output name="lut5_out" num_pins="2"/>
+                <output name="lut6_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
+                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
+                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>         
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
+              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
+              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
+              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
+              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
+              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- BEGIN fle mode of dual lut5 -->
+        <mode name="n2_lut5">
+          <pb_type name="ble5" num_pb="2">
+            <input name="in" num_pins="5"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Regular LUT mode -->
+            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="5" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                  we instead take the average of these numbers to get more stable results
+                82e-12
+                173e-12
+                261e-12
+                263e-12
+                398e-12
+                -->
+              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+                235e-12
+              </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble5.in" output="lut5.in"/>
+              <direct name="direct2" input="lut5.out" output="ff.D">
+                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
+                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
+            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
+            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
+            <direct name="direct4" input="ble5.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- END fle mode of dual lut5 -->
+        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="2">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
+              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
+                </direct>
+              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
+                </direct>
+              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
+                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
+            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
+              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- n2_lut5 -->
+        <mode name="n1_lut6">
+          <pb_type name="ble6" num_pb="1">
+            <input name="in" num_pins="6"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="6" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                  261e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
+              <direct name="direct2" input="lut6.out" output="ff.D">
+                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
+                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
+            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
+          </interconnect>
+        </mode>
+        <!-- n1_lut6 -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
+           The delays below come from Stratix IV. the delay through a connection block
+           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+           delay within the crossbar is 95 ps. 
+           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+           to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
+        </complete>
+
+        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+                 naive specification).
+          -->
+        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
+        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
+          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="10"/>
+      <input name="raddr" num_pins="10"/>
+      <input name="d_in" num_pins="32"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="32"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 512x32=16Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 16K dual-port RAM
+        -->
+      <mode name="mem_512x32_dp">
+        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="10" port_class="address"/>
+          <input name="raddr" num_pins="10" port_class="address"/>
+          <input name="d_in" num_pins="32" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="32" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From fb5a5a244871c52e6608be163757a6ba942ee0b7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 19 Aug 2020 20:12:49 -0600
Subject: [PATCH 044/148] [documentation] remove the limitation on through
 channels

---
 docs/source/manual/arch_lang/addon_vpr_syntax.rst | 2 --
 1 file changed, 2 deletions(-)

diff --git a/docs/source/manual/arch_lang/addon_vpr_syntax.rst b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
index dc7e868b6..773ac0992 100644
--- a/docs/source/manual/arch_lang/addon_vpr_syntax.rst
+++ b/docs/source/manual/arch_lang/addon_vpr_syntax.rst
@@ -52,8 +52,6 @@ Layout
 
   .. warning:: Do NOT enable ``through_channel`` if you are not using the tileable routing resource graph generator!
   
-  .. warning:: Currently ``through_channel`` supports only a fixed routing channel width!
-
   .. warning:: You cannot use ``spread`` pin location for the ``height > 1`` or ``width >1`` tiles when using the tileable routing resource graph!!! Otherwise, it will cause undriven pins in your device!!!
 
 

From b83319bf14d6e4578af7564d833c1727bf057632 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Aug 2020 13:48:22 -0600
Subject: [PATCH 045/148] [Check codes] add check codes for default circuit
 models. Error out when there is no default model in a defined group

---
 .../src/check_circuit_library.cpp             | 46 +++++++++++++++++--
 1 file changed, 43 insertions(+), 3 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
index ea6db0678..e438ba5f8 100644
--- a/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/check_circuit_library.cpp
@@ -197,6 +197,43 @@ size_t check_circuit_model_port_required(const CircuitLibrary& circuit_lib,
   return num_err;
 }
 
+/************************************************************************
+ *  A generic function to search each default circuit model by types 
+ *  that have been defined by users.
+ *  If a type of circuit model is defined, we expect there is a default model 
+ *  to be specified
+ ***********************************************************************/
+static 
+size_t check_default_circuit_model_by_types(const CircuitLibrary& circuit_lib) {
+  size_t num_err = 0;
+
+  for (size_t itype = 0; itype < NUM_CIRCUIT_MODEL_TYPES; ++itype) {
+    std::vector<CircuitModelId> curr_models = circuit_lib.models_by_type(e_circuit_model_type(itype));
+    if (0 == curr_models.size()) {
+       continue;
+    }
+    /* Go through the models and try to find a default one */
+    size_t found_default_counter = 0;
+    for (const auto& curr_model : curr_models) {
+      if (true == circuit_lib.model_is_default(curr_model)) {
+        found_default_counter++;
+      }
+    }
+    if (0 == found_default_counter) {
+      VTR_LOG_ERROR("Miss a default circuit model for the type %s! Try to define it in your architecture file!\n",
+                    CIRCUIT_MODEL_TYPE_STRING[itype]);
+      num_err++;
+    }
+    if (1 < found_default_counter) {
+      VTR_LOG_ERROR("Found >1 default circuit models for the type %s! Expect only one!\n",
+                    CIRCUIT_MODEL_TYPE_STRING[itype]);
+      num_err++;
+    }
+  }
+
+  return num_err;
+}
+
 /************************************************************************
  *  A generic function to find the default circuit model with a given type
  *  If not found, we give an error
@@ -207,9 +244,9 @@ size_t check_required_default_circuit_model(const CircuitLibrary& circuit_lib,
   size_t num_err = 0;
 
   if (CircuitModelId::INVALID() == circuit_lib.default_model(circuit_model_type)) {
-    VTR_LOG_ERROR("A default circuit model for the type %s! Try to define it in your architecture file!\n",
+    VTR_LOG_ERROR("Miss a default circuit model for the type %s! Try to define it in your architecture file!\n",
                   CIRCUIT_MODEL_TYPE_STRING[size_t(circuit_model_type)]);
-    exit(1);
+    num_err++;
   }
 
   return num_err;
@@ -626,7 +663,10 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
 
   num_err += check_circuit_model_port_required(circuit_lib, CIRCUIT_MODEL_LUT, lut_port_types_required);
 
-  /* 10. We must have default circuit models for these types: MUX, channel wires and wires */
+  /* 10. For each type of circuit models that are define, we must have 1 default model
+   *     We must have default circuit models for these types: MUX, channel wires and wires 
+   */
+  num_err += check_default_circuit_model_by_types(circuit_lib);
   num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_MUX);
   num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_CHAN_WIRE);
   num_err += check_required_default_circuit_model(circuit_lib, CIRCUIT_MODEL_WIRE);

From 9c66a35bf6861a993eb2f35581c7fc6fe19840cd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Aug 2020 14:06:03 -0600
Subject: [PATCH 046/148] [arch language] Now circuit library will
 automatically identify the default circuit model if needed

---
 .../libarchopenfpga/src/circuit_library.cpp    | 18 ++++++++++++++++++
 .../libarchopenfpga/src/circuit_library.h      |  4 ++++
 .../src/read_xml_openfpga_arch.cpp             |  3 +++
 3 files changed, 25 insertions(+)

diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
index cccc62e71..881035ee7 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
@@ -2,6 +2,7 @@
 #include <algorithm>
 
 #include "vtr_assert.h"
+#include "vtr_log.h"
 
 #include "openfpga_port_parser.h"
 #include "circuit_library.h"
@@ -2108,6 +2109,23 @@ void CircuitLibrary::build_timing_graphs() {
   return;
 }
 
+/* Automatically identify the default models for each type*/
+void CircuitLibrary::auto_detect_default_models() {
+  /* Go through the model fast look-up */
+  for (const auto& curr_type_models : model_lookup_) {
+    if ( (1 == curr_type_models.size())
+      && (false == model_is_default(curr_type_models[0]))) {
+      /* This is the only model in this type,
+       * it is safe to set it to be default
+       * Give a warning for users
+       */
+      set_model_is_default(curr_type_models[0], true);
+      VTR_LOG_WARN("Automatically set circuit model '%s' to be default in its type.\n",
+                   model_name(curr_type_models[0]).c_str());
+    }
+  }
+}
+
 /************************************************************************
  * Internal mutators: build timing graphs 
  ***********************************************************************/
diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h
index abb03d1f8..5e023c665 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.h
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.h
@@ -461,6 +461,10 @@ class CircuitLibrary {
   public: /* Public Mutators: builders */
     void build_model_links();
     void build_timing_graphs();
+    /* Automatically identify the default models for each type,
+     * suggest to do this after circuit library is built
+     */
+    void auto_detect_default_models();
   public: /* Internal mutators: build timing graphs */
     void add_edge(const CircuitModelId& model_id,
                   const CircuitPortId& from_port, const size_t& from_pin, 
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
index 6bc31ef46..e8ce6aeab 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_openfpga_arch.cpp
@@ -52,6 +52,9 @@ openfpga::Arch read_xml_openfpga_arch(const char* arch_file_name) {
     auto xml_circuit_models = get_single_child(xml_openfpga_arch, "circuit_library", loc_data);
     openfpga_arch.circuit_lib = read_xml_circuit_library(xml_circuit_models, loc_data);
 
+    /* Automatically identify the default models for circuit library */
+    openfpga_arch.circuit_lib.auto_detect_default_models();
+
     /* Build the internal links for the circuit library */
     openfpga_arch.circuit_lib.build_model_links();
   

From ac8e937a504747dd028e5288f8009ab858c150c4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Aug 2020 14:08:38 -0600
Subject: [PATCH 047/148] [Documentation] Update for default circuit model
 rules

---
 docs/source/manual/arch_lang/circuit_library.rst | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst
index 9fe29a0fa..59e5f055f 100644
--- a/docs/source/manual/arch_lang/circuit_library.rst
+++ b/docs/source/manual/arch_lang/circuit_library.rst
@@ -78,9 +78,9 @@ Here, we focus these common syntax and we will detail special syntax in :ref:`ci
 
 .. warning:: ``prefix`` may be deprecated soon
 
-.. note:: Multiplexers cannot be user-defined.
+.. warning:: Multiplexers cannot be user-defined.
 
-.. note:: For a circuit model type, only one circuit model can be set as default.
+.. warning:: For a circuit model type, only one circuit model is allowed to be set as default. If there is only one circuit model defined in a type, it will be considered as the default automatically.
 
 .. note:: If ``<spice_netlist>`` or ``<verilog_netlist>`` are not specified, FPGA-Verilog/SPICE auto-generates the Verilog/SPICE netlists for multiplexers, wires, and LUTs.
 

From 9101ba102143ef98de7a1f137a54956775c7a6d9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Aug 2020 14:55:44 -0600
Subject: [PATCH 048/148] [Architecture Language] Update openfpga architecture
 files for default models

---
 .../openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml   | 2 +-
 ...c_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml | 2 +-
 .../k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml          | 2 +-
 .../k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml      | 4 ++--
 .../k6_frac_N10_adder_column_chain_40nm_openfpga.xml          | 2 +-
 .../k6_frac_N10_adder_register_chain_40nm_openfpga.xml        | 2 +-
 .../k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml   | 2 +-
 ...ac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml | 2 +-
 ...adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml | 2 +-
 9 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
index bbc33f2e8..6d5df7467 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
index ef872ccbf..6ddb0d681 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
index c4d47ad2c..b8c99a382 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
index 5925aeb2d..c0c1aa581 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
@@ -175,7 +175,7 @@
        <port type="output" prefix="Qb" size="1"/>
        <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="iopad" prefix="iopad" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
@@ -184,7 +184,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
index f2265e48c..26af034f5 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
index 3597e7c50..e10c12d27 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
@@ -184,7 +184,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
index b17169f78..8537cfc18 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
@@ -189,7 +189,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
index f26140913..b815842e7 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml
@@ -189,7 +189,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
index 7f31c435f..943d3c040 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
@@ -204,7 +204,7 @@
       <port type="input" prefix="outpad" size="1"/>
       <port type="output" prefix="inpad" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>

From 4b3142c4ee6fa4f8a71628e250aebf2236912cb9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 23 Aug 2020 15:13:28 -0600
Subject: [PATCH 049/148] [Architecture File] Patch openfpga architecture with
 default circuit model definition

---
 ...0_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
index 943d3c040..c74625e33 100644
--- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
@@ -154,7 +154,7 @@
        <port type="output" prefix="Q" size="1"/>
        <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" is_default="true" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>

From b5251ce5af7616d87a8436c351a652ce314680bb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 1 Sep 2020 11:07:50 -0600
Subject: [PATCH 050/148] [documentation] update motivation figure and layout
 licenses

---
 docs/source/figures/openfpga_motivation.png | Bin 279950 -> 279839 bytes
 docs/source/motivation.rst                  |   2 +-
 2 files changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/source/figures/openfpga_motivation.png b/docs/source/figures/openfpga_motivation.png
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A2LJ#7

diff --git a/docs/source/motivation.rst b/docs/source/motivation.rst
index 01ae7da54..b70b92ace 100644
--- a/docs/source/motivation.rst
+++ b/docs/source/motivation.rst
@@ -9,7 +9,7 @@ OpenFPGA aims to be an open-source framework that enables rapid prototyping of c
    :scale: 50%
    :alt: OpenFPGA: a fast prototyping framework for customizable FPGAs
 
-   Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches
+   Comparison on engineering time and effort to prototype an FPGA using OpenFPGA and conventional approaches [All the layout figures are permitted to publish under proper licenses]
 
 Using OpenFPGA, the development cycle in both hardware and software can be significantly accelerated. OpenFPGA can automatically generate Verilog netlists describing a full FPGA fabric based on an XML-based description file. Thanks to modern semi-custom design tools, production-ready layout generation can be achieved within 24 hours. To help sign-off, OpenFPGA can auto-generate Verilog testbenches to validate the correctness of FPGA fabric using modern verification tools.
 OpenFPGA also provides native bitstream generation support based the same XML-based description file used in Verilog generation. This avoid the recurring engineering in developing CAD tools for different FPGAs. Once the FPGA architecture is finalized, the CAD tool is ready to use.

From 04070fd4ca24aa3cdf9366dff3a054ec9093493c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 2 Sep 2020 22:16:10 -0600
Subject: [PATCH 051/148] [Debug aid] add pb_type full hierarchy path in the
 error message of architecture binding checker

---
 .../annotation/check_pb_type_annotation.cpp   |  9 +++--
 openfpga/src/utils/pb_type_utils.cpp          | 38 +++++++++++++++++++
 openfpga/src/utils/pb_type_utils.h            |  2 +
 3 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/openfpga/src/annotation/check_pb_type_annotation.cpp b/openfpga/src/annotation/check_pb_type_annotation.cpp
index d0709c81c..1ed6fea8b 100644
--- a/openfpga/src/annotation/check_pb_type_annotation.cpp
+++ b/openfpga/src/annotation/check_pb_type_annotation.cpp
@@ -194,7 +194,7 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
     /* Every physical pb_type should be linked to a valid circuit model */
     if (CircuitModelId::INVALID() == vpr_device_annotation.pb_type_circuit_model(cur_pb_type)) {
       VTR_LOG_ERROR("Found a physical pb_type '%s' missing circuit model binding!\n",
-                    cur_pb_type->name);
+                    generate_pb_type_hierarchy_path(cur_pb_type).c_str());
       num_err++;
       return; /* Invalid id already, further check is not applicable */
     }
@@ -202,7 +202,8 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
     for (t_port* port : pb_type_ports(cur_pb_type)) {
       if (CircuitPortId::INVALID() == vpr_device_annotation.pb_circuit_port(port)) {
         VTR_LOG_ERROR("Found a port '%s' of physical pb_type '%s' missing circuit port binding!\n",
-                      port->name, cur_pb_type->name);
+                      port->name,
+                      generate_pb_type_hierarchy_path(cur_pb_type).c_str());
         num_err++;
       }
     }
@@ -217,7 +218,7 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
       VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' missing circuit model binding!\n",
                     interc->name,
                     physical_mode->name,
-                    cur_pb_type->name);
+                    generate_pb_type_hierarchy_path(cur_pb_type).c_str());
       num_err++;
       continue;
     }
@@ -226,7 +227,7 @@ void rec_check_vpr_pb_type_circuit_model_annotation(t_pb_type* cur_pb_type,
       VTR_LOG_ERROR("Found an interconnect '%s' under physical mode '%s' of pb_type '%s' linked to a circuit model '%s' with a wrong type!\nExpect: '%s' Linked: '%s'\n",
                     interc->name,
                     physical_mode->name, 
-                    cur_pb_type->name,
+                    generate_pb_type_hierarchy_path(cur_pb_type).c_str(),
                     circuit_lib.model_name(interc_circuit_model).c_str(),
                     CIRCUIT_MODEL_TYPE_STRING[circuit_lib.model_type(interc_circuit_model)],
                     CIRCUIT_MODEL_TYPE_STRING[required_circuit_model_type]);
diff --git a/openfpga/src/utils/pb_type_utils.cpp b/openfpga/src/utils/pb_type_utils.cpp
index 9166a16e8..c9fed784c 100644
--- a/openfpga/src/utils/pb_type_utils.cpp
+++ b/openfpga/src/utils/pb_type_utils.cpp
@@ -324,4 +324,42 @@ std::vector<t_port*> find_pb_type_ports_match_circuit_model_port_type(t_pb_type*
   return ports;
 }
 
+/*********************************************************************
+ * Generate the full hierarchy for a pb_type
+ * The final name will be in the following format:
+ * <top_pb_type_name>[<mode_name>].<parent_pb_type_name> ... <current_pb_type_name>
+ *
+ * TODO: This function should be part of the VPR libarchfpga parser
+ **********************************************************************/
+std::string generate_pb_type_hierarchy_path(t_pb_type* cur_pb_type) {
+  std::string hie_name(cur_pb_type->name);
+
+  t_pb_type* parent_pb_type = cur_pb_type;
+
+  /* Backward trace until we meet the top-level pb_type */
+  while (1) {
+    /* If there is no parent mode, this is a top-level pb_type, quit the loop here */
+    t_mode* parent_mode = parent_pb_type->parent_mode;
+    if (NULL == parent_mode) {
+      break;
+    }
+    
+    /* Add the mode name to the full hierarchy */
+    hie_name = std::string("[") + std::string(parent_mode->name) + std::string("].") + hie_name;
+
+    /* Backtrace to the upper level */
+    parent_pb_type = parent_mode->parent_pb_type;
+
+    /* If there is no parent pb_type, this is a top-level pb_type, quit the loop here */
+    if (NULL == parent_pb_type) {
+      break;
+    }
+
+    /* Add the current pb_type name to the hierarchy name */
+    hie_name = std::string(parent_pb_type->name) + hie_name;
+  }
+
+  return hie_name;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/utils/pb_type_utils.h b/openfpga/src/utils/pb_type_utils.h
index 5d23f23bc..83ba9000b 100644
--- a/openfpga/src/utils/pb_type_utils.h
+++ b/openfpga/src/utils/pb_type_utils.h
@@ -57,6 +57,8 @@ std::vector<t_port*> find_pb_type_ports_match_circuit_model_port_type(t_pb_type*
                                                                       const e_circuit_model_port_type& port_type,
                                                                       const VprDeviceAnnotation& vpr_device_annotation);
 
+std::string generate_pb_type_hierarchy_path(t_pb_type* cur_pb_type);
+
 } /* end namespace openfpga */
 
 #endif

From 7a2502ddf9ee99b3710aa1a075a3f08ef52218fb Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 2 Sep 2020 22:47:14 -0600
Subject: [PATCH 052/148] [documentation] add more guidelines about the
 vpr-openfpga architecture annotation

---
 docs/source/manual/arch_lang/annotate_vpr_arch.rst | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
index e2f22ae37..d990e3092 100644
--- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst
+++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst
@@ -111,6 +111,8 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
 
   .. note:: This should be applied to primitive ``pb_type``, i.e., ``pb_type`` have no children.
 
+  .. note:: This definition should be placed directly under the XML node ``<pb_type_annotation>`` without any intermediate XML nodes!
+
   - ``name="<string>"`` specifiy the full name of a ``pb_type`` in the hierarchy of VPR architecture.
 
   - ``physical_pb_type_name=<string>`` creates the link on ``pb_type`` between operating and physical modes. This syntax is mandatory for every primitive ``pb_type`` in an operating mode ``pb_type``. It should be a valid name of primitive ``pb_type`` in physical mode.   
@@ -125,10 +127,12 @@ The ``circuit_model_name`` should match the given name of a ``circuit_model`` de
 
 .. option:: <interconnect name="<string>" circuit_model_name="<string>">
 
-  - ``name="<string>"`` specifiy the name of a ``interconnect`` in VPR architecture. Different from ``pb_type``, hierarchical name is not required here.
+  - ``name="<string>"`` specify the name of a ``interconnect`` in VPR architecture. Different from ``pb_type``, hierarchical name is not required here.
 
   - ``circuit_model_name="<string>"`` For the interconnection type direct, the type of the linked circuit model should be wire. For multiplexers, the type of linked circuit model should be ``mux``. For complete, the type of the linked circuit model can be either ``mux`` or ``wire``, depending on the case.
 
+  .. note:: A ``<pb_type name="<string>">`` parent XML node is required for the interconnect-to-circuit bindings whose interconnects are defined under the ``pb_type`` in VPR architecture description. 
+
 .. option:: <port name="<string>" physical_mode_port="<string>"
              physical_mode_pin_initial_offset="<int>" physical_mode_pin_rotate_offset="<int>"/>
 

From 9bf0e772a355beb8d148c6637ae0ee0feac8609b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 15:45:35 -0600
Subject: [PATCH 053/148] [Regression Tests]Add a new testcase for routing
 multiplexer designs without buffers

---
 .../mux_design/debuf_mux/config/task.conf     | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf

diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf
new file mode 100644
index 000000000..c076c6071
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/mux_design/debuf_mux/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From eecfd186f0f2d7b80b67c8322291b029b2333c0f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 15:46:10 -0600
Subject: [PATCH 054/148] [OpenFPGA Architecture] Add the openfpga architecture
 for multiplexers without buffers

---
 .../k6_frac_N8_debuf_mux_40nm_openfpga.xml    | 231 ++++++++++++++++++
 1 file changed, 231 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml
new file mode 100644
index 000000000..b0c8c6ba0
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml
@@ -0,0 +1,231 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N8_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 8, I = 32
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

From a03f2fe974512ab465f7e06703ef8d88f6085ac0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 15:48:08 -0600
Subject: [PATCH 055/148] [Regression Test] Deploy the debuf mux test case to
 CI

---
 .travis/fpga_verilog_reg_test.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index fde145744..f4f0d82d0 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -55,6 +55,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/stdcell_m
 echo -e "Testing Verilog generation with routing multiplexers implemented by local encoders";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_encoder --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with routing multiplexers without buffers";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with behavioral description";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
 

From aa9521b23b667be3517926e7f8fcfb6ee2a4ee45 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 15:57:44 -0600
Subject: [PATCH 056/148] [OpenFPGA architecture] Add the architecture where
 routing multiplexers have only input buffers

---
 ...6_frac_N8_inbuf_only_mux_40nm_openfpga.xml | 231 ++++++++++++++++++
 1 file changed, 231 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml
new file mode 100644
index 000000000..1cb12f465
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml
@@ -0,0 +1,231 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N8_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 8, I = 32
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="buf4"/>
+      <output_buffer exist="false"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="buf4"/>
+      <output_buffer exist="false"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="buf4"/>
+      <output_buffer exist="false"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

From aaf63050bbedd5192ddcc5af5b290a52d323cfcf Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 15:58:34 -0600
Subject: [PATCH 057/148] [OpenFPGA architecture] Add the architecture where
 routing multiplexers have only output buffers

---
 ..._frac_N8_outbuf_only_mux_40nm_openfpga.xml | 231 ++++++++++++++++++
 1 file changed, 231 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml
new file mode 100644
index 000000000..07b4e93d8
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml
@@ -0,0 +1,231 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N8_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 8, I = 32
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:4]"/>
+      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
+      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:5]"/>
+      <port name="out" physical_mode_port="lut6_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

From f42411c29e327ed8b38c00ba2a5a8df3e51789ea Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 16:03:43 -0600
Subject: [PATCH 058/148] [Regression Tests] Add test cases for routing
 multiplexer design with input/output buffers only

---
 .../inbuf_only_mux/config/task.conf           | 37 +++++++++++++++++++
 .../outbuf_only_mux/config/task.conf          | 37 +++++++++++++++++++
 2 files changed, 74 insertions(+)
 create mode 100644 openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf
 create mode 100644 openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf

diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf
new file mode 100644
index 000000000..ed3766047
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/mux_design/inbuf_only_mux/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf b/openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf
new file mode 100644
index 000000000..da765eacd
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/mux_design/outbuf_only_mux/config/task.conf
@@ -0,0 +1,37 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From f149c88548eaf92961ca7bb14af0c6a00546aadd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 16:11:48 -0600
Subject: [PATCH 059/148] [Regression Test] Deploy input buffer only
 multiplexer testcase to CI

---
 .travis/fpga_verilog_reg_test.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index f4f0d82d0..0a46dd5de 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -58,6 +58,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/local_enc
 echo -e "Testing Verilog generation with routing multiplexers without buffers";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with behavioral description";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
 

From c31d36deb63b8fb0c1275249a56a47b3c0906af4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 16:16:03 -0600
Subject: [PATCH 060/148] [Regression Tests] Deploy output buffer only routing
 multiplexer testcase to CI

---
 .travis/fpga_verilog_reg_test.sh                    | 3 +++
 libopenfpga/libarchopenfpga/src/circuit_library.cpp | 2 +-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index 0a46dd5de..35086b65b 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -61,6 +61,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/debuf_mux
 echo -e "Testing Verilog generation with routing multiplexers with input buffers only";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/inbuf_only_mux --debug --show_thread_logs
 
+echo -e "Testing Verilog generation with routing multiplexers with output buffers only";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_only_mux --debug --show_thread_logs
+
 echo -e "Testing Verilog generation with behavioral description";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs
 
diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
index 881035ee7..42df84407 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
@@ -1963,7 +1963,7 @@ void CircuitLibrary::link_buffer_model(const CircuitModelId& model_id) {
   /* Get the circuit model id by name, skip those with empty names*/
   for (size_t buffer_id = 0; buffer_id < buffer_model_names_[model_id].size(); ++buffer_id) {
     if (true == buffer_model_names_[model_id][buffer_id].empty()) {
-      return;
+      continue;
     }
     buffer_model_ids_[model_id][buffer_id] = model(buffer_model_names_[model_id][buffer_id]);
   }

From e3559f0df98183a78cf670168150faa71467bd23 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 16:53:16 -0600
Subject: [PATCH 061/148] [Regression Test] Add compiler coverage test to CI

---
 .travis.yml       | 61 ++++++++++++++++++++++++++++++++++++++++++++---
 .travis/common.sh |  4 ++--
 2 files changed, 60 insertions(+), 5 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index bf9c42724..55bcf6254 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -15,7 +15,7 @@ cache:
 
 # Supported Operating systems
 dist: bionic
-compiler: g++-8
+#compiler: g++-8
 addons:
   apt:
     sources:
@@ -33,8 +33,6 @@ addons:
     - doxygen
     - flex
     - fontconfig
-    - g++-8
-    - gcc-8
     - gdb
     - git
     - gperf
@@ -56,6 +54,17 @@ addons:
     - zip
     - qt5-default
     - clang-format-7
+# Add all the supported compilers
+    - g++-6
+    - gcc-6
+    - g++-7
+    - gcc-7
+    - g++-8
+    - gcc-8
+    - g++-9
+    - gcc-9
+    - clang-6.0
+    - clang-8
 #- os: osx
 #  osx_image: xcode10.2 # we target latest MacOS Mojave
 #  sudo: true
@@ -76,6 +85,10 @@ addons:
 #      - libxml++
 #      - qt5
 
+# Use gcc-8 as default compiler
+env:
+  - MATRIX_EVAL="CC=gcc-8 && CXX=g++-8"
+
 before_script:
   - source .travis/common.sh
   - source .travis/install.sh
@@ -116,6 +129,48 @@ jobs:
         - source .travis/build.sh
         - source .travis/fpga_spice_reg_test.sh
 
+    - stage: Test
+      name: "Build Compatibility: GCC-6 (Ubuntu Bionic 18.04)"
+      env:
+        - MATRIX_EVAL="CC=gcc-6 && CXX=g++-6"
+      script:
+        - source .travis/build.sh
+
+    - stage: Test
+      name: "Build Compatibility: GCC-7 (Ubuntu Bionic 18.04)"
+      env:
+        - MATRIX_EVAL="CC=gcc-7 && CXX=g++-7"
+      script:
+        - source .travis/build.sh
+
+    - stage: Test
+      name: "Build Compatibility: GCC-8 (Ubuntu Bionic 18.04)"
+      env:
+        - MATRIX_EVAL="CC=gcc-8 && CXX=g++-8"
+      script:
+        - source .travis/build.sh
+
+    - stage: Test
+      name: "Build Compatibility: GCC-9 (Ubuntu Bionic 18.04)"
+      env:
+        - MATRIX_EVAL="CC=gcc-9 && CXX=g++-9"
+      script:
+        - source .travis/build.sh
+
+    - stage: Test
+      name: "Build Compatibility: Clang-6 (Ubuntu Bionic 18.04)"
+      env:
+        - MATRIX_EVAL="CC=clang-6.0 && CXX=clang++-6.0"
+      script:
+        - source .travis/build.sh
+
+    - stage: Test
+      name: "Build Compatibility: Clang-8 (Ubuntu Bionic 18.04)"
+      env:
+        - MATRIX_EVAL="CC=clang-8 && CXX=clang++-8"
+      script:
+        - source .travis/build.sh
+
 #after_failure:
 #  - .travis/after_failure.sh
 
diff --git a/.travis/common.sh b/.travis/common.sh
index a293cb00f..880d64ae8 100644
--- a/.travis/common.sh
+++ b/.travis/common.sh
@@ -39,8 +39,8 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
   sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted
 else
   # For linux, we use g++-8 and gcc-8 as default compilers
-  export CC=gcc-8
-  export CXX=g++-8
+  #export CC=gcc-8
+  #export CXX=g++-8
 fi
 
 

From c08d4f5cd9c00110f9702948b7cd364fed3c5378 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 16:59:08 -0600
Subject: [PATCH 062/148] [Regression Test] Patch travis script

---
 .travis/common.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.travis/common.sh b/.travis/common.sh
index 880d64ae8..bee008a88 100644
--- a/.travis/common.sh
+++ b/.travis/common.sh
@@ -37,7 +37,7 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
   # export PATH="/usr/local/opt/qt/bin:$PATH"
   # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h
   sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted
-else
+#else
   # For linux, we use g++-8 and gcc-8 as default compilers
   #export CC=gcc-8
   #export CXX=g++-8

From d4bac95cd4d354839f8381f8ff166a411b47cb69 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 17:07:14 -0600
Subject: [PATCH 063/148] [Regression Tests] Enable matrix eval parameter in
 setting up compilers

---
 .travis/common.sh | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/.travis/common.sh b/.travis/common.sh
index bee008a88..a5a7274de 100644
--- a/.travis/common.sh
+++ b/.travis/common.sh
@@ -37,10 +37,11 @@ if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
   # export PATH="/usr/local/opt/qt/bin:$PATH"
   # Install header files in Mojave, if not gcc-4.9 cannot spot stdio.h
   sudo installer -pkg /Library/Developer/CommandLineTools/Packages/macOS_SDK_headers_for_macOS_10.14.pkg -target / -allowUntrusted
-#else
+else
   # For linux, we use g++-8 and gcc-8 as default compilers
-  #export CC=gcc-8
-  #export CXX=g++-8
+  eval "${MATRIX_EVAL}"
+  export "CC=$CC"
+  export "CXX=$CXX"
 fi
 
 

From fc6bfdc7a22cf2be757911d976b01da408257991 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 18:55:21 -0600
Subject: [PATCH 064/148] [OpenFPGA Code] Patch syntax compatibility for older
 gcc

---
 libopenfpga/libopenfpgautil/src/openfpga_decode.h  | 1 +
 libopenfpga/libopenfpgautil/src/openfpga_scale.cpp | 6 +++---
 openfpga/src/base/io_location_map.h                | 1 +
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/libopenfpga/libopenfpgautil/src/openfpga_decode.h b/libopenfpga/libopenfpgautil/src/openfpga_decode.h
index ab6778c86..85809fee2 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_decode.h
+++ b/libopenfpga/libopenfpgautil/src/openfpga_decode.h
@@ -4,6 +4,7 @@
 /********************************************************************
  * Include header files that are required by function declaration
  *******************************************************************/
+#include <stddef.h>
 #include <vector>
 
 /********************************************************************
diff --git a/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp b/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp
index 9baa753d1..66364501d 100644
--- a/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp
+++ b/libopenfpga/libopenfpgautil/src/openfpga_scale.cpp
@@ -140,7 +140,7 @@ float string_to_unit(const std::string& scale) {
   /* Invalid unit report error */
   VTR_LOGF_ERROR(__FILE__, __LINE__,
                  "Invalid unit %s!\nAcceptable units are [a|f|p|n|u|k|M|B|T] or empty\n",
-                 scale); 
+                 scale.c_str()); 
   exit(1);
 }
 
@@ -153,13 +153,13 @@ float string_to_time_unit(const std::string& scale) {
     && (2 != scale.length()) ) {
     VTR_LOGF_ERROR(__FILE__, __LINE__,
                    "Time unit (='%s') must contain only one or two characters!\n",
-                   scale);
+                   scale.c_str());
   } 
   /* The last character must be 's' */
   if ('s' != scale.back()) {
     VTR_LOGF_ERROR(__FILE__, __LINE__,
                    "Time unit (='%s') must end with 's'!\n",
-                   scale);
+                   scale.c_str());
   }
 
   float unit = 1.;
diff --git a/openfpga/src/base/io_location_map.h b/openfpga/src/base/io_location_map.h
index de6422d23..ef326a66a 100644
--- a/openfpga/src/base/io_location_map.h
+++ b/openfpga/src/base/io_location_map.h
@@ -4,6 +4,7 @@
 /********************************************************************
  * Include header files required by the data structure definition
  *******************************************************************/
+#include <stddef.h>
 #include <vector>
 
 /* Begin namespace openfpga */

From c23742c7517e70cc39f5f5d0ec35ac39e9e38fb0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 20:13:27 -0600
Subject: [PATCH 065/148] [OpenFPGA code] fix bug for clang compatibility

---
 libopenfpga/libopenfpgashell/src/command_parser.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libopenfpga/libopenfpgashell/src/command_parser.cpp b/libopenfpga/libopenfpgashell/src/command_parser.cpp
index 5e0397421..b2daf12f7 100644
--- a/libopenfpga/libopenfpgashell/src/command_parser.cpp
+++ b/libopenfpga/libopenfpgashell/src/command_parser.cpp
@@ -67,7 +67,7 @@ bool parse_command(const std::vector<std::string>& argv,
   /* Validate that the command name matches argv[0] */
   if (argv[0] != cmd.name()) { 
     VTR_LOG("Unexpected command name '%s'!\n",
-            argv[0]);
+            argv[0].c_str());
     return false;
   }
 

From b43cd2741df94a9a164a0d68dbf3eb4d2dfc01c0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 20:14:16 -0600
Subject: [PATCH 066/148] [Regression Tests] Add gcc-5 compatibility test to
 Travis CI

---
 .travis.yml | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/.travis.yml b/.travis.yml
index 55bcf6254..c4349f39c 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -55,6 +55,8 @@ addons:
     - qt5-default
     - clang-format-7
 # Add all the supported compilers
+    - g++-5
+    - gcc-5
     - g++-6
     - gcc-6
     - g++-7
@@ -129,6 +131,13 @@ jobs:
         - source .travis/build.sh
         - source .travis/fpga_spice_reg_test.sh
 
+    - stage: Test
+      name: "Build Compatibility: GCC-5 (Ubuntu Bionic 18.04)"
+      env:
+        - MATRIX_EVAL="CC=gcc-5 && CXX=g++-5"
+      script:
+        - source .travis/build.sh
+
     - stage: Test
       name: "Build Compatibility: GCC-6 (Ubuntu Bionic 18.04)"
       env:

From 8b6c8f73e9a1a7a54f7019e2ef1c8d0da0dba792 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 14 Sep 2020 21:26:53 -0600
Subject: [PATCH 067/148] [OpenFPGA code] fix bug for clang compatibility

---
 libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
index 9fb61a654..0954a0086 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
@@ -459,7 +459,7 @@ void read_xml_output_mask(pugi::xml_node& xml_port,
     if (circuit_lib.port_size(port) != mask_vector.size()) {
       archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_port),
                      "Invalid lut_output_mask attribute '%s'! It must match the port size (=%lu)\n",
-                     output_mask_attr, circuit_lib.port_size(port));
+                     output_mask_attr.c_str(), circuit_lib.port_size(port));
     } 
   } else {
     /* By default, we give a mask vector covering each pin of the port */

From 3c0faf0021a9507a2a7b13f0c1d815aa68e00f8a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 17:27:24 -0600
Subject: [PATCH 068/148] [OpenFPGA Architecture] Add a new architecture with
 fully connected crossbar at CLB outputs

---
 ..._N4_tileable_full_output_crossbar_40nm.xml | 291 ++++++++++++++++++
 1 file changed, 291 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
new file mode 100644
index 000000000..f1d8ac1d3
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
@@ -0,0 +1,291 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+  - Local routing: a fully connected crossbar between LEs and CLB outputs
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="10" equivalent="full"/>
+      <output name="O" num_pins="4" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!--/auto_layout-->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="10" equivalent="full"/>
+      <output name="O" num_pins="4" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 4-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="input_crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <complete name="output_crossbar" input="fle[3:0].out" output="clb.O">
+          <delay_constant max="45e-12" in_port="fle[3:0].out" out_port="clb.O"/>
+        </complete>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 30fb99095fc557f7be1ec1e4d6b3062cd889a816 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 17:29:15 -0600
Subject: [PATCH 069/148] [Regression Tests] Add new test case for fully
 connected output crossbar

---
 .../config/task.conf                          | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf

diff --git a/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf
new file mode 100644
index 000000000..e9e253d1d
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_frame_40nm_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+external_fabric_key_file=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N4_tileable_full_output_crossbar_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 030d7f02f84c7275fd83c8156066ff94c7b6c0ed Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 17:30:08 -0600
Subject: [PATCH 070/148] [OpenFPGA architecture] bug fix in the fully
 connected output crossbar architecture

---
 .../vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
index f1d8ac1d3..b4be8823f 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
@@ -268,7 +268,7 @@
 		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
 		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
 		     to get the part that should be marked on the crossbar.	 -->
-        <complete name="input_crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
           <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
           <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
         </complete>

From 35d47ee0e74a656d3c712a8052cf28d6b962d07e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 17:33:54 -0600
Subject: [PATCH 071/148] [Regression tests] bug fix in the test case for fully
 connected output crossbar

---
 .../fully_connected_output_crossbar/config/task.conf          | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf
index e9e253d1d..f8717b5fd 100644
--- a/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf
@@ -17,12 +17,12 @@ fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_frame_40nm_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N4_tileable_full_output_crossbar_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif

From 5fe039dd7cc7c8aed34e414ca9e9fb45ed2904c0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 17:35:49 -0600
Subject: [PATCH 072/148] [Regression Tests] Deploy the fully connected
 crossbar test to CI

---
 .travis/fpga_verilog_reg_test.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index 35086b65b..8956cab1e 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -90,6 +90,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/power_gated_design/p
 echo -e "Testing Depopulated crossbar in local routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar --debug --show_thread_logs
 
+echo -e "Testing Fully connected output crossbar in local routing";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
+
 echo -e "Testing through channels in tileable routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs

From f5b7ac62698ec5ca541327d8a1ad5866d0ec1bba Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 18:04:55 -0600
Subject: [PATCH 073/148] [OpenFPGA Architecture] Add a new architecture with
 no local routing

---
 ...4_no_local_routing_40nm_frame_openfpga.xml | 196 ++++++++++++
 .../k4_N4_tileable_no_local_routing_40nm.xml  | 286 ++++++++++++++++++
 2 files changed, 482 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
 create mode 100644 openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml

diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
new file mode 100644
index 000000000..9ba39b3ce
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
@@ -0,0 +1,196 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" size="1"/>
+       <port type="wl" prefix="wl" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="config_latch"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
new file mode 100644
index 000000000..4605da01e
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
@@ -0,0 +1,286 @@
+<!-- 
+  Architecture with no fracturable LUTs
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+  - Local routing: a fully connected crossbar between LEs and CLB outputs
+
+  Details on Modelling:
+
+  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
+
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I0" num_pins="4" equivalent="full"/>
+      <input name="I1" num_pins="4" equivalent="full"/>
+      <input name="I2" num_pins="4" equivalent="full"/>
+      <input name="I3" num_pins="4" equivalent="full"/>
+      <output name="O" num_pins="4" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!--/auto_layout-->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" packable="false">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I0" num_pins="4" equivalent="full"/>
+      <input name="I1" num_pins="4" equivalent="full"/>
+      <input name="I2" num_pins="4" equivalent="full"/>
+      <input name="I3" num_pins="4" equivalent="full"/>
+      <output name="O" num_pins="4" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe basic logic element.  
+             Each basic logic element has a 4-LUT that can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <output name="out" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <direct name="crossbar0" input="clb.I0" output="fle[0:0].in">
+        <direct name="crossbar1" input="clb.I1" output="fle[1:1].in">
+        <direct name="crossbar2" input="clb.I2" output="fle[2:2].in">
+        <direct name="crossbar3" input="clb.I3" output="fle[3:3].in">
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="output_crossbar" input="fle[3:0].out" output="clb.O"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From c40c9f58767d29965ba35f678aa146b34b7718e0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 18:05:33 -0600
Subject: [PATCH 074/148] [Regression test] add test case for no local routing
 architecture

---
 .../no_local_routing/config/task.conf         | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf

diff --git a/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf
new file mode 100644
index 000000000..c076b156c
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+external_fabric_key_file=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From c22d8e242136d4b955b65e055a2d7e5f58560420 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 18:07:52 -0600
Subject: [PATCH 075/148] [Architecture] Bug fix in no local routing
 architecture

---
 .../vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml     | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
index 4605da01e..06499b328 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
@@ -265,10 +265,10 @@
         <!-- 6-LUT mode definition end -->
       </pb_type>
       <interconnect>
-        <direct name="crossbar0" input="clb.I0" output="fle[0:0].in">
-        <direct name="crossbar1" input="clb.I1" output="fle[1:1].in">
-        <direct name="crossbar2" input="clb.I2" output="fle[2:2].in">
-        <direct name="crossbar3" input="clb.I3" output="fle[3:3].in">
+        <direct name="crossbar0" input="clb.I0" output="fle[0:0].in"/>
+        <direct name="crossbar1" input="clb.I1" output="fle[1:1].in"/>
+        <direct name="crossbar2" input="clb.I2" output="fle[2:2].in"/>
+        <direct name="crossbar3" input="clb.I3" output="fle[3:3].in"/>
         <complete name="clks" input="clb.clk" output="fle[3:0].clk">
         </complete>
         <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  

From 2aff461f59827b64bad2ff0f031be8cc2a8be9ab Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 18:09:24 -0600
Subject: [PATCH 076/148] [Regression Tests] Deploy no local routing test case
 to CI

---
 .travis/fpga_verilog_reg_test.sh | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index 8956cab1e..a8d1e8eb7 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -93,6 +93,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar
 echo -e "Testing Fully connected output crossbar in local routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
 
+echo -e "Testing no local routing architecture";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/no_local_routing --debug --show_thread_logs
+
 echo -e "Testing through channels in tileable routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs

From ca1bafc6886adfc98fa2c0cba6408c1f4108c480 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 19:26:12 -0600
Subject: [PATCH 077/148] [OpenFPGA Architecture] Add full pin equivalence to
 full output crossbar architecture

---
 .../vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml     | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
index b4be8823f..16ceb2be2 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
@@ -55,7 +55,7 @@
         <site pb_type="clb"/>
       </equivalent_sites>
       <input name="I" num_pins="10" equivalent="full"/>
-      <output name="O" num_pins="4" equivalent="none"/>
+      <output name="O" num_pins="4" equivalent="full"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
       <pinlocations pattern="spread"/>
@@ -200,7 +200,7 @@
 	   -->
     <pb_type name="clb">
       <input name="I" num_pins="10" equivalent="full"/>
-      <output name="O" num_pins="4" equivalent="none"/>
+      <output name="O" num_pins="4" equivalent="full"/>
       <clock name="clk" num_pins="1"/>
       <!-- Describe basic logic element.  
              Each basic logic element has a 4-LUT that can be optionally registered

From 9cfb2f52ef320065221d1e2e4249854e8316b34d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 16 Sep 2020 19:26:46 -0600
Subject: [PATCH 078/148] [OpenFPGA code] bug fix for fully equivalent outputs
 of pb_type

---
 openfpga/src/base/openfpga_pb_pin_fixup.cpp |   1 +
 openfpga/src/repack/repack.cpp              | 106 ++++++++++++++++----
 2 files changed, 87 insertions(+), 20 deletions(-)

diff --git a/openfpga/src/base/openfpga_pb_pin_fixup.cpp b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
index 2a8686190..17c48fb5b 100644
--- a/openfpga/src/base/openfpga_pb_pin_fixup.cpp
+++ b/openfpga/src/base/openfpga_pb_pin_fixup.cpp
@@ -133,6 +133,7 @@ void update_cluster_pin_with_post_routing_results(const DeviceContext& device_ct
     if (routing_net_id == cluster_net_id) {
       continue;
     }
+
     /* Add to net modification */
     vpr_clustering_annotation.rename_net(blk_id, j, routing_net_id);
  
diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index 39697f100..c3ab88f1c 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -38,6 +38,8 @@ static
 void rec_find_routed_sink_pb_graph_pins(const t_pb* pb,
                                         const t_pb_graph_pin* source_pb_pin,
                                         const AtomNetId& atom_net_id,
+                                        const VprDeviceAnnotation& device_annotation,
+                                        const std::map<const t_pb_graph_pin*, AtomNetId>& pb_pin_mapped_nets,
                                         t_pb_graph_pin** pb_graph_pin_lookup_from_index,
                                         std::vector<t_pb_graph_pin*>& sink_pb_pins) {
 
@@ -69,7 +71,49 @@ void rec_find_routed_sink_pb_graph_pins(const t_pb* pb,
 
     if ( (true == sink_pb_pin->parent_node->is_root())
       && (OUT_PORT == sink_pb_pin->port->type)) {
-      sink_pb_pins.push_back(sink_pb_pin);
+      /* Be careful!!! There is an inconsistency between pb_route and actual net mapping!
+       * The sink_pb_pin in the pb_route may not be the one we want
+       * due to net remapping in the routing stage
+       * If the net becomes invalid, we search all the fan-out of the source pb_pin 
+       * and find one that is mapped to the net
+       */
+      AtomNetId remapped_net = AtomNetId::INVALID(); 
+      auto remapped_result = pb_pin_mapped_nets.find(sink_pb_pin);
+      if (remapped_result != pb_pin_mapped_nets.end()) {
+        remapped_net = remapped_result->second; 
+      }
+      if (atom_net_id == remapped_net) {
+        sink_pb_pins.push_back(sink_pb_pin);
+      } else {
+        VTR_ASSERT_SAFE(atom_net_id != remapped_net);
+        bool found_actual_sink_pb_pin = false;
+        for (int iedge = 0; iedge < source_pb_pin->num_output_edges; ++iedge) {
+          /* Bypass the interconnect that does not belong to a physical mode */
+          int parent_mode_index = source_pb_pin->output_edges[iedge]->interconnect->parent_mode_index;
+          VTR_ASSERT(parent_mode_index < sink_pb_pin->parent_node->pb_type->num_modes);
+          if (&(sink_pb_pin->parent_node->pb_type->modes[parent_mode_index])
+              != device_annotation.physical_mode(sink_pb_pin->parent_node->pb_type)) {
+            continue;
+          }
+          for (int ipin = 0; ipin < source_pb_pin->output_edges[iedge]->num_output_pins; ++ipin) {
+            const t_pb_graph_pin* cand_sink_pb_pin = source_pb_pin->output_edges[iedge]->output_pins[ipin];
+            auto cand_remapped_result = pb_pin_mapped_nets.find(cand_sink_pb_pin);
+            AtomNetId cand_sink_pb_pin_net = AtomNetId::INVALID(); 
+            if (cand_remapped_result != pb_pin_mapped_nets.end()) {
+              cand_sink_pb_pin_net = cand_remapped_result->second; 
+            }
+            if (atom_net_id == cand_sink_pb_pin_net) {
+              sink_pb_pins.push_back(const_cast<t_pb_graph_pin*>(cand_sink_pb_pin));
+              found_actual_sink_pb_pin = true;
+              break;
+            }
+          }
+          if (true == found_actual_sink_pb_pin) {
+            break;
+          }
+        }
+        VTR_ASSERT(true == found_actual_sink_pb_pin);
+      }
       continue;
     }
 
@@ -78,7 +122,7 @@ void rec_find_routed_sink_pb_graph_pins(const t_pb* pb,
   }
 
   for (t_pb_graph_pin* sink_pb_pin : sink_pb_pins_to_search) {
-    rec_find_routed_sink_pb_graph_pins(pb, sink_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index, sink_pb_pins);
+    rec_find_routed_sink_pb_graph_pins(pb, sink_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index, sink_pb_pins);
   }
 }
 
@@ -90,10 +134,12 @@ static
 std::vector<t_pb_graph_pin*> find_routed_pb_graph_pins_atom_net(const t_pb* pb,
                                                                 const t_pb_graph_pin* source_pb_pin,
                                                                 const AtomNetId& atom_net_id,
+                                                                const VprDeviceAnnotation& device_annotation,
+                                                                const std::map<const t_pb_graph_pin*, AtomNetId>& pb_pin_mapped_nets,
                                                                 t_pb_graph_pin** pb_graph_pin_lookup_from_index) {
   std::vector<t_pb_graph_pin*> sink_pb_pins;  
 
-  rec_find_routed_sink_pb_graph_pins(pb, source_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index, sink_pb_pins);
+  rec_find_routed_sink_pb_graph_pins(pb, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index, sink_pb_pins);
 
   return sink_pb_pins; 
 }
@@ -227,6 +273,34 @@ void add_lb_router_nets(LbRouter& lb_router,
   /* Build the fast look-up between pb_pin_id and pb_graph_pin pointer */
   t_pb_graph_pin** pb_graph_pin_lookup_from_index = alloc_and_load_pb_graph_pin_lookup_from_index(lb_type);
 
+  /* Build a fast look-up between pb_graph_pin and atom net id which it is mapped to 
+   * Note that, we only care the pb_graph_pin at the root pb_graph_node
+   * where pb_graph_pin may be remapped to a new net due to routing optimization
+   */
+  std::map<const t_pb_graph_pin*, AtomNetId> pb_pin_mapped_nets;
+  for (int j = 0; j < lb_type->pb_type->num_pins; j++) {
+    /* Find the net mapped to this pin in clustering results*/
+    ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(block_id, j);
+    /* Get the actual net id because it may be renamed during routing */
+    if (true == clustering_annotation.is_net_renamed(block_id, j)) {
+      cluster_net_id = clustering_annotation.net(block_id, j);
+    }
+
+    /* Bypass unmapped pins */
+    if (ClusterNetId::INVALID() == cluster_net_id) {
+      continue;
+    }
+
+    /* Get the source pb_graph pin and find the rr_node in logical block routing resource graph */
+    const t_pb_graph_pin* pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, j);
+    VTR_ASSERT(pb_pin->parent_node == pb->pb_graph_node);
+
+    AtomNetId atom_net_id = atom_ctx.lookup.atom_net(cluster_net_id);
+    VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
+
+    pb_pin_mapped_nets[pb_pin] = atom_net_id;
+  }
+
   /* Cache all the source nodes and sinks node for each net
    * net_terminal[net][0] is the list of source nodes 
    * net_terminal[net][1] is the list of sink nodes 
@@ -238,17 +312,6 @@ void add_lb_router_nets(LbRouter& lb_router,
 
   /* Find the source nodes for the nets mapped to inputs of a clustered block */
   for (int j = 0; j < lb_type->pb_type->num_pins; j++) {
-    /* Find the net mapped to this pin in clustering results*/
-    ClusterNetId cluster_net_id = clustering_ctx.clb_nlist.block_net(block_id, j);
-    /* Get the actual net id because it may be renamed during routing */
-    if (true == clustering_annotation.is_net_renamed(block_id, j)) {
-      cluster_net_id = clustering_annotation.net(block_id, j);
-    }
-    /* Bypass unmapped pins */
-    if (ClusterNetId::INVALID() == cluster_net_id) {
-      continue;
-    }
-
     /* Get the source pb_graph pin and find the rr_node in logical block routing resource graph */
     const t_pb_graph_pin* source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, j);
     VTR_ASSERT(source_pb_pin->parent_node == pb->pb_graph_node);
@@ -258,22 +321,25 @@ void add_lb_router_nets(LbRouter& lb_router,
       continue;
     }
 
+    /* Find the net mapped to this pin in clustering results*/
+    AtomNetId atom_net_id = pb_pin_mapped_nets[source_pb_pin];
+    /* Bypass unmapped pins */
+    if (AtomNetId::INVALID() == atom_net_id) {
+      continue;
+    }
+
     /* The outputs of pb_graph_node is INTERMEDIATE node in the routing resource graph,
      * they are all connected to a common source node
      */
     LbRRNodeId source_lb_rr_node = lb_rr_graph.find_node(LB_INTERMEDIATE, source_pb_pin);
     VTR_ASSERT(true == lb_rr_graph.valid_node_id(source_lb_rr_node));
 
-    AtomNetId atom_net_id = atom_ctx.lookup.atom_net(cluster_net_id);
-    VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
-
-
     int pb_route_index = find_pb_route_remapped_source_pb_pin(pb, source_pb_pin, atom_net_id);
     t_pb_graph_pin* packing_source_pb_pin = get_pb_graph_node_pin_from_block_pin(block_id, pb_route_index);
     VTR_ASSERT(nullptr != packing_source_pb_pin);
 
     /* Find all the sink pins in the pb_route, we walk through the input pins and find the pin  */
-    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, packing_source_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index);
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index);
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
@@ -338,7 +404,7 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
 
     /* Find all the sink pins in the pb_route */
-    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, atom_net_id, pb_graph_pin_lookup_from_index);
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index);
 
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());

From de48b8c7b2f01ae9d81c6b2a81a9a3162796d0c1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 17 Sep 2020 10:21:25 -0600
Subject: [PATCH 079/148] [Benchmark]  Add a new micro benchmark to test
 fracturable LUTs

---
 .../micro_benchmark/and2_or2/and2_or2.act     |  4 ++++
 .../micro_benchmark/and2_or2/and2_or2.blif    | 11 ++++++++++
 .../micro_benchmark/and2_or2/and2_or2.v       | 22 +++++++++++++++++++
 3 files changed, 37 insertions(+)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
new file mode 100644
index 000000000..33c156f30
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
@@ -0,0 +1,4 @@
+a 0.5 0.5
+b 0.5 0.5
+c 0.25 0.25
+d 0.25 0.25
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
new file mode 100644
index 000000000..88e7fcf9a
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
@@ -0,0 +1,11 @@
+.model and2_or2
+.inputs a b
+.outputs c d
+
+.names a b c
+11 1
+
+.names a b d
+00 1
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
new file mode 100644
index 000000000..b57cdeffe
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
@@ -0,0 +1,22 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND + 2-input OR 
+//                 This benchmark is designed to test fracturable LUTs
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and2_or2(
+  a,
+  b,
+  c,
+  d);
+
+input wire a;
+input wire b;
+output wire c;
+output wire d;
+
+assign c = a & b;
+assign d = a | b;
+
+endmodule

From 367cf59efda561d110157ad7ddbf91a5c721f214 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 17 Sep 2020 10:35:13 -0600
Subject: [PATCH 080/148] [Benchmark] Bug fix in the and2_or2 benchmark

---
 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
index 88e7fcf9a..14a8bc6eb 100644
--- a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
@@ -6,6 +6,6 @@
 11 1
 
 .names a b d
-00 1
+00 0
 
 .end

From 681e80d4b62c68c56494439c424fa4f4887ea007 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 17 Sep 2020 10:39:22 -0600
Subject: [PATCH 081/148] [Regression tests] update frac_lut test case using
 more representative benchmarks

---
 .../fpga_verilog/lut_design/frac_lut/config/task.conf      | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf
index fbe91030d..1809feae5 100644
--- a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf
@@ -27,6 +27,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
 #
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
 bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
 # Modelsim is ok with this but icarus fails due to poor support on timing and looping
 #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
 
@@ -39,9 +40,9 @@ bench1_top = routing_test
 bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
 bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
 
-bench2_top = and2_latch
-bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act
-bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+bench2_top = and2_or2
+bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
+bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

From ccd9ebe71b5087e49ba0c11472ac6d40fee6dbad Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 17 Sep 2020 16:59:20 -0600
Subject: [PATCH 082/148] [Documentation] Use travis.com in CI badge as
 travis.org will be deprecated by the end of 2020

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 614d295c3..4c05b4f94 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
 # Getting Started with OpenFPGA <img src="./docs/source/figures/OpenFPGA_logo.png" width="200" align="right">
-[![Build Status](https://travis-ci.org/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
+[![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
 
 ## Introduction

From 9e4353ddf4d0af0496162eb8b30df6384e9d649c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 17 Sep 2020 17:01:23 -0600
Subject: [PATCH 083/148] [Documentation] Patch on the travis link

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 4c05b4f94..1965b9b47 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,5 @@
 # Getting Started with OpenFPGA <img src="./docs/source/figures/OpenFPGA_logo.png" width="200" align="right">
-[![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.org/LNIS-Projects/OpenFPGA)
+[![Build Status](https://travis-ci.com/LNIS-Projects/OpenFPGA.svg?branch=master)](https://travis-ci.com/LNIS-Projects/OpenFPGA)
 [![Documentation Status](https://readthedocs.org/projects/openfpga/badge/?version=master)](https://openfpga.readthedocs.io/en/master/?badge=master)
 
 ## Introduction

From 51d423e4dba703f05e4ab78cdb2e1a2d5d62e77e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 14:59:00 -0600
Subject: [PATCH 084/148] [FPGA-SPICE] Add pass-gate SPICE netlist writer

---
 .../src/fpga_spice/spice_essential_gates.cpp  |  20 +-
 openfpga/src/fpga_spice/spice_passgate.cpp    | 338 ++++++++++++++++++
 openfpga/src/fpga_spice/spice_passgate.h      |  30 ++
 3 files changed, 386 insertions(+), 2 deletions(-)
 create mode 100644 openfpga/src/fpga_spice/spice_passgate.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_passgate.h

diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index 7fd144f33..2a916f60e 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -1,6 +1,6 @@
 /************************************************
  * This file includes functions on 
- * outputting Verilog netlists for essential gates
+ * outputting SPICE netlists for essential gates
  * which are inverters, buffers, transmission-gates
  * logic gates etc. 
  ***********************************************/
@@ -22,6 +22,7 @@
 
 #include "spice_constants.h"
 #include "spice_writer_utils.h"
+#include "spice_passgate.h"
 #include "spice_essential_gates.h"
 
 /* begin namespace openfpga */
@@ -1046,7 +1047,7 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == tech_lib.model_type(tech_model));
     }
 
-    /* Now branch on netlist writing */
+    /* Now branch on netlist writing: for inverter/buffers */
     if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
       if (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) {
         VTR_ASSERT(true == module_manager.valid_module_id(module_id));
@@ -1069,6 +1070,21 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       /* Finish, go to the next */
       continue;
     }
+
+    /* Now branch on netlist writing: for inverter/buffers */
+    if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
+      status = print_spice_passgate_subckt(fp,
+                                           module_manager, module_id,
+                                           circuit_lib, circuit_model,
+                                           tech_lib, tech_model);
+
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        break;
+      }
+
+      /* Finish, go to the next */
+      continue;
+    }
   } 
 
   /* Close file handler*/
diff --git a/openfpga/src/fpga_spice/spice_passgate.cpp b/openfpga/src/fpga_spice/spice_passgate.cpp
new file mode 100644
index 000000000..a54956849
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_passgate.cpp
@@ -0,0 +1,338 @@
+/************************************************
+ * This file includes functions on 
+ * outputting SPICE netlists for transmission-gates
+ ***********************************************/
+#include <fstream>
+#include <cmath>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "circuit_library_utils.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_passgate.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Generate the SPICE modeling for the PMOS part of a pass-gate logic
+ *
+ * This function is created to be shared by pass-transistor and
+ * transmission-gate SPICE netlist writer
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   a pass-gate. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+static 
+int print_spice_passgate_pmos_modeling(std::fstream& fp,
+                                       const std::string& trans_name_postfix,
+                                       const std::string& input_port_name,
+                                       const std::string& gate_port_name,
+                                       const std::string& output_port_name,
+                                       const TechnologyLibrary& tech_lib,
+                                       const TechnologyModelId& tech_model,
+                                       const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Write transistor pairs using the technology model */
+  fp << "Xpmos_" << trans_name_postfix << " ";
+  fp << input_port_name << " "; 
+  fp << gate_port_name << " "; 
+  fp << output_port_name << " "; 
+  fp << "LVDD "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE modeling for the NMOS part of a pass-gate logic
+ *
+ * This function is created to be shared by pass-transistor and
+ * transmission-gate SPICE netlist writer
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   a pass-gate. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+static 
+int print_spice_passgate_nmos_modeling(std::fstream& fp,
+                                       const std::string& trans_name_postfix,
+                                       const std::string& input_port_name,
+                                       const std::string& gate_port_name,
+                                       const std::string& output_port_name,
+                                       const TechnologyLibrary& tech_lib,
+                                       const TechnologyModelId& tech_model,
+                                       const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  fp << "Xnmos_" << trans_name_postfix << " ";
+  fp << input_port_name << " "; 
+  fp << gate_port_name << " "; 
+  fp << output_port_name << " "; 
+  fp << "LGND "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for a pass-transistor
+ *
+ * Schematic
+ *
+ *        sel
+ *         |
+ *        ===
+ *        | |
+ *   in --  ---out
+ *
+ *******************************************************************/
+static 
+int print_spice_pass_transistor_subckt(std::fstream& fp,
+                                       const ModuleManager& module_manager,
+                                       const ModuleId& module_id,
+                                       const CircuitLibrary& circuit_lib,
+                                       const CircuitModelId& circuit_model,
+                                       const TechnologyLibrary& tech_lib,
+                                       const TechnologyModelId& tech_model) {
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There is only 2 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT(2 == input_ports.size());
+  for (const auto& input_port : input_ports) {
+     VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+  }
+
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  float total_nmos_width = circuit_lib.pass_gate_logic_nmos_size(circuit_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+
+  for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+    float curr_bin_width = regular_nmos_bin_width;
+    /* For last bin, we need an irregular width */
+    if ((ibin == num_nmos_bins - 1) 
+       && (0. != last_nmos_bin_width)) {
+      curr_bin_width = last_nmos_bin_width;
+    }
+
+    status = print_spice_passgate_nmos_modeling(fp,
+                                                std::to_string(ibin),
+                                                circuit_lib.port_prefix(input_ports[0]), 
+                                                circuit_lib.port_prefix(input_ports[1]), 
+                                                circuit_lib.port_prefix(output_ports[0]), 
+                                                tech_lib,
+                                                tech_model,
+                                                curr_bin_width);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return status;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for a transmission gate
+ *
+ * Schematic
+ * 
+ *        selb
+ *         |
+ *         o
+ *        ===
+ *        | |
+ *   in --  ---out
+ *        | |
+ *        ===
+ *         |
+ *        sel
+ *
+ *******************************************************************/
+static 
+int print_spice_transmission_gate_subckt(std::fstream& fp,
+                                         const ModuleManager& module_manager,
+                                         const ModuleId& module_id,
+                                         const CircuitLibrary& circuit_lib,
+                                         const CircuitModelId& circuit_model,
+                                         const TechnologyLibrary& tech_lib,
+                                         const TechnologyModelId& tech_model) {
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There is only 3 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT(3 == input_ports.size());
+  for (const auto& input_port : input_ports) {
+     VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+  }
+
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  float total_pmos_width = circuit_lib.pass_gate_logic_pmos_size(circuit_model)
+                           * tech_lib.model_pn_ratio(tech_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
+  float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
+  for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
+    float curr_bin_width = regular_pmos_bin_width;
+    /* For last bin, we need an irregular width */
+    if ((ibin == num_pmos_bins - 1) 
+       && (0. != last_pmos_bin_width)) {
+      curr_bin_width = last_pmos_bin_width;
+    }
+
+    status = print_spice_passgate_pmos_modeling(fp,
+                                                std::to_string(ibin),
+                                                circuit_lib.port_prefix(input_ports[0]), 
+                                                circuit_lib.port_prefix(input_ports[2]), 
+                                                circuit_lib.port_prefix(output_ports[0]), 
+                                                tech_lib,
+                                                tech_model,
+                                                curr_bin_width);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  float total_nmos_width = circuit_lib.pass_gate_logic_nmos_size(circuit_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+
+  for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+    float curr_bin_width = regular_nmos_bin_width;
+    /* For last bin, we need an irregular width */
+    if ((ibin == num_nmos_bins - 1) 
+       && (0. != last_nmos_bin_width)) {
+      curr_bin_width = last_nmos_bin_width;
+    }
+
+    status = print_spice_passgate_nmos_modeling(fp,
+                                                std::to_string(ibin),
+                                                circuit_lib.port_prefix(input_ports[0]), 
+                                                circuit_lib.port_prefix(input_ports[1]), 
+                                                circuit_lib.port_prefix(output_ports[0]), 
+                                                tech_lib,
+                                                tech_model,
+                                                curr_bin_width);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return status;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for a pass-gate
+ *
+ * Note: 
+ * - This function supports both pass-transistor
+ *   and transmission gates
+ *******************************************************************/
+int print_spice_passgate_subckt(std::fstream& fp,
+                                const ModuleManager& module_manager,
+                                const ModuleId& module_id,
+                                const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& circuit_model,
+                                const TechnologyLibrary& tech_lib,
+                                const TechnologyModelId& tech_model) {
+  int status = CMD_EXEC_SUCCESS;
+
+  if (CIRCUIT_MODEL_PASS_GATE_TRANSISTOR == circuit_lib.pass_gate_logic_type(circuit_model)) {
+    status = print_spice_pass_transistor_subckt(fp,
+                                                module_manager, module_id,
+                                                circuit_lib, circuit_model,
+                                                tech_lib, tech_model);
+  } else if (CIRCUIT_MODEL_PASS_GATE_TRANSMISSION == circuit_lib.is_power_gated(circuit_model)) {
+    status = print_spice_transmission_gate_subckt(fp,
+                                                  module_manager, module_id,
+                                                  circuit_lib, circuit_model,
+                                                  tech_lib, tech_model);
+  }
+ 
+  return status;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_passgate.h b/openfpga/src/fpga_spice/spice_passgate.h
new file mode 100644
index 000000000..96a292809
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_passgate.h
@@ -0,0 +1,30 @@
+#ifndef SPICE_PASSGATE_H
+#define SPICE_PASSGATE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <map>
+#include "module_manager.h"
+#include "circuit_library.h"
+#include "technology_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_passgate_subckt(std::fstream& fp,
+                                const ModuleManager& module_manager,
+                                const ModuleId& module_id,
+                                const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& circuit_model,
+                                const TechnologyLibrary& tech_lib,
+                                const TechnologyModelId& tech_model);
+
+} /* end namespace openfpga */
+
+#endif

From f5dadca884c0086b1de64396ded980f76f91bc83 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 15:07:48 -0600
Subject: [PATCH 085/148] [FPGA-SPICE] Optimize the print-out of SPICE ports

---
 .../src/fpga_spice/spice_writer_utils.cpp     | 23 +++++++++++++++++--
 openfpga/src/fpga_spice/spice_writer_utils.h  |  3 ++-
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/fpga_spice/spice_writer_utils.cpp b/openfpga/src/fpga_spice/spice_writer_utils.cpp
index f3c4ab4d7..89b82a027 100644
--- a/openfpga/src/fpga_spice/spice_writer_utils.cpp
+++ b/openfpga/src/fpga_spice/spice_writer_utils.cpp
@@ -70,10 +70,21 @@ void print_spice_comment(std::fstream& fp,
 
 /************************************************
  * Generate a string for a port in SPICE format
+ * If the pin id is zero, e.g., A[0], the option
+ * 'omit_pin_zero' may be turned on for compact port
+ * print-out, e.g., A
  ***********************************************/
-std::string generate_spice_port(const BasicPort& port) {
+std::string generate_spice_port(const BasicPort& port,
+                                const bool& omit_pin_zero) {
   VTR_ASSERT(1 == port.get_width());
+
   std::string ret = port.get_name();
+
+  if ((true == omit_pin_zero)
+     && (0 == port.get_lsb())) {
+    return ret;
+  }
+
   ret += "[";
   ret += std::to_string(port.get_lsb());
   ret += "]";
@@ -119,7 +130,15 @@ void print_spice_subckt_definition(std::fstream& fp,
         
         BasicPort port_pin(port.get_name(), pin, pin);
 
-        fp << generate_spice_port(port_pin);
+        /* For single-bit port,
+         * we can print the port name directly
+         */
+        bool omit_pin_zero = false;
+        if ((1 == port.pins().size())
+           && (0 == pin)) {
+          omit_pin_zero = true;
+        }
+        fp << generate_spice_port(port_pin, omit_pin_zero);
 
         /* Increase the counter */
         pin_cnt++;
diff --git a/openfpga/src/fpga_spice/spice_writer_utils.h b/openfpga/src/fpga_spice/spice_writer_utils.h
index 5aa1882c9..3da2a6339 100644
--- a/openfpga/src/fpga_spice/spice_writer_utils.h
+++ b/openfpga/src/fpga_spice/spice_writer_utils.h
@@ -39,7 +39,8 @@ void print_spice_include_netlist(std::fstream& fp,
 void print_spice_comment(std::fstream& fp, 
                          const std::string& comment);
 
-std::string generate_spice_port(const BasicPort& port);
+std::string generate_spice_port(const BasicPort& port,
+                                const bool& omit_pin_zero = false);
 
 void print_spice_subckt_definition(std::fstream& fp, 
                                    const ModuleManager& module_manager, const ModuleId& module_id);

From aa078f079ce6174ead058c99236cf96cfaedc437 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 15:20:19 -0600
Subject: [PATCH 086/148] [FPGA-SPICE] Restructured SPICE netlist writers for
 atom circuits to avoid large cpp files

---
 openfpga/src/fpga_spice/spice_buffer.cpp      | 897 ++++++++++++++++
 openfpga/src/fpga_spice/spice_buffer.h        |  39 +
 .../src/fpga_spice/spice_essential_gates.cpp  | 961 +-----------------
 .../src/fpga_spice/spice_essential_gates.h    |   4 -
 openfpga/src/fpga_spice/spice_submodule.cpp   |   3 +-
 .../fpga_spice/spice_transistor_wrapper.cpp   | 117 +++
 .../src/fpga_spice/spice_transistor_wrapper.h |  25 +
 7 files changed, 1081 insertions(+), 965 deletions(-)
 create mode 100644 openfpga/src/fpga_spice/spice_buffer.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_buffer.h
 create mode 100644 openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_transistor_wrapper.h

diff --git a/openfpga/src/fpga_spice/spice_buffer.cpp b/openfpga/src/fpga_spice/spice_buffer.cpp
new file mode 100644
index 000000000..59fa06d7f
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_buffer.cpp
@@ -0,0 +1,897 @@
+/************************************************
+ * This file includes functions on 
+ * outputting SPICE netlists for inverters and buffers 
+ ***********************************************/
+#include <fstream>
+#include <cmath>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "circuit_library_utils.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_buffer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Generate the SPICE modeling for a power-gated inverter
+ *
+ * This function is created to be shared by inverter and buffer SPICE netlist writer
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   an inverter. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+static 
+int print_spice_powergated_inverter_pmos_modeling(std::fstream& fp,
+                                                  const std::string& trans_name_postfix,
+                                                  const std::string& input_port_name,
+                                                  const std::string& output_port_name,
+                                                  const CircuitLibrary& circuit_lib,
+                                                  const CircuitPortId& enb_port,
+                                                  const TechnologyLibrary& tech_lib,
+                                                  const TechnologyModelId& tech_model,
+                                                  const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Write power-gating transistor pairs using the technology model
+   * Note that for a mulit-bit power gating port, we should cascade the transistors
+   */
+  bool first_enb_pin = true;
+  size_t last_enb_pin;
+  for (const auto& power_gate_pin : circuit_lib.pins(enb_port)) {
+    BasicPort enb_pin(circuit_lib.port_prefix(enb_port), power_gate_pin, power_gate_pin);
+    fp << "Xpmos_powergate_" << trans_name_postfix << "_pin_" << power_gate_pin << " ";
+    /* For the first pin, we should connect it to local VDD*/
+    if (true == first_enb_pin) {
+      fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; 
+      fp << generate_spice_port(enb_pin) << " "; 
+      fp << "LVDD "; 
+      fp << "LVDD "; 
+      first_enb_pin = false;
+    } else {
+      VTR_ASSERT_SAFE(false == first_enb_pin);
+      fp << output_port_name << "_pmos_pg_" << last_enb_pin << " "; 
+      fp << generate_spice_port(enb_pin) << " "; 
+      fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; 
+      fp << "LVDD "; 
+    }
+    fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+    fp << " W=" << std::setprecision(10) << trans_width;
+    fp << "\n";
+
+    /* Cache the last pin*/
+    last_enb_pin = power_gate_pin;
+  }
+
+  /* Write transistor pairs using the technology model */
+  fp << "Xpmos_" << trans_name_postfix << " ";
+  fp << output_port_name << " "; 
+  fp << input_port_name << " "; 
+  fp << output_port_name << "_pmos_pg_" << circuit_lib.pins(enb_port).back() << " "; 
+  fp << "LVDD "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE modeling for the NMOS part of a power-gated inverter
+ *
+ * This function is created to be shared by inverter and buffer SPICE netlist writer
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   an inverter. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+static 
+int print_spice_powergated_inverter_nmos_modeling(std::fstream& fp,
+                                                  const std::string& trans_name_postfix,
+                                                  const std::string& input_port_name,
+                                                  const std::string& output_port_name,
+                                                  const CircuitLibrary& circuit_lib,
+                                                  const CircuitPortId& en_port,
+                                                  const TechnologyLibrary& tech_lib,
+                                                  const TechnologyModelId& tech_model,
+                                                  const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  bool first_en_pin = true;
+  size_t last_en_pin;
+  for (const auto& power_gate_pin : circuit_lib.pins(en_port)) {
+    BasicPort en_pin(circuit_lib.port_prefix(en_port), power_gate_pin, power_gate_pin);
+    fp << "Xnmos_powergate_" << trans_name_postfix << "_pin_" << power_gate_pin << " ";
+    /* For the first pin, we should connect it to local VDD*/
+    if (true == first_en_pin) {
+      fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; 
+      fp << generate_spice_port(en_pin) << " "; 
+      fp << "LGND "; 
+      fp << "LGND "; 
+      first_en_pin = false;
+    } else {
+      VTR_ASSERT_SAFE(false == first_en_pin);
+      fp << output_port_name << "_nmos_pg_" << last_en_pin << " "; 
+      fp << circuit_lib.port_prefix(en_port) << " "; 
+      fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; 
+      fp << "LGND "; 
+    }
+    fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+    fp << " W=" << std::setprecision(10) << trans_width;
+    fp << "\n";
+
+    /* Cache the last pin*/
+    last_en_pin = power_gate_pin;
+  }
+
+  fp << "Xnmos_" << trans_name_postfix << " ";
+  fp << output_port_name << " "; 
+  fp << input_port_name << " "; 
+  fp << output_port_name << " _nmos_pg_" << circuit_lib.pins(en_port).back() << " "; 
+  fp << "LGND "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for a power gated inverter
+ * The Enable signal controlled the power gating
+ *
+ * Note: 
+ * - This function supports multi-bit power gating 
+ *
+ * Schematic
+ *            LVDD
+ *              |
+ *             -
+ *   ENb[0] -o||
+ *             -
+ *              |
+ *             -
+ *   ENb[1] -o||
+ *             -
+ *              |
+ *
+ *            ... <More control signals if available in the port>
+ *
+ *              |
+ *             -
+ *        +-o||
+ *        |    -
+ *        |     |
+ *   in-->+     +--> OUT
+ *        |     |
+ *        |    -
+ *        +--||
+ *             -
+ *
+ *            ... <More control signals if available in the port>
+ *
+ *              |
+ *             -
+ *    EN[1] -||
+ *             -
+ *              |
+ *             -
+ *    EN[0] -||
+ *             -
+ *              |
+ *            LGND
+ *
+ *******************************************************************/
+static 
+int print_spice_powergated_inverter_subckt(std::fstream& fp,
+                                           const ModuleManager& module_manager,
+                                           const ModuleId& module_id,
+                                           const CircuitLibrary& circuit_lib,
+                                           const CircuitModelId& circuit_model,
+                                           const TechnologyLibrary& tech_lib,
+                                           const TechnologyModelId& tech_model) {
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There is only 1 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* If the circuit model is power-gated, we need to find at least one global config_enable signals */
+  VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model));
+  CircuitPortId en_port = find_circuit_model_power_gate_en_port(circuit_lib, circuit_model);
+  CircuitPortId enb_port = find_circuit_model_power_gate_enb_port(circuit_lib, circuit_model);
+  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(en_port));
+  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(enb_port));
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  float total_pmos_width = circuit_lib.buffer_size(circuit_model)
+                         * tech_lib.model_pn_ratio(tech_model)
+                         * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
+  float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
+  for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
+    float curr_bin_width = regular_pmos_bin_width;
+    /* For last bin, we need an irregular width */
+    if ((ibin == num_pmos_bins - 1) 
+       && (0. != last_pmos_bin_width)) {
+      curr_bin_width = last_pmos_bin_width;
+    }
+    status = print_spice_powergated_inverter_pmos_modeling(fp,
+                                                           std::to_string(ibin),
+                                                           circuit_lib.port_prefix(input_ports[0]), 
+                                                           circuit_lib.port_prefix(output_ports[0]), 
+                                                           circuit_lib,
+                                                           enb_port,
+                                                           tech_lib,
+                                                           tech_model,
+                                                           curr_bin_width);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  float total_nmos_width = circuit_lib.buffer_size(circuit_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+  for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+    float curr_bin_width = regular_nmos_bin_width;
+    /* For last bin, we need an irregular width */
+    if ((ibin == num_nmos_bins - 1) 
+       && (0. != last_nmos_bin_width)) {
+      curr_bin_width = last_nmos_bin_width;
+    }
+
+    status = print_spice_powergated_inverter_nmos_modeling(fp,
+                                                           std::to_string(ibin),
+                                                           circuit_lib.port_prefix(input_ports[0]), 
+                                                           circuit_lib.port_prefix(output_ports[0]), 
+                                                           circuit_lib,
+                                                           en_port,
+                                                           tech_lib,
+                                                           tech_model,
+                                                           curr_bin_width);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE modeling for the PMOS part of a regular inverter
+ *
+ * This function is created to be shared by inverter and buffer SPICE netlist writer
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   an inverter. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+static 
+int print_spice_regular_inverter_pmos_modeling(std::fstream& fp,
+                                               const std::string& trans_name_postfix,
+                                               const std::string& input_port_name,
+                                               const std::string& output_port_name,
+                                               const TechnologyLibrary& tech_lib,
+                                               const TechnologyModelId& tech_model,
+                                               const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Write transistor pairs using the technology model */
+  fp << "Xpmos_" << trans_name_postfix << " ";
+  fp << output_port_name << " "; 
+  fp << input_port_name << " "; 
+  fp << "LVDD "; 
+  fp << "LVDD "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE modeling for the NMOS part of a regular inverter
+ *
+ * This function is created to be shared by inverter and buffer SPICE netlist writer
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   an inverter. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+static 
+int print_spice_regular_inverter_nmos_modeling(std::fstream& fp,
+                                               const std::string& trans_name_postfix,
+                                               const std::string& input_port_name,
+                                               const std::string& output_port_name,
+                                               const TechnologyLibrary& tech_lib,
+                                               const TechnologyModelId& tech_model,
+                                               const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  fp << "Xnmos_" << trans_name_postfix << " ";
+  fp << output_port_name << " "; 
+  fp << input_port_name << " "; 
+  fp << "LGND "; 
+  fp << "LGND "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for a regular inverter
+ *
+ * Note: 
+ * - This function does NOT support power-gating
+ *   It should be managed in a separated function
+ *
+ * Schematic
+ *          LVDD
+ *            |
+ *           -
+ *      +-o||
+ *      |    -
+ *      |     |
+ * in-->+     +--> OUT
+ *      |     |
+ *      |    -
+ *      +--||
+ *           -
+ *            |
+ *          LGND
+ *
+ *******************************************************************/
+static 
+int print_spice_regular_inverter_subckt(std::fstream& fp,
+                                        const ModuleManager& module_manager,
+                                        const ModuleId& module_id,
+                                        const CircuitLibrary& circuit_lib,
+                                        const CircuitModelId& circuit_model,
+                                        const TechnologyLibrary& tech_lib,
+                                        const TechnologyModelId& tech_model) {
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There is only 1 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  float total_pmos_width = circuit_lib.buffer_size(circuit_model)
+                           * tech_lib.model_pn_ratio(tech_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
+  float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
+  for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
+    float curr_bin_width = regular_pmos_bin_width;
+    /* For last bin, we need an irregular width */
+    if ((ibin == num_pmos_bins - 1) 
+       && (0. != last_pmos_bin_width)) {
+      curr_bin_width = last_pmos_bin_width;
+    }
+
+    status = print_spice_regular_inverter_pmos_modeling(fp,
+                                                        std::to_string(ibin),
+                                                        circuit_lib.port_prefix(input_ports[0]), 
+                                                        circuit_lib.port_prefix(output_ports[0]), 
+                                                        tech_lib,
+                                                        tech_model,
+                                                        curr_bin_width);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  float total_nmos_width = circuit_lib.buffer_size(circuit_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+
+  for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+    float curr_bin_width = regular_nmos_bin_width;
+    /* For last bin, we need an irregular width */
+    if ((ibin == num_nmos_bins - 1) 
+       && (0. != last_nmos_bin_width)) {
+      curr_bin_width = last_nmos_bin_width;
+    }
+
+    status = print_spice_regular_inverter_nmos_modeling(fp,
+                                                        std::to_string(ibin),
+                                                        circuit_lib.port_prefix(input_ports[0]), 
+                                                        circuit_lib.port_prefix(output_ports[0]), 
+                                                        tech_lib,
+                                                        tech_model,
+                                                        curr_bin_width);
+    if (CMD_EXEC_FATAL_ERROR == status) {
+      return status;
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return status;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for an inverter
+ * Branch on the different circuit topologies
+ *******************************************************************/
+int print_spice_inverter_subckt(std::fstream& fp,
+                                const ModuleManager& module_manager,
+                                const ModuleId& module_id,
+                                const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& circuit_model,
+                                const TechnologyLibrary& tech_lib,
+                                const TechnologyModelId& tech_model) {
+  int status = CMD_EXEC_SUCCESS;
+  if (true == circuit_lib.is_power_gated(circuit_model)) {
+    status = print_spice_powergated_inverter_subckt(fp,
+                                                    module_manager, module_id,
+                                                    circuit_lib, circuit_model,
+                                                    tech_lib, tech_model);
+  } else { 
+    VTR_ASSERT_SAFE(false == circuit_lib.is_power_gated(circuit_model));
+    status = print_spice_regular_inverter_subckt(fp,
+                                                 module_manager, module_id,
+                                                 circuit_lib, circuit_model,
+                                                 tech_lib, tech_model);
+  }
+ 
+  return status;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for a power-gated buffer
+ * which contains at least 2 stages
+ *
+ * Schematic of a multi-stage buffer
+ * 
+ *            LVDD              LVDD
+ *              |                |
+ *             -                -
+ *   ENb[0] -o||     ENb[0] -o||
+ *             -                -
+ *              |                |
+ *             -                -
+ *   ENb[1] -o||     ENb[1] -o||
+ *             -                -
+ *              |                |
+ *
+ *            ... <More control signals if available in the port>
+ *
+ *              |                |
+ *             -                -
+ *        +-o||            +-o||
+ *        |    -           |    -
+ *        |     |          |     |
+ *   in-->+     +-- ... ---+---->+---> out
+ *        |     |          |     |
+ *        |    -           |    -
+ *        +--||            +--||
+ *             -                -
+ *              |                |
+ *
+ *            ... <More control signals if available in the port>
+ *
+ *              |                |
+ *             -                -
+ *   EN[0]  -||       EN[0]  -||
+ *             -                -
+ *              |                |
+ *             -                -
+ *   EN[1]  -||       EN[1]  -||
+ *             -                -
+ *              |                |
+
+ *              |                |
+ *            LGND             LGND
+ *
+ *******************************************************************/
+static 
+int print_spice_powergated_buffer_subckt(std::fstream& fp,
+                                         const ModuleManager& module_manager,
+                                         const ModuleId& module_id,
+                                         const CircuitLibrary& circuit_lib,
+                                         const CircuitModelId& circuit_model,
+                                         const TechnologyLibrary& tech_lib,
+                                         const TechnologyModelId& tech_model) {
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There is only 1 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  /* If the circuit model is power-gated, we need to find at least one global config_enable signals */
+  VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model));
+  CircuitPortId en_port = find_circuit_model_power_gate_en_port(circuit_lib, circuit_model);
+  CircuitPortId enb_port = find_circuit_model_power_gate_enb_port(circuit_lib, circuit_model);
+  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(en_port));
+  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(enb_port));
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Buffers must have >= 2 stages */
+  VTR_ASSERT(2 <= circuit_lib.buffer_num_levels(circuit_model));
+
+  /* Build the array denoting width of inverters per stage */
+  std::vector<float> buffer_widths(circuit_lib.buffer_num_levels(circuit_model), 1);
+  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
+    buffer_widths[level] = circuit_lib.buffer_size(circuit_model)
+                         * std::pow(circuit_lib.buffer_f_per_stage(circuit_model), level);
+  }
+
+  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
+    std::string input_port_name = circuit_lib.port_prefix(input_ports[0]); 
+    std::string output_port_name = circuit_lib.port_prefix(output_ports[0]); 
+
+    /* Special for first stage: output port should be an intermediate node 
+     * Special for rest of stages: input port should be the output of previous stage
+     */
+    if (0 == level) {
+      output_port_name += std::string("_level") + std::to_string(level);
+    } else {
+      VTR_ASSERT(0 < level);
+      input_port_name += std::string("_level") + std::to_string(level - 1);
+    }
+
+    /* Consider use size/bin to compact layout:
+     * Try to size transistors to the max width for each bin
+     * The last bin may not reach the max width 
+     */
+    float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+    float total_pmos_width = buffer_widths[level]
+                             * tech_lib.model_pn_ratio(tech_model)
+                             * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+    int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
+    float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
+
+    for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
+      float curr_bin_width = regular_pmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_pmos_bins - 1) 
+         && (0. != last_pmos_bin_width)) {
+        curr_bin_width = last_pmos_bin_width;
+      }
+
+      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
+
+      status = print_spice_powergated_inverter_pmos_modeling(fp,
+                                                             name_postfix,
+                                                             circuit_lib.port_prefix(input_ports[0]), 
+                                                             circuit_lib.port_prefix(output_ports[0]), 
+                                                             circuit_lib,
+                                                             enb_port,
+                                                             tech_lib,
+                                                             tech_model,
+                                                             curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+
+    /* Consider use size/bin to compact layout:
+     * Try to size transistors to the max width for each bin
+     * The last bin may not reach the max width 
+     */
+    float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+    float total_nmos_width = buffer_widths[level]
+                             * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+    int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+    float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+
+    for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+      float curr_bin_width = regular_nmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_nmos_bins - 1) 
+         && (0. != last_nmos_bin_width)) {
+        curr_bin_width = last_nmos_bin_width;
+      }
+
+      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
+
+      status = print_spice_powergated_inverter_nmos_modeling(fp,
+                                                             name_postfix,
+                                                             circuit_lib.port_prefix(input_ports[0]), 
+                                                             circuit_lib.port_prefix(output_ports[0]), 
+                                                             circuit_lib,
+                                                             en_port,
+                                                             tech_lib,
+                                                             tech_model,
+                                                             curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return CMD_EXEC_SUCCESS;
+}
+
+
+/********************************************************************
+ * Generate the SPICE subckt for a regular buffer
+ * which contains at least 2 stages
+ *
+ * Note: 
+ * - This function does NOT support power-gating
+ *   It should be managed in a separated function
+ *
+ * Schematic of a multi-stage buffer
+ * 
+ *          LVDD              LVDD
+ *            |                |
+ *           -                -
+ *      +-o||            +-o||
+ *      |    -           |    -
+ *      |     |          |     |
+ * in-->+     +-- ... ---+---->+---> out
+ *      |     |          |     |
+ *      |    -           |    -
+ *      +--||            +--||
+ *           -                -
+ *            |                |
+ *          LGND             LGND
+ *
+ *******************************************************************/
+static 
+int print_spice_regular_buffer_subckt(std::fstream& fp,
+                                      const ModuleManager& module_manager,
+                                      const ModuleId& module_id,
+                                      const CircuitLibrary& circuit_lib,
+                                      const CircuitModelId& circuit_model,
+                                      const TechnologyLibrary& tech_lib,
+                                      const TechnologyModelId& tech_model) {
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There is only 1 input port and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Buffers must have >= 2 stages */
+  VTR_ASSERT(2 <= circuit_lib.buffer_num_levels(circuit_model));
+
+  /* Build the array denoting width of inverters per stage */
+  std::vector<float> buffer_widths(circuit_lib.buffer_num_levels(circuit_model), 1);
+  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
+    buffer_widths[level] = circuit_lib.buffer_size(circuit_model)
+                         * std::pow(circuit_lib.buffer_f_per_stage(circuit_model), level);
+  }
+
+  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
+    std::string input_port_name = circuit_lib.port_prefix(input_ports[0]); 
+    std::string output_port_name = circuit_lib.port_prefix(output_ports[0]); 
+
+    /* Special for first stage: output port should be an intermediate node 
+     * Special for rest of stages: input port should be the output of previous stage
+     */
+    if (0 == level) {
+      output_port_name += std::string("_level") + std::to_string(level);
+    } else {
+      VTR_ASSERT(0 < level);
+      input_port_name += std::string("_level") + std::to_string(level - 1);
+    }
+    
+    /* Consider use size/bin to compact layout:
+     * Try to size transistors to the max width for each bin
+     * The last bin may not reach the max width 
+     */
+    float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+    float total_pmos_width = buffer_widths[level]
+                             * tech_lib.model_pn_ratio(tech_model)
+                             * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+    int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
+    float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
+
+    for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
+      float curr_bin_width = regular_pmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_pmos_bins - 1) 
+         && (0. != last_pmos_bin_width)) {
+        curr_bin_width = last_pmos_bin_width;
+      }
+
+      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
+
+      status = print_spice_regular_inverter_pmos_modeling(fp,
+                                                          name_postfix,
+                                                          circuit_lib.port_prefix(input_ports[0]), 
+                                                          circuit_lib.port_prefix(output_ports[0]), 
+                                                          tech_lib,
+                                                          tech_model,
+                                                          curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+
+    /* Consider use size/bin to compact layout:
+     * Try to size transistors to the max width for each bin
+     * The last bin may not reach the max width 
+     */
+    float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+    float total_nmos_width = buffer_widths[level]
+                              * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+    int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+    float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+
+    for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+      float curr_bin_width = regular_nmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_nmos_bins - 1) 
+         && (0. != last_nmos_bin_width)) {
+        curr_bin_width = last_nmos_bin_width;
+      }
+
+      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
+
+      status = print_spice_regular_inverter_nmos_modeling(fp,
+                                                          name_postfix,
+                                                          circuit_lib.port_prefix(input_ports[0]), 
+                                                          circuit_lib.port_prefix(output_ports[0]), 
+                                                          tech_lib,
+                                                          tech_model,
+                                                          curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return status;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for an buffer 
+ * which consists of multiple stage of inverters
+ *******************************************************************/
+int print_spice_buffer_subckt(std::fstream& fp,
+                              const ModuleManager& module_manager,
+                              const ModuleId& module_id,
+                              const CircuitLibrary& circuit_lib,
+                              const CircuitModelId& circuit_model,
+                              const TechnologyLibrary& tech_lib,
+                              const TechnologyModelId& tech_model) {
+  int status = CMD_EXEC_SUCCESS;
+  if (true == circuit_lib.is_power_gated(circuit_model)) {
+    status = print_spice_powergated_buffer_subckt(fp,
+                                                  module_manager, module_id,
+                                                  circuit_lib, circuit_model,
+                                                  tech_lib, tech_model);
+  } else { 
+    VTR_ASSERT_SAFE(false == circuit_lib.is_power_gated(circuit_model));
+    status = print_spice_regular_buffer_subckt(fp,
+                                               module_manager, module_id,
+                                               circuit_lib, circuit_model,
+                                               tech_lib, tech_model);
+  }
+ 
+  return status;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_buffer.h b/openfpga/src/fpga_spice/spice_buffer.h
new file mode 100644
index 000000000..d7019f995
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_buffer.h
@@ -0,0 +1,39 @@
+#ifndef SPICE_BUFFER_H
+#define SPICE_BUFFER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <map>
+#include "module_manager.h"
+#include "circuit_library.h"
+#include "technology_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_inverter_subckt(std::fstream& fp,
+                                const ModuleManager& module_manager,
+                                const ModuleId& module_id,
+                                const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& circuit_model,
+                                const TechnologyLibrary& tech_lib,
+                                const TechnologyModelId& tech_model);
+
+int print_spice_buffer_subckt(std::fstream& fp,
+                              const ModuleManager& module_manager,
+                              const ModuleId& module_id,
+                              const CircuitLibrary& circuit_lib,
+                              const CircuitModelId& circuit_model,
+                              const TechnologyLibrary& tech_lib,
+                              const TechnologyModelId& tech_model);
+
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index 2a916f60e..fe554c328 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -22,972 +22,13 @@
 
 #include "spice_constants.h"
 #include "spice_writer_utils.h"
+#include "spice_buffer.h"
 #include "spice_passgate.h"
 #include "spice_essential_gates.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
-/********************************************************************
- * Print a SPICE model wrapper for a transistor model
- *******************************************************************/
-static 
-int print_spice_transistor_model_wrapper(std::fstream& fp,
-                                         const TechnologyLibrary& tech_lib,
-                                         const TechnologyModelId& model) {
-
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Transistor model followed a fixed port mapping
-   * [X|M]<MODEL_CARD_NAME> <DRAIN> <GATE> <SOURCE> <BULK> 
-   * which is a standard in SPICE modeling
-   * We will output the pmos and nmos transistors wrappers
-   * which are defined in this model
-   */
-  for (int itype = TECH_LIB_TRANSISTOR_PMOS;
-       itype < NUM_TECH_LIB_TRANSISTOR_TYPES;
-       ++itype) {
-    const e_tech_lib_transistor_type& trans_type = static_cast<e_tech_lib_transistor_type>(itype); 
-    fp << ".subckt ";
-    fp << tech_lib.transistor_model_name(model, trans_type) << TRANSISTOR_WRAPPER_POSTFIX; 
-    fp << " drain gate source bulk";
-    fp << " L=" << std::setprecision(10) << tech_lib.transistor_model_chan_length(model, trans_type); 
-    fp << " W=" << std::setprecision(10) << tech_lib.transistor_model_min_width(model, trans_type); 
-    fp << "\n";
-
-    fp << tech_lib.model_ref(model);
-    fp << "1";
-    fp << " drain gate source bulk";
-    fp << " " << tech_lib.transistor_model_name(model, trans_type);
-    fp << " L=L W=W";
-    fp << "\n";
-
-    fp << ".ends";
-    fp << "\n";
-  }
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE netlist for transistors
- *******************************************************************/
-int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
-                                   const TechnologyLibrary& tech_lib,
-                                   const std::string& submodule_dir) {
-  std::string spice_fname = submodule_dir + std::string(TRANSISTORS_SPICE_FILE_NAME);
-
-  std::fstream fp;
-
-  /* Create the file stream */
-  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
-  /* Check if the file stream if valid or not */
-  check_file_stream(spice_fname.c_str(), fp); 
-
-  /* Create file */
-  VTR_LOG("Generating SPICE netlist '%s' for transistors...",
-          spice_fname.c_str()); 
-
-  print_spice_file_header(fp, std::string("Transistor wrappers"));
-
-  /* Iterate over the transistor models */
-  for (const TechnologyModelId& model : tech_lib.models()) {
-    /* Focus on transistor model */
-    if (TECH_LIB_MODEL_TRANSISTOR != tech_lib.model_type(model)) {
-      continue;
-    }
-    /* Write a wrapper for the transistor model */
-    if (CMD_EXEC_SUCCESS == print_spice_transistor_model_wrapper(fp, tech_lib, model)) {
-      return CMD_EXEC_FATAL_ERROR;
-    }
-  } 
-
-  /* Close file handler*/
-  fp.close();
-
-  /* Add fname to the netlist name list */
-  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
-  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
-  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
-
-  VTR_LOG("Done\n");
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE modeling for a power-gated inverter
- *
- * This function is created to be shared by inverter and buffer SPICE netlist writer
- *
- * Note: 
- * - This function does NOT create a file
- *   but requires a file stream created
- * - This function only output SPICE modeling for 
- *   an inverter. Any preprocessing or subckt definition should not be included!
- *******************************************************************/
-static 
-int print_spice_powergated_inverter_pmos_modeling(std::fstream& fp,
-                                                  const std::string& trans_name_postfix,
-                                                  const std::string& input_port_name,
-                                                  const std::string& output_port_name,
-                                                  const CircuitLibrary& circuit_lib,
-                                                  const CircuitPortId& enb_port,
-                                                  const TechnologyLibrary& tech_lib,
-                                                  const TechnologyModelId& tech_model,
-                                                  const float& trans_width) {
-
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Write power-gating transistor pairs using the technology model
-   * Note that for a mulit-bit power gating port, we should cascade the transistors
-   */
-  bool first_enb_pin = true;
-  size_t last_enb_pin;
-  for (const auto& power_gate_pin : circuit_lib.pins(enb_port)) {
-    BasicPort enb_pin(circuit_lib.port_prefix(enb_port), power_gate_pin, power_gate_pin);
-    fp << "Xpmos_powergate_" << trans_name_postfix << "_pin_" << power_gate_pin << " ";
-    /* For the first pin, we should connect it to local VDD*/
-    if (true == first_enb_pin) {
-      fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; 
-      fp << generate_spice_port(enb_pin) << " "; 
-      fp << "LVDD "; 
-      fp << "LVDD "; 
-      first_enb_pin = false;
-    } else {
-      VTR_ASSERT_SAFE(false == first_enb_pin);
-      fp << output_port_name << "_pmos_pg_" << last_enb_pin << " "; 
-      fp << generate_spice_port(enb_pin) << " "; 
-      fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; 
-      fp << "LVDD "; 
-    }
-    fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-    fp << " W=" << std::setprecision(10) << trans_width;
-    fp << "\n";
-
-    /* Cache the last pin*/
-    last_enb_pin = power_gate_pin;
-  }
-
-  /* Write transistor pairs using the technology model */
-  fp << "Xpmos_" << trans_name_postfix << " ";
-  fp << output_port_name << " "; 
-  fp << input_port_name << " "; 
-  fp << output_port_name << "_pmos_pg_" << circuit_lib.pins(enb_port).back() << " "; 
-  fp << "LVDD "; 
-  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-  fp << " W=" << std::setprecision(10) << trans_width;
-  fp << "\n";
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE modeling for the NMOS part of a power-gated inverter
- *
- * This function is created to be shared by inverter and buffer SPICE netlist writer
- *
- * Note: 
- * - This function does NOT create a file
- *   but requires a file stream created
- * - This function only output SPICE modeling for 
- *   an inverter. Any preprocessing or subckt definition should not be included!
- *******************************************************************/
-static 
-int print_spice_powergated_inverter_nmos_modeling(std::fstream& fp,
-                                                  const std::string& trans_name_postfix,
-                                                  const std::string& input_port_name,
-                                                  const std::string& output_port_name,
-                                                  const CircuitLibrary& circuit_lib,
-                                                  const CircuitPortId& en_port,
-                                                  const TechnologyLibrary& tech_lib,
-                                                  const TechnologyModelId& tech_model,
-                                                  const float& trans_width) {
-
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  bool first_en_pin = true;
-  size_t last_en_pin;
-  for (const auto& power_gate_pin : circuit_lib.pins(en_port)) {
-    BasicPort en_pin(circuit_lib.port_prefix(en_port), power_gate_pin, power_gate_pin);
-    fp << "Xnmos_powergate_" << trans_name_postfix << "_pin_" << power_gate_pin << " ";
-    /* For the first pin, we should connect it to local VDD*/
-    if (true == first_en_pin) {
-      fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; 
-      fp << generate_spice_port(en_pin) << " "; 
-      fp << "LGND "; 
-      fp << "LGND "; 
-      first_en_pin = false;
-    } else {
-      VTR_ASSERT_SAFE(false == first_en_pin);
-      fp << output_port_name << "_nmos_pg_" << last_en_pin << " "; 
-      fp << circuit_lib.port_prefix(en_port) << " "; 
-      fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; 
-      fp << "LGND "; 
-    }
-    fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-    fp << " W=" << std::setprecision(10) << trans_width;
-    fp << "\n";
-
-    /* Cache the last pin*/
-    last_en_pin = power_gate_pin;
-  }
-
-  fp << "Xnmos_" << trans_name_postfix << " ";
-  fp << output_port_name << " "; 
-  fp << input_port_name << " "; 
-  fp << output_port_name << " _nmos_pg_" << circuit_lib.pins(en_port).back() << " "; 
-  fp << "LGND "; 
-  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-  fp << " W=" << std::setprecision(10) << trans_width;
-  fp << "\n";
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE subckt for a power gated inverter
- * The Enable signal controlled the power gating
- *
- * Note: 
- * - This function supports multi-bit power gating 
- *
- * Schematic
- *            LVDD
- *              |
- *             -
- *   ENb[0] -o||
- *             -
- *              |
- *             -
- *   ENb[1] -o||
- *             -
- *              |
- *
- *            ... <More control signals if available in the port>
- *
- *              |
- *             -
- *        +-o||
- *        |    -
- *        |     |
- *   in-->+     +--> OUT
- *        |     |
- *        |    -
- *        +--||
- *             -
- *
- *            ... <More control signals if available in the port>
- *
- *              |
- *             -
- *    EN[1] -||
- *             -
- *              |
- *             -
- *    EN[0] -||
- *             -
- *              |
- *            LGND
- *
- *******************************************************************/
-static 
-int print_spice_powergated_inverter_subckt(std::fstream& fp,
-                                           const ModuleManager& module_manager,
-                                           const ModuleId& module_id,
-                                           const CircuitLibrary& circuit_lib,
-                                           const CircuitModelId& circuit_model,
-                                           const TechnologyLibrary& tech_lib,
-                                           const TechnologyModelId& tech_model) {
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Print the inverter subckt definition */
-  print_spice_subckt_definition(fp, module_manager, module_id); 
-
-  /* Find the input and output ports:
-   * we do NOT support global ports here, 
-   * it should be handled in another type of inverter subckt (power-gated)
-   */
-  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
-  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
-
-  /* Make sure:
-   * There is only 1 input port and 1 output port, 
-   * each size of which is 1
-   */
-  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
-  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
-
-  /* If the circuit model is power-gated, we need to find at least one global config_enable signals */
-  VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model));
-  CircuitPortId en_port = find_circuit_model_power_gate_en_port(circuit_lib, circuit_model);
-  CircuitPortId enb_port = find_circuit_model_power_gate_enb_port(circuit_lib, circuit_model);
-  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(en_port));
-  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(enb_port));
-
-  int status = CMD_EXEC_SUCCESS;
-
-  /* Consider use size/bin to compact layout:
-   * Try to size transistors to the max width for each bin
-   * The last bin may not reach the max width 
-   */
-  float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-  float total_pmos_width = circuit_lib.buffer_size(circuit_model)
-                         * tech_lib.model_pn_ratio(tech_model)
-                         * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-  int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
-  float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
-  for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
-    float curr_bin_width = regular_pmos_bin_width;
-    /* For last bin, we need an irregular width */
-    if ((ibin == num_pmos_bins - 1) 
-       && (0. != last_pmos_bin_width)) {
-      curr_bin_width = last_pmos_bin_width;
-    }
-    status = print_spice_powergated_inverter_pmos_modeling(fp,
-                                                           std::to_string(ibin),
-                                                           circuit_lib.port_prefix(input_ports[0]), 
-                                                           circuit_lib.port_prefix(output_ports[0]), 
-                                                           circuit_lib,
-                                                           enb_port,
-                                                           tech_lib,
-                                                           tech_model,
-                                                           curr_bin_width);
-    if (CMD_EXEC_FATAL_ERROR == status) {
-      return status;
-    }
-  }
-
-  /* Consider use size/bin to compact layout:
-   * Try to size transistors to the max width for each bin
-   * The last bin may not reach the max width 
-   */
-  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-  float total_nmos_width = circuit_lib.buffer_size(circuit_model)
-                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
-  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
-  for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
-    float curr_bin_width = regular_nmos_bin_width;
-    /* For last bin, we need an irregular width */
-    if ((ibin == num_nmos_bins - 1) 
-       && (0. != last_nmos_bin_width)) {
-      curr_bin_width = last_nmos_bin_width;
-    }
-
-    status = print_spice_powergated_inverter_nmos_modeling(fp,
-                                                           std::to_string(ibin),
-                                                           circuit_lib.port_prefix(input_ports[0]), 
-                                                           circuit_lib.port_prefix(output_ports[0]), 
-                                                           circuit_lib,
-                                                           en_port,
-                                                           tech_lib,
-                                                           tech_model,
-                                                           curr_bin_width);
-    if (CMD_EXEC_FATAL_ERROR == status) {
-      return status;
-    }
-  }
-
-  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE modeling for the PMOS part of a regular inverter
- *
- * This function is created to be shared by inverter and buffer SPICE netlist writer
- *
- * Note: 
- * - This function does NOT create a file
- *   but requires a file stream created
- * - This function only output SPICE modeling for 
- *   an inverter. Any preprocessing or subckt definition should not be included!
- *******************************************************************/
-static 
-int print_spice_regular_inverter_pmos_modeling(std::fstream& fp,
-                                               const std::string& trans_name_postfix,
-                                               const std::string& input_port_name,
-                                               const std::string& output_port_name,
-                                               const TechnologyLibrary& tech_lib,
-                                               const TechnologyModelId& tech_model,
-                                               const float& trans_width) {
-
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Write transistor pairs using the technology model */
-  fp << "Xpmos_" << trans_name_postfix << " ";
-  fp << output_port_name << " "; 
-  fp << input_port_name << " "; 
-  fp << "LVDD "; 
-  fp << "LVDD "; 
-  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-  fp << " W=" << std::setprecision(10) << trans_width;
-  fp << "\n";
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE modeling for the NMOS part of a regular inverter
- *
- * This function is created to be shared by inverter and buffer SPICE netlist writer
- *
- * Note: 
- * - This function does NOT create a file
- *   but requires a file stream created
- * - This function only output SPICE modeling for 
- *   an inverter. Any preprocessing or subckt definition should not be included!
- *******************************************************************/
-static 
-int print_spice_regular_inverter_nmos_modeling(std::fstream& fp,
-                                               const std::string& trans_name_postfix,
-                                               const std::string& input_port_name,
-                                               const std::string& output_port_name,
-                                               const TechnologyLibrary& tech_lib,
-                                               const TechnologyModelId& tech_model,
-                                               const float& trans_width) {
-
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  fp << "Xnmos_" << trans_name_postfix << " ";
-  fp << output_port_name << " "; 
-  fp << input_port_name << " "; 
-  fp << "LGND "; 
-  fp << "LGND "; 
-  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-  fp << " W=" << std::setprecision(10) << trans_width;
-  fp << "\n";
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE subckt for a regular inverter
- *
- * Note: 
- * - This function does NOT support power-gating
- *   It should be managed in a separated function
- *
- * Schematic
- *          LVDD
- *            |
- *           -
- *      +-o||
- *      |    -
- *      |     |
- * in-->+     +--> OUT
- *      |     |
- *      |    -
- *      +--||
- *           -
- *            |
- *          LGND
- *
- *******************************************************************/
-static 
-int print_spice_regular_inverter_subckt(std::fstream& fp,
-                                        const ModuleManager& module_manager,
-                                        const ModuleId& module_id,
-                                        const CircuitLibrary& circuit_lib,
-                                        const CircuitModelId& circuit_model,
-                                        const TechnologyLibrary& tech_lib,
-                                        const TechnologyModelId& tech_model) {
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Print the inverter subckt definition */
-  print_spice_subckt_definition(fp, module_manager, module_id); 
-
-  /* Find the input and output ports:
-   * we do NOT support global ports here, 
-   * it should be handled in another type of inverter subckt (power-gated)
-   */
-  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
-  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
-
-  /* Make sure:
-   * There is only 1 input port and 1 output port, 
-   * each size of which is 1
-   */
-  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
-  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
-
-  int status = CMD_EXEC_SUCCESS;
-
-  /* Consider use size/bin to compact layout:
-   * Try to size transistors to the max width for each bin
-   * The last bin may not reach the max width 
-   */
-  float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-  float total_pmos_width = circuit_lib.buffer_size(circuit_model)
-                           * tech_lib.model_pn_ratio(tech_model)
-                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-  int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
-  float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
-  for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
-    float curr_bin_width = regular_pmos_bin_width;
-    /* For last bin, we need an irregular width */
-    if ((ibin == num_pmos_bins - 1) 
-       && (0. != last_pmos_bin_width)) {
-      curr_bin_width = last_pmos_bin_width;
-    }
-
-    status = print_spice_regular_inverter_pmos_modeling(fp,
-                                                        std::to_string(ibin),
-                                                        circuit_lib.port_prefix(input_ports[0]), 
-                                                        circuit_lib.port_prefix(output_ports[0]), 
-                                                        tech_lib,
-                                                        tech_model,
-                                                        curr_bin_width);
-    if (CMD_EXEC_FATAL_ERROR == status) {
-      return status;
-    }
-  }
-
-  /* Consider use size/bin to compact layout:
-   * Try to size transistors to the max width for each bin
-   * The last bin may not reach the max width 
-   */
-  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-  float total_nmos_width = circuit_lib.buffer_size(circuit_model)
-                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
-  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
-
-  for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
-    float curr_bin_width = regular_nmos_bin_width;
-    /* For last bin, we need an irregular width */
-    if ((ibin == num_nmos_bins - 1) 
-       && (0. != last_nmos_bin_width)) {
-      curr_bin_width = last_nmos_bin_width;
-    }
-
-    status = print_spice_regular_inverter_nmos_modeling(fp,
-                                                        std::to_string(ibin),
-                                                        circuit_lib.port_prefix(input_ports[0]), 
-                                                        circuit_lib.port_prefix(output_ports[0]), 
-                                                        tech_lib,
-                                                        tech_model,
-                                                        curr_bin_width);
-    if (CMD_EXEC_FATAL_ERROR == status) {
-      return status;
-    }
-  }
-
-  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
-
-  return status;
-}
-
-/********************************************************************
- * Generate the SPICE subckt for an inverter
- * Branch on the different circuit topologies
- *******************************************************************/
-static 
-int print_spice_inverter_subckt(std::fstream& fp,
-                                const ModuleManager& module_manager,
-                                const ModuleId& module_id,
-                                const CircuitLibrary& circuit_lib,
-                                const CircuitModelId& circuit_model,
-                                const TechnologyLibrary& tech_lib,
-                                const TechnologyModelId& tech_model) {
-  int status = CMD_EXEC_SUCCESS;
-  if (true == circuit_lib.is_power_gated(circuit_model)) {
-    status = print_spice_powergated_inverter_subckt(fp,
-                                                    module_manager, module_id,
-                                                    circuit_lib, circuit_model,
-                                                    tech_lib, tech_model);
-  } else { 
-    VTR_ASSERT_SAFE(false == circuit_lib.is_power_gated(circuit_model));
-    status = print_spice_regular_inverter_subckt(fp,
-                                                 module_manager, module_id,
-                                                 circuit_lib, circuit_model,
-                                                 tech_lib, tech_model);
-  }
- 
-  return status;
-}
-
-/********************************************************************
- * Generate the SPICE subckt for a power-gated buffer
- * which contains at least 2 stages
- *
- * Schematic of a multi-stage buffer
- * 
- *            LVDD              LVDD
- *              |                |
- *             -                -
- *   ENb[0] -o||     ENb[0] -o||
- *             -                -
- *              |                |
- *             -                -
- *   ENb[1] -o||     ENb[1] -o||
- *             -                -
- *              |                |
- *
- *            ... <More control signals if available in the port>
- *
- *              |                |
- *             -                -
- *        +-o||            +-o||
- *        |    -           |    -
- *        |     |          |     |
- *   in-->+     +-- ... ---+---->+---> out
- *        |     |          |     |
- *        |    -           |    -
- *        +--||            +--||
- *             -                -
- *              |                |
- *
- *            ... <More control signals if available in the port>
- *
- *              |                |
- *             -                -
- *   EN[0]  -||       EN[0]  -||
- *             -                -
- *              |                |
- *             -                -
- *   EN[1]  -||       EN[1]  -||
- *             -                -
- *              |                |
-
- *              |                |
- *            LGND             LGND
- *
- *******************************************************************/
-static 
-int print_spice_powergated_buffer_subckt(std::fstream& fp,
-                                         const ModuleManager& module_manager,
-                                         const ModuleId& module_id,
-                                         const CircuitLibrary& circuit_lib,
-                                         const CircuitModelId& circuit_model,
-                                         const TechnologyLibrary& tech_lib,
-                                         const TechnologyModelId& tech_model) {
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Print the inverter subckt definition */
-  print_spice_subckt_definition(fp, module_manager, module_id); 
-
-  /* Find the input and output ports:
-   * we do NOT support global ports here, 
-   * it should be handled in another type of inverter subckt (power-gated)
-   */
-  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
-  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
-
-  /* Make sure:
-   * There is only 1 input port and 1 output port, 
-   * each size of which is 1
-   */
-  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
-  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
-
-  /* If the circuit model is power-gated, we need to find at least one global config_enable signals */
-  VTR_ASSERT(true == circuit_lib.is_power_gated(circuit_model));
-  CircuitPortId en_port = find_circuit_model_power_gate_en_port(circuit_lib, circuit_model);
-  CircuitPortId enb_port = find_circuit_model_power_gate_enb_port(circuit_lib, circuit_model);
-  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(en_port));
-  VTR_ASSERT(true == circuit_lib.valid_circuit_port_id(enb_port));
-
-  int status = CMD_EXEC_SUCCESS;
-
-  /* Buffers must have >= 2 stages */
-  VTR_ASSERT(2 <= circuit_lib.buffer_num_levels(circuit_model));
-
-  /* Build the array denoting width of inverters per stage */
-  std::vector<float> buffer_widths(circuit_lib.buffer_num_levels(circuit_model), 1);
-  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
-    buffer_widths[level] = circuit_lib.buffer_size(circuit_model)
-                         * std::pow(circuit_lib.buffer_f_per_stage(circuit_model), level);
-  }
-
-  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
-    std::string input_port_name = circuit_lib.port_prefix(input_ports[0]); 
-    std::string output_port_name = circuit_lib.port_prefix(output_ports[0]); 
-
-    /* Special for first stage: output port should be an intermediate node 
-     * Special for rest of stages: input port should be the output of previous stage
-     */
-    if (0 == level) {
-      output_port_name += std::string("_level") + std::to_string(level);
-    } else {
-      VTR_ASSERT(0 < level);
-      input_port_name += std::string("_level") + std::to_string(level - 1);
-    }
-
-    /* Consider use size/bin to compact layout:
-     * Try to size transistors to the max width for each bin
-     * The last bin may not reach the max width 
-     */
-    float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-    float total_pmos_width = buffer_widths[level]
-                             * tech_lib.model_pn_ratio(tech_model)
-                             * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-    int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
-    float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
-
-    for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
-      float curr_bin_width = regular_pmos_bin_width;
-      /* For last bin, we need an irregular width */
-      if ((ibin == num_pmos_bins - 1) 
-         && (0. != last_pmos_bin_width)) {
-        curr_bin_width = last_pmos_bin_width;
-      }
-
-      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
-
-      status = print_spice_powergated_inverter_pmos_modeling(fp,
-                                                             name_postfix,
-                                                             circuit_lib.port_prefix(input_ports[0]), 
-                                                             circuit_lib.port_prefix(output_ports[0]), 
-                                                             circuit_lib,
-                                                             enb_port,
-                                                             tech_lib,
-                                                             tech_model,
-                                                             curr_bin_width);
-      if (CMD_EXEC_FATAL_ERROR == status) {
-        return status;
-      }
-    }
-
-    /* Consider use size/bin to compact layout:
-     * Try to size transistors to the max width for each bin
-     * The last bin may not reach the max width 
-     */
-    float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-    float total_nmos_width = buffer_widths[level]
-                             * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-    int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
-    float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
-
-    for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
-      float curr_bin_width = regular_nmos_bin_width;
-      /* For last bin, we need an irregular width */
-      if ((ibin == num_nmos_bins - 1) 
-         && (0. != last_nmos_bin_width)) {
-        curr_bin_width = last_nmos_bin_width;
-      }
-
-      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
-
-      status = print_spice_powergated_inverter_nmos_modeling(fp,
-                                                             name_postfix,
-                                                             circuit_lib.port_prefix(input_ports[0]), 
-                                                             circuit_lib.port_prefix(output_ports[0]), 
-                                                             circuit_lib,
-                                                             en_port,
-                                                             tech_lib,
-                                                             tech_model,
-                                                             curr_bin_width);
-      if (CMD_EXEC_FATAL_ERROR == status) {
-        return status;
-      }
-    }
-  }
-
-  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
-
-  return CMD_EXEC_SUCCESS;
-}
-
-
-/********************************************************************
- * Generate the SPICE subckt for a regular buffer
- * which contains at least 2 stages
- *
- * Note: 
- * - This function does NOT support power-gating
- *   It should be managed in a separated function
- *
- * Schematic of a multi-stage buffer
- * 
- *          LVDD              LVDD
- *            |                |
- *           -                -
- *      +-o||            +-o||
- *      |    -           |    -
- *      |     |          |     |
- * in-->+     +-- ... ---+---->+---> out
- *      |     |          |     |
- *      |    -           |    -
- *      +--||            +--||
- *           -                -
- *            |                |
- *          LGND             LGND
- *
- *******************************************************************/
-static 
-int print_spice_regular_buffer_subckt(std::fstream& fp,
-                                      const ModuleManager& module_manager,
-                                      const ModuleId& module_id,
-                                      const CircuitLibrary& circuit_lib,
-                                      const CircuitModelId& circuit_model,
-                                      const TechnologyLibrary& tech_lib,
-                                      const TechnologyModelId& tech_model) {
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Print the inverter subckt definition */
-  print_spice_subckt_definition(fp, module_manager, module_id); 
-
-  /* Find the input and output ports:
-   * we do NOT support global ports here, 
-   * it should be handled in another type of inverter subckt (power-gated)
-   */
-  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
-  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
-
-  /* Make sure:
-   * There is only 1 input port and 1 output port, 
-   * each size of which is 1
-   */
-  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
-  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
-
-  int status = CMD_EXEC_SUCCESS;
-
-  /* Buffers must have >= 2 stages */
-  VTR_ASSERT(2 <= circuit_lib.buffer_num_levels(circuit_model));
-
-  /* Build the array denoting width of inverters per stage */
-  std::vector<float> buffer_widths(circuit_lib.buffer_num_levels(circuit_model), 1);
-  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
-    buffer_widths[level] = circuit_lib.buffer_size(circuit_model)
-                         * std::pow(circuit_lib.buffer_f_per_stage(circuit_model), level);
-  }
-
-  for (size_t level = 0; level < circuit_lib.buffer_num_levels(circuit_model); ++level) {
-    std::string input_port_name = circuit_lib.port_prefix(input_ports[0]); 
-    std::string output_port_name = circuit_lib.port_prefix(output_ports[0]); 
-
-    /* Special for first stage: output port should be an intermediate node 
-     * Special for rest of stages: input port should be the output of previous stage
-     */
-    if (0 == level) {
-      output_port_name += std::string("_level") + std::to_string(level);
-    } else {
-      VTR_ASSERT(0 < level);
-      input_port_name += std::string("_level") + std::to_string(level - 1);
-    }
-    
-    /* Consider use size/bin to compact layout:
-     * Try to size transistors to the max width for each bin
-     * The last bin may not reach the max width 
-     */
-    float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-    float total_pmos_width = buffer_widths[level]
-                             * tech_lib.model_pn_ratio(tech_model)
-                             * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
-    int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
-    float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
-
-    for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
-      float curr_bin_width = regular_pmos_bin_width;
-      /* For last bin, we need an irregular width */
-      if ((ibin == num_pmos_bins - 1) 
-         && (0. != last_pmos_bin_width)) {
-        curr_bin_width = last_pmos_bin_width;
-      }
-
-      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
-
-      status = print_spice_regular_inverter_pmos_modeling(fp,
-                                                          name_postfix,
-                                                          circuit_lib.port_prefix(input_ports[0]), 
-                                                          circuit_lib.port_prefix(output_ports[0]), 
-                                                          tech_lib,
-                                                          tech_model,
-                                                          curr_bin_width);
-      if (CMD_EXEC_FATAL_ERROR == status) {
-        return status;
-      }
-    }
-
-    /* Consider use size/bin to compact layout:
-     * Try to size transistors to the max width for each bin
-     * The last bin may not reach the max width 
-     */
-    float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-    float total_nmos_width = buffer_widths[level]
-                              * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
-    int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
-    float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
-
-    for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
-      float curr_bin_width = regular_nmos_bin_width;
-      /* For last bin, we need an irregular width */
-      if ((ibin == num_nmos_bins - 1) 
-         && (0. != last_nmos_bin_width)) {
-        curr_bin_width = last_nmos_bin_width;
-      }
-
-      std::string name_postfix = std::string("level") + std::to_string(level) + std::string("_bin") + std::to_string(ibin);
-
-      status = print_spice_regular_inverter_nmos_modeling(fp,
-                                                          name_postfix,
-                                                          circuit_lib.port_prefix(input_ports[0]), 
-                                                          circuit_lib.port_prefix(output_ports[0]), 
-                                                          tech_lib,
-                                                          tech_model,
-                                                          curr_bin_width);
-      if (CMD_EXEC_FATAL_ERROR == status) {
-        return status;
-      }
-    }
-  }
-
-  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
-
-  return status;
-}
-
-/********************************************************************
- * Generate the SPICE subckt for an buffer 
- * which consists of multiple stage of inverters
- *******************************************************************/
-static 
-int print_spice_buffer_subckt(std::fstream& fp,
-                              const ModuleManager& module_manager,
-                              const ModuleId& module_id,
-                              const CircuitLibrary& circuit_lib,
-                              const CircuitModelId& circuit_model,
-                              const TechnologyLibrary& tech_lib,
-                              const TechnologyModelId& tech_model) {
-  int status = CMD_EXEC_SUCCESS;
-  if (true == circuit_lib.is_power_gated(circuit_model)) {
-    status = print_spice_powergated_buffer_subckt(fp,
-                                                  module_manager, module_id,
-                                                  circuit_lib, circuit_model,
-                                                  tech_lib, tech_model);
-  } else { 
-    VTR_ASSERT_SAFE(false == circuit_lib.is_power_gated(circuit_model));
-    status = print_spice_regular_buffer_subckt(fp,
-                                               module_manager, module_id,
-                                               circuit_lib, circuit_model,
-                                               tech_lib, tech_model);
-  }
- 
-  return status;
-}
-
 /********************************************************************
  * Generate the SPICE netlist for essential gates:
  * - inverters and their templates
diff --git a/openfpga/src/fpga_spice/spice_essential_gates.h b/openfpga/src/fpga_spice/spice_essential_gates.h
index de9ab3cdb..0fbd1895d 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.h
+++ b/openfpga/src/fpga_spice/spice_essential_gates.h
@@ -18,10 +18,6 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
-                                   const TechnologyLibrary& tech_lib,
-                                   const std::string& submodule_dir);
-
 int print_spice_essential_gates(NetlistManager& netlist_manager,
                                 const ModuleManager& module_manager,
                                 const CircuitLibrary& circuit_lib,
diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp
index 4de678af5..ad72e8515 100644
--- a/openfpga/src/fpga_spice/spice_submodule.cpp
+++ b/openfpga/src/fpga_spice/spice_submodule.cpp
@@ -10,6 +10,7 @@
 /* Headers from openfpgashell library */
 #include "command_exit_codes.h"
 
+#include "spice_transistor_wrapper.h"
 #include "spice_essential_gates.h"
 
 #include "spice_constants.h"
@@ -21,7 +22,7 @@ namespace openfpga {
 /*********************************************************************
  * Top-level function to generate primitive modules:
  * 1. Transistor wrapper
- * 2. TODO: Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
+ * 2. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
  * 3. TODO: Routing multiplexers
  * 4. TODO: Local encoders for routing multiplexers
  * 5. TODO: Wires
diff --git a/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp b/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
new file mode 100644
index 000000000..140d68181
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
@@ -0,0 +1,117 @@
+/************************************************
+ * This file includes functions on 
+ * outputting wrapper SPICE netlists for transistor
+ ***********************************************/
+#include <fstream>
+#include <cmath>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "circuit_library_utils.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_transistor_wrapper.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print a SPICE model wrapper for a transistor model
+ *******************************************************************/
+static 
+int print_spice_transistor_model_wrapper(std::fstream& fp,
+                                         const TechnologyLibrary& tech_lib,
+                                         const TechnologyModelId& model) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Transistor model followed a fixed port mapping
+   * [X|M]<MODEL_CARD_NAME> <DRAIN> <GATE> <SOURCE> <BULK> 
+   * which is a standard in SPICE modeling
+   * We will output the pmos and nmos transistors wrappers
+   * which are defined in this model
+   */
+  for (int itype = TECH_LIB_TRANSISTOR_PMOS;
+       itype < NUM_TECH_LIB_TRANSISTOR_TYPES;
+       ++itype) {
+    const e_tech_lib_transistor_type& trans_type = static_cast<e_tech_lib_transistor_type>(itype); 
+    fp << ".subckt ";
+    fp << tech_lib.transistor_model_name(model, trans_type) << TRANSISTOR_WRAPPER_POSTFIX; 
+    fp << " drain gate source bulk";
+    fp << " L=" << std::setprecision(10) << tech_lib.transistor_model_chan_length(model, trans_type); 
+    fp << " W=" << std::setprecision(10) << tech_lib.transistor_model_min_width(model, trans_type); 
+    fp << "\n";
+
+    fp << tech_lib.model_ref(model);
+    fp << "1";
+    fp << " drain gate source bulk";
+    fp << " " << tech_lib.transistor_model_name(model, trans_type);
+    fp << " L=L W=W";
+    fp << "\n";
+
+    fp << ".ends";
+    fp << "\n";
+  }
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE netlist for transistors
+ *******************************************************************/
+int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
+                                   const TechnologyLibrary& tech_lib,
+                                   const std::string& submodule_dir) {
+  std::string spice_fname = submodule_dir + std::string(TRANSISTORS_SPICE_FILE_NAME);
+
+  std::fstream fp;
+
+  /* Create the file stream */
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+  /* Check if the file stream if valid or not */
+  check_file_stream(spice_fname.c_str(), fp); 
+
+  /* Create file */
+  VTR_LOG("Generating SPICE netlist '%s' for transistors...",
+          spice_fname.c_str()); 
+
+  print_spice_file_header(fp, std::string("Transistor wrappers"));
+
+  /* Iterate over the transistor models */
+  for (const TechnologyModelId& model : tech_lib.models()) {
+    /* Focus on transistor model */
+    if (TECH_LIB_MODEL_TRANSISTOR != tech_lib.model_type(model)) {
+      continue;
+    }
+    /* Write a wrapper for the transistor model */
+    if (CMD_EXEC_SUCCESS == print_spice_transistor_model_wrapper(fp, tech_lib, model)) {
+      return CMD_EXEC_FATAL_ERROR;
+    }
+  } 
+
+  /* Close file handler*/
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
+
+  VTR_LOG("Done\n");
+
+  return CMD_EXEC_SUCCESS;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_transistor_wrapper.h b/openfpga/src/fpga_spice/spice_transistor_wrapper.h
new file mode 100644
index 000000000..86115c5c4
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_transistor_wrapper.h
@@ -0,0 +1,25 @@
+#ifndef SPICE_TRANSISTOR_WRAPPER_H
+#define SPICE_TRANSISTOR_WRAPPER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <map>
+#include "netlist_manager.h"
+#include "technology_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
+                                   const TechnologyLibrary& tech_lib,
+                                   const std::string& submodule_dir);
+
+} /* end namespace openfpga */
+
+#endif

From 3262ceb2769d12d9c19018ddd2fa97293b6fe317 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 15:24:40 -0600
Subject: [PATCH 087/148] [FPGA-SPICE] Bug fix for pass gate transistor sizing

---
 openfpga/src/fpga_spice/spice_passgate.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/openfpga/src/fpga_spice/spice_passgate.cpp b/openfpga/src/fpga_spice/spice_passgate.cpp
index a54956849..20b8ef84b 100644
--- a/openfpga/src/fpga_spice/spice_passgate.cpp
+++ b/openfpga/src/fpga_spice/spice_passgate.cpp
@@ -243,7 +243,6 @@ int print_spice_transmission_gate_subckt(std::fstream& fp,
    */
   float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
   float total_pmos_width = circuit_lib.pass_gate_logic_pmos_size(circuit_model)
-                           * tech_lib.model_pn_ratio(tech_model)
                            * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
   int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
   float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);

From 482d90018f4fcf777603d39313b33cb2068838d1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 15:33:28 -0600
Subject: [PATCH 088/148] [FPGA-SPICE] Create generic PMOS/NMOS instanciation
 function

---
 openfpga/src/fpga_spice/spice_passgate.cpp    | 126 ++++--------------
 .../fpga_spice/spice_transistor_wrapper.cpp   |  73 ++++++++++
 .../src/fpga_spice/spice_transistor_wrapper.h |  18 +++
 3 files changed, 116 insertions(+), 101 deletions(-)

diff --git a/openfpga/src/fpga_spice/spice_passgate.cpp b/openfpga/src/fpga_spice/spice_passgate.cpp
index 20b8ef84b..d26ac5bfb 100644
--- a/openfpga/src/fpga_spice/spice_passgate.cpp
+++ b/openfpga/src/fpga_spice/spice_passgate.cpp
@@ -20,88 +20,12 @@
 
 #include "spice_constants.h"
 #include "spice_writer_utils.h"
+#include "spice_transistor_wrapper.h"
 #include "spice_passgate.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
 
-/********************************************************************
- * Generate the SPICE modeling for the PMOS part of a pass-gate logic
- *
- * This function is created to be shared by pass-transistor and
- * transmission-gate SPICE netlist writer
- *
- * Note: 
- * - This function does NOT create a file
- *   but requires a file stream created
- * - This function only output SPICE modeling for 
- *   a pass-gate. Any preprocessing or subckt definition should not be included!
- *******************************************************************/
-static 
-int print_spice_passgate_pmos_modeling(std::fstream& fp,
-                                       const std::string& trans_name_postfix,
-                                       const std::string& input_port_name,
-                                       const std::string& gate_port_name,
-                                       const std::string& output_port_name,
-                                       const TechnologyLibrary& tech_lib,
-                                       const TechnologyModelId& tech_model,
-                                       const float& trans_width) {
-
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  /* Write transistor pairs using the technology model */
-  fp << "Xpmos_" << trans_name_postfix << " ";
-  fp << input_port_name << " "; 
-  fp << gate_port_name << " "; 
-  fp << output_port_name << " "; 
-  fp << "LVDD "; 
-  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-  fp << " W=" << std::setprecision(10) << trans_width;
-  fp << "\n";
-
-  return CMD_EXEC_SUCCESS;
-}
-
-/********************************************************************
- * Generate the SPICE modeling for the NMOS part of a pass-gate logic
- *
- * This function is created to be shared by pass-transistor and
- * transmission-gate SPICE netlist writer
- *
- * Note: 
- * - This function does NOT create a file
- *   but requires a file stream created
- * - This function only output SPICE modeling for 
- *   a pass-gate. Any preprocessing or subckt definition should not be included!
- *******************************************************************/
-static 
-int print_spice_passgate_nmos_modeling(std::fstream& fp,
-                                       const std::string& trans_name_postfix,
-                                       const std::string& input_port_name,
-                                       const std::string& gate_port_name,
-                                       const std::string& output_port_name,
-                                       const TechnologyLibrary& tech_lib,
-                                       const TechnologyModelId& tech_model,
-                                       const float& trans_width) {
-
-  if (false == valid_file_stream(fp)) {
-    return CMD_EXEC_FATAL_ERROR;
-  }
-
-  fp << "Xnmos_" << trans_name_postfix << " ";
-  fp << input_port_name << " "; 
-  fp << gate_port_name << " "; 
-  fp << output_port_name << " "; 
-  fp << "LGND "; 
-  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
-  fp << " W=" << std::setprecision(10) << trans_width;
-  fp << "\n";
-
-  return CMD_EXEC_SUCCESS;
-}
-
 /********************************************************************
  * Generate the SPICE subckt for a pass-transistor
  *
@@ -167,14 +91,14 @@ int print_spice_pass_transistor_subckt(std::fstream& fp,
       curr_bin_width = last_nmos_bin_width;
     }
 
-    status = print_spice_passgate_nmos_modeling(fp,
-                                                std::to_string(ibin),
-                                                circuit_lib.port_prefix(input_ports[0]), 
-                                                circuit_lib.port_prefix(input_ports[1]), 
-                                                circuit_lib.port_prefix(output_ports[0]), 
-                                                tech_lib,
-                                                tech_model,
-                                                curr_bin_width);
+    status = print_spice_generic_nmos_modeling(fp,
+                                               std::to_string(ibin),
+                                               circuit_lib.port_prefix(input_ports[0]), 
+                                               circuit_lib.port_prefix(input_ports[1]), 
+                                               circuit_lib.port_prefix(output_ports[0]), 
+                                               tech_lib,
+                                               tech_model,
+                                               curr_bin_width);
     if (CMD_EXEC_FATAL_ERROR == status) {
       return status;
     }
@@ -254,14 +178,14 @@ int print_spice_transmission_gate_subckt(std::fstream& fp,
       curr_bin_width = last_pmos_bin_width;
     }
 
-    status = print_spice_passgate_pmos_modeling(fp,
-                                                std::to_string(ibin),
-                                                circuit_lib.port_prefix(input_ports[0]), 
-                                                circuit_lib.port_prefix(input_ports[2]), 
-                                                circuit_lib.port_prefix(output_ports[0]), 
-                                                tech_lib,
-                                                tech_model,
-                                                curr_bin_width);
+    status = print_spice_generic_pmos_modeling(fp,
+                                               std::to_string(ibin),
+                                               circuit_lib.port_prefix(input_ports[0]), 
+                                               circuit_lib.port_prefix(input_ports[2]), 
+                                               circuit_lib.port_prefix(output_ports[0]), 
+                                               tech_lib,
+                                               tech_model,
+                                               curr_bin_width);
     if (CMD_EXEC_FATAL_ERROR == status) {
       return status;
     }
@@ -285,14 +209,14 @@ int print_spice_transmission_gate_subckt(std::fstream& fp,
       curr_bin_width = last_nmos_bin_width;
     }
 
-    status = print_spice_passgate_nmos_modeling(fp,
-                                                std::to_string(ibin),
-                                                circuit_lib.port_prefix(input_ports[0]), 
-                                                circuit_lib.port_prefix(input_ports[1]), 
-                                                circuit_lib.port_prefix(output_ports[0]), 
-                                                tech_lib,
-                                                tech_model,
-                                                curr_bin_width);
+    status = print_spice_generic_nmos_modeling(fp,
+                                               std::to_string(ibin),
+                                               circuit_lib.port_prefix(input_ports[0]), 
+                                               circuit_lib.port_prefix(input_ports[1]), 
+                                               circuit_lib.port_prefix(output_ports[0]), 
+                                               tech_lib,
+                                               tech_model,
+                                               curr_bin_width);
     if (CMD_EXEC_FATAL_ERROR == status) {
       return status;
     }
diff --git a/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp b/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
index 140d68181..882d43f4d 100644
--- a/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
+++ b/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
@@ -114,4 +114,77 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
   return CMD_EXEC_SUCCESS;
 }
 
+/********************************************************************
+ * Generate the SPICE modeling for the PMOS part of a logic gate
+ *
+ * This function is created to be shared by pass-transistor and
+ * transmission-gate SPICE netlist writer
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   a PMOS. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+int print_spice_generic_pmos_modeling(std::fstream& fp,
+                                      const std::string& trans_name_postfix,
+                                      const std::string& input_port_name,
+                                      const std::string& gate_port_name,
+                                      const std::string& output_port_name,
+                                      const TechnologyLibrary& tech_lib,
+                                      const TechnologyModelId& tech_model,
+                                      const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Write transistor pairs using the technology model */
+  fp << "Xpmos_" << trans_name_postfix << " ";
+  fp << input_port_name << " "; 
+  fp << gate_port_name << " "; 
+  fp << output_port_name << " "; 
+  fp << "LVDD "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Generate the SPICE modeling for the NMOS part of a logic gate
+ *
+ * Note: 
+ * - This function does NOT create a file
+ *   but requires a file stream created
+ * - This function only output SPICE modeling for 
+ *   a NMOS. Any preprocessing or subckt definition should not be included!
+ *******************************************************************/
+int print_spice_generic_nmos_modeling(std::fstream& fp,
+                                      const std::string& trans_name_postfix,
+                                      const std::string& input_port_name,
+                                      const std::string& gate_port_name,
+                                      const std::string& output_port_name,
+                                      const TechnologyLibrary& tech_lib,
+                                      const TechnologyModelId& tech_model,
+                                      const float& trans_width) {
+
+  if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  fp << "Xnmos_" << trans_name_postfix << " ";
+  fp << input_port_name << " "; 
+  fp << gate_port_name << " "; 
+  fp << output_port_name << " "; 
+  fp << "LGND "; 
+  fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
+  fp << " W=" << std::setprecision(10) << trans_width;
+  fp << "\n";
+
+  return CMD_EXEC_SUCCESS;
+}
+
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_transistor_wrapper.h b/openfpga/src/fpga_spice/spice_transistor_wrapper.h
index 86115c5c4..7b3bef199 100644
--- a/openfpga/src/fpga_spice/spice_transistor_wrapper.h
+++ b/openfpga/src/fpga_spice/spice_transistor_wrapper.h
@@ -20,6 +20,24 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
                                    const TechnologyLibrary& tech_lib,
                                    const std::string& submodule_dir);
 
+int print_spice_generic_pmos_modeling(std::fstream& fp,
+                                      const std::string& trans_name_postfix,
+                                      const std::string& input_port_name,
+                                      const std::string& gate_port_name,
+                                      const std::string& output_port_name,
+                                      const TechnologyLibrary& tech_lib,
+                                      const TechnologyModelId& tech_model,
+                                      const float& trans_width);
+
+int print_spice_generic_nmos_modeling(std::fstream& fp,
+                                      const std::string& trans_name_postfix,
+                                      const std::string& input_port_name,
+                                      const std::string& gate_port_name,
+                                      const std::string& output_port_name,
+                                      const TechnologyLibrary& tech_lib,
+                                      const TechnologyModelId& tech_model,
+                                      const float& trans_width);
+
 } /* end namespace openfpga */
 
 #endif

From e102e30d197578f77089a269c41793889dac8eba Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 16:20:21 -0600
Subject: [PATCH 089/148] [FPGA-SPICE] Add support for AND/OR logic gate

---
 openfpga/src/fpga_spice/spice_buffer.cpp      |  24 +-
 openfpga/src/fpga_spice/spice_constants.h     |   3 +
 .../src/fpga_spice/spice_essential_gates.cpp  |  26 +-
 openfpga/src/fpga_spice/spice_logic_gate.cpp  | 346 ++++++++++++++++++
 openfpga/src/fpga_spice/spice_logic_gate.h    |  38 ++
 openfpga/src/fpga_spice/spice_passgate.cpp    |   2 +-
 .../fpga_spice/spice_transistor_wrapper.cpp   |   6 +-
 7 files changed, 428 insertions(+), 17 deletions(-)
 create mode 100644 openfpga/src/fpga_spice/spice_logic_gate.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_logic_gate.h

diff --git a/openfpga/src/fpga_spice/spice_buffer.cpp b/openfpga/src/fpga_spice/spice_buffer.cpp
index 59fa06d7f..824e3debc 100644
--- a/openfpga/src/fpga_spice/spice_buffer.cpp
+++ b/openfpga/src/fpga_spice/spice_buffer.cpp
@@ -63,15 +63,15 @@ int print_spice_powergated_inverter_pmos_modeling(std::fstream& fp,
     if (true == first_enb_pin) {
       fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; 
       fp << generate_spice_port(enb_pin) << " "; 
-      fp << "LVDD "; 
-      fp << "LVDD "; 
+      fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
+      fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
       first_enb_pin = false;
     } else {
       VTR_ASSERT_SAFE(false == first_enb_pin);
       fp << output_port_name << "_pmos_pg_" << last_enb_pin << " "; 
       fp << generate_spice_port(enb_pin) << " "; 
       fp << output_port_name << "_pmos_pg_" << power_gate_pin << " "; 
-      fp << "LVDD "; 
+      fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
     }
     fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
     fp << " W=" << std::setprecision(10) << trans_width;
@@ -86,7 +86,7 @@ int print_spice_powergated_inverter_pmos_modeling(std::fstream& fp,
   fp << output_port_name << " "; 
   fp << input_port_name << " "; 
   fp << output_port_name << "_pmos_pg_" << circuit_lib.pins(enb_port).back() << " "; 
-  fp << "LVDD "; 
+  fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
   fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
   fp << " W=" << std::setprecision(10) << trans_width;
   fp << "\n";
@@ -129,15 +129,15 @@ int print_spice_powergated_inverter_nmos_modeling(std::fstream& fp,
     if (true == first_en_pin) {
       fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; 
       fp << generate_spice_port(en_pin) << " "; 
-      fp << "LGND "; 
-      fp << "LGND "; 
+      fp << SPICE_SUBCKT_GND_PORT_NAME << " "; 
+      fp << SPICE_SUBCKT_GND_PORT_NAME << " "; 
       first_en_pin = false;
     } else {
       VTR_ASSERT_SAFE(false == first_en_pin);
       fp << output_port_name << "_nmos_pg_" << last_en_pin << " "; 
       fp << circuit_lib.port_prefix(en_port) << " "; 
       fp << output_port_name << "_nmos_pg_" << power_gate_pin << " "; 
-      fp << "LGND "; 
+      fp << SPICE_SUBCKT_GND_PORT_NAME << " "; 
     }
     fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
     fp << " W=" << std::setprecision(10) << trans_width;
@@ -151,7 +151,7 @@ int print_spice_powergated_inverter_nmos_modeling(std::fstream& fp,
   fp << output_port_name << " "; 
   fp << input_port_name << " "; 
   fp << output_port_name << " _nmos_pg_" << circuit_lib.pins(en_port).back() << " "; 
-  fp << "LGND "; 
+  fp << SPICE_SUBCKT_GND_PORT_NAME << " "; 
   fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
   fp << " W=" << std::setprecision(10) << trans_width;
   fp << "\n";
@@ -338,8 +338,8 @@ int print_spice_regular_inverter_pmos_modeling(std::fstream& fp,
   fp << "Xpmos_" << trans_name_postfix << " ";
   fp << output_port_name << " "; 
   fp << input_port_name << " "; 
-  fp << "LVDD "; 
-  fp << "LVDD "; 
+  fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
+  fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
   fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
   fp << " W=" << std::setprecision(10) << trans_width;
   fp << "\n";
@@ -374,8 +374,8 @@ int print_spice_regular_inverter_nmos_modeling(std::fstream& fp,
   fp << "Xnmos_" << trans_name_postfix << " ";
   fp << output_port_name << " "; 
   fp << input_port_name << " "; 
-  fp << "LGND "; 
-  fp << "LGND "; 
+  fp << SPICE_SUBCKT_GND_PORT_NAME << " "; 
+  fp << SPICE_SUBCKT_GND_PORT_NAME << " "; 
   fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
   fp << " W=" << std::setprecision(10) << trans_width;
   fp << "\n";
diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 770e1b595..80a13af36 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -10,4 +10,7 @@ constexpr char* TRANSISTOR_WRAPPER_POSTFIX = "_wrapper";
 constexpr char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
 constexpr char* ESSENTIALS_SPICE_FILE_NAME = "inv_buf_passgate.sp";
 
+constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
+constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
+
 #endif
diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index fe554c328..6cad5c6f6 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -24,6 +24,7 @@
 #include "spice_writer_utils.h"
 #include "spice_buffer.h"
 #include "spice_passgate.h"
+#include "spice_logic_gate.h"
 #include "spice_essential_gates.h"
 
 /* begin namespace openfpga */
@@ -112,7 +113,7 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       continue;
     }
 
-    /* Now branch on netlist writing: for inverter/buffers */
+    /* Now branch on netlist writing: for pass-gate logic */
     if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
       status = print_spice_passgate_subckt(fp,
                                            module_manager, module_id,
@@ -126,6 +127,29 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       /* Finish, go to the next */
       continue;
     }
+
+    /* Now branch on netlist writing: for logic gate */
+    if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
+      if (CIRCUIT_MODEL_GATE_AND == circuit_lib.gate_type(circuit_model)) {
+        status = print_spice_and_gate_subckt(fp,
+                                             module_manager, module_id,
+                                             circuit_lib, circuit_model,
+                                             tech_lib, tech_model);
+      } else if (CIRCUIT_MODEL_GATE_OR == circuit_lib.gate_type(circuit_model)) {
+        status = print_spice_or_gate_subckt(fp,
+                                            module_manager, module_id,
+                                            circuit_lib, circuit_model,
+                                            tech_lib, tech_model);
+      }
+
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        break;
+      }
+
+      /* Finish, go to the next */
+      continue;
+    }
+
   } 
 
   /* Close file handler*/
diff --git a/openfpga/src/fpga_spice/spice_logic_gate.cpp b/openfpga/src/fpga_spice/spice_logic_gate.cpp
new file mode 100644
index 000000000..6eba3da7a
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_logic_gate.cpp
@@ -0,0 +1,346 @@
+/************************************************
+ * This file includes functions on 
+ * outputting SPICE netlists for logic gates:
+ * - N-input AND gate
+ * - N-input OR gate
+ ***********************************************/
+#include <fstream>
+#include <cmath>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "circuit_library_utils.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_transistor_wrapper.h"
+#include "spice_logic_gate.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Generate the SPICE subckt for a N-input AND gate
+ *
+ * Schematic
+ *
+ *           VDD        VDD                 VDD
+ *            |          |                   |
+ *           -          -                   -
+ *   in0 -o||   in1 -o||    ... in[N-1] -o||
+ *           -          -                   -
+ *            |          |                   |
+ *            +----+-----+- ... -------------+
+ *                 |
+ *                -
+ *         in0 -||
+ *                -
+ *                 |
+ *                -
+ *         in1 -||
+ *                -
+ *                 |
+ *                ...
+ *                 |
+ *                -
+ *     in[N-1] -||
+ *                -
+ *                 |
+ *                GND
+ *******************************************************************/
+int print_spice_and_gate_subckt(std::fstream& fp,
+                                const ModuleManager& module_manager,
+                                const ModuleId& module_id,
+                                const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& circuit_model,
+                                const TechnologyLibrary& tech_lib,
+                                const TechnologyModelId& tech_model) {
+
+ if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There are at least 2 input ports and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT(2 <= input_ports.size());
+  for (const auto& input_port : input_ports) {
+     VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+  }
+
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  float total_pmos_width = 1. /* TODO: allow users to define gate strength */
+                           * tech_lib.model_pn_ratio(tech_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
+  float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
+
+
+  /* Output the PMOS network */
+  for (const auto& input_port : input_ports) {
+    for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
+      float curr_bin_width = regular_pmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_pmos_bins - 1) 
+         && (0. != last_pmos_bin_width)) {
+        curr_bin_width = last_pmos_bin_width;
+      }
+
+      status = print_spice_generic_pmos_modeling(fp,
+                                                 std::to_string(ibin),
+                                                 std::string(SPICE_SUBCKT_VDD_PORT_NAME), 
+                                                 circuit_lib.port_prefix(input_port), 
+                                                 circuit_lib.port_prefix(output_ports[0]), 
+                                                 tech_lib,
+                                                 tech_model,
+                                                 curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+  }
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  float total_nmos_width = 1. /* TODO: allow users to define gate strength */
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+
+  /* Output the NMOS network */
+  for (size_t input_id = 0; input_id < input_ports.size(); ++input_id) {
+    for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+      float curr_bin_width = regular_nmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_nmos_bins - 1) 
+         && (0. != last_nmos_bin_width)) {
+        curr_bin_width = last_nmos_bin_width;
+      }
+
+      /* Depending on the input id, we assign different port names to source/drain */
+      std::string source_port_name;
+      std::string drain_port_name;
+
+      if (0 == input_id) {
+        /* First transistor should connect to the output port and an internal node */
+        source_port_name = circuit_lib.port_prefix(output_ports[0]);
+        drain_port_name = std::string("internal_node") + std::to_string(input_id);
+      } else if (input_id == input_ports.size() - 1) {
+        /* Last transistor should connect to an internal node and GND */
+        source_port_name = std::string("internal_node") + std::to_string(input_id - 1);
+        drain_port_name = std::string(SPICE_SUBCKT_GND_PORT_NAME);
+      } else {
+        /* Other transistors should connect to two internal nodes */ 
+        source_port_name = std::string("internal_node") + std::to_string(input_id - 1);
+        drain_port_name = std::string("internal_node") + std::to_string(input_id);
+      }
+
+      status = print_spice_generic_nmos_modeling(fp,
+                                                 std::to_string(ibin),
+                                                 source_port_name, 
+                                                 circuit_lib.port_prefix(input_ports[input_id]), 
+                                                 drain_port_name, 
+                                                 tech_lib,
+                                                 tech_model,
+                                                 curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return status;
+}
+
+/********************************************************************
+ * Generate the SPICE subckt for a N-input OR gate
+ *
+ * Schematic
+ *
+ *
+ *                VDD
+ *                 |
+ *                -
+ *        in0 -o||
+ *                -
+ *                 |
+ *                -
+ *        in1 -o||
+ *                -
+ *                 |
+ *                ...
+ *                 |
+ *                -
+ *    in[N-1] -o||
+ *                -
+ *                 |
+ *            +----+-----+- ... -------------+
+ *            |          |                   |
+ *           -          -                   -
+ *    in0 -||    in1 -||    ...  in[N-1] -||
+ *           -          -                   -
+ *            |          |                   |
+ *           GND        GND                 GND
+ *******************************************************************/
+int print_spice_or_gate_subckt(std::fstream& fp,
+                               const ModuleManager& module_manager,
+                               const ModuleId& module_id,
+                               const CircuitLibrary& circuit_lib,
+                               const CircuitModelId& circuit_model,
+                               const TechnologyLibrary& tech_lib,
+                               const TechnologyModelId& tech_model) {
+
+ if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There are at least 2 input ports and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT(2 <= input_ports.size());
+  for (const auto& input_port : input_ports) {
+     VTR_ASSERT(1 == circuit_lib.port_size(input_port));
+  }
+
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  float total_pmos_width = 1. /* TODO: allow users to define gate strength */
+                           * tech_lib.model_pn_ratio(tech_model)
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
+  int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
+  float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);
+
+
+  /* Output the PMOS network */
+  for (size_t input_id = 0; input_id < input_ports.size(); ++input_id) {
+    for (int ibin = 0; ibin < num_pmos_bins; ++ibin) { 
+      float curr_bin_width = regular_pmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_pmos_bins - 1) 
+         && (0. != last_pmos_bin_width)) {
+        curr_bin_width = last_pmos_bin_width;
+      }
+
+      /* Depending on the input id, we assign different port names to source/drain */
+      std::string source_port_name;
+      std::string drain_port_name;
+
+      if (0 == input_id) {
+        /* First transistor should connect to the output port and an internal node */
+        source_port_name = circuit_lib.port_prefix(output_ports[0]);
+        drain_port_name = std::string("internal_node") + std::to_string(input_id);
+      } else if (input_id == input_ports.size() - 1) {
+        /* Last transistor should connect to an internal node and GND */
+        source_port_name = std::string("internal_node") + std::to_string(input_id - 1);
+        drain_port_name = std::string(SPICE_SUBCKT_VDD_PORT_NAME);
+      } else {
+        /* Other transistors should connect to two internal nodes */ 
+        source_port_name = std::string("internal_node") + std::to_string(input_id - 1);
+        drain_port_name = std::string("internal_node") + std::to_string(input_id);
+      }
+
+      status = print_spice_generic_pmos_modeling(fp,
+                                                 std::to_string(ibin),
+                                                 source_port_name, 
+                                                 circuit_lib.port_prefix(input_ports[input_id]), 
+                                                 drain_port_name, 
+                                                 tech_lib,
+                                                 tech_model,
+                                                 curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+  }
+
+  /* Consider use size/bin to compact layout:
+   * Try to size transistors to the max width for each bin
+   * The last bin may not reach the max width 
+   */
+  float regular_nmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  float total_nmos_width = 1. /* TODO: allow users to define gate strength */
+                           * tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_NMOS);
+  int num_nmos_bins = std::ceil(total_nmos_width / regular_nmos_bin_width);
+  float last_nmos_bin_width = std::fmod(total_nmos_width, regular_nmos_bin_width);
+
+  /* Output the NMOS network */
+  for (const auto& input_port : input_ports) {
+    for (int ibin = 0; ibin < num_nmos_bins; ++ibin) { 
+      float curr_bin_width = regular_nmos_bin_width;
+      /* For last bin, we need an irregular width */
+      if ((ibin == num_nmos_bins - 1) 
+         && (0. != last_nmos_bin_width)) {
+        curr_bin_width = last_nmos_bin_width;
+      }
+
+      status = print_spice_generic_nmos_modeling(fp,
+                                                 std::to_string(ibin),
+                                                 circuit_lib.port_prefix(output_ports[0]), 
+                                                 circuit_lib.port_prefix(input_port), 
+                                                 std::string(SPICE_SUBCKT_GND_PORT_NAME), 
+                                                 tech_lib,
+                                                 tech_model,
+                                                 curr_bin_width);
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        return status;
+      }
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return status;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_logic_gate.h b/openfpga/src/fpga_spice/spice_logic_gate.h
new file mode 100644
index 000000000..4a72c803f
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_logic_gate.h
@@ -0,0 +1,38 @@
+#ifndef SPICE_LOGIC_GATE_H
+#define SPICE_LOGIC_GATE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <map>
+#include "module_manager.h"
+#include "circuit_library.h"
+#include "technology_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_and_gate_subckt(std::fstream& fp,
+                                const ModuleManager& module_manager,
+                                const ModuleId& module_id,
+                                const CircuitLibrary& circuit_lib,
+                                const CircuitModelId& circuit_model,
+                                const TechnologyLibrary& tech_lib,
+                                const TechnologyModelId& tech_model);
+
+int print_spice_or_gate_subckt(std::fstream& fp,
+                               const ModuleManager& module_manager,
+                               const ModuleId& module_id,
+                               const CircuitLibrary& circuit_lib,
+                               const CircuitModelId& circuit_model,
+                               const TechnologyLibrary& tech_lib,
+                               const TechnologyModelId& tech_model);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_spice/spice_passgate.cpp b/openfpga/src/fpga_spice/spice_passgate.cpp
index d26ac5bfb..cf3702ba7 100644
--- a/openfpga/src/fpga_spice/spice_passgate.cpp
+++ b/openfpga/src/fpga_spice/spice_passgate.cpp
@@ -248,7 +248,7 @@ int print_spice_passgate_subckt(std::fstream& fp,
                                                 module_manager, module_id,
                                                 circuit_lib, circuit_model,
                                                 tech_lib, tech_model);
-  } else if (CIRCUIT_MODEL_PASS_GATE_TRANSMISSION == circuit_lib.is_power_gated(circuit_model)) {
+  } else if (CIRCUIT_MODEL_PASS_GATE_TRANSMISSION == circuit_lib.pass_gate_logic_type(circuit_model)) {
     status = print_spice_transmission_gate_subckt(fp,
                                                   module_manager, module_id,
                                                   circuit_lib, circuit_model,
diff --git a/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp b/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
index 882d43f4d..6a90b0c96 100644
--- a/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
+++ b/openfpga/src/fpga_spice/spice_transistor_wrapper.cpp
@@ -96,7 +96,7 @@ int print_spice_transistor_wrapper(NetlistManager& netlist_manager,
       continue;
     }
     /* Write a wrapper for the transistor model */
-    if (CMD_EXEC_SUCCESS == print_spice_transistor_model_wrapper(fp, tech_lib, model)) {
+    if (CMD_EXEC_SUCCESS != print_spice_transistor_model_wrapper(fp, tech_lib, model)) {
       return CMD_EXEC_FATAL_ERROR;
     }
   } 
@@ -144,7 +144,7 @@ int print_spice_generic_pmos_modeling(std::fstream& fp,
   fp << input_port_name << " "; 
   fp << gate_port_name << " "; 
   fp << output_port_name << " "; 
-  fp << "LVDD "; 
+  fp << SPICE_SUBCKT_VDD_PORT_NAME << " "; 
   fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_PMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
   fp << " W=" << std::setprecision(10) << trans_width;
   fp << "\n";
@@ -178,7 +178,7 @@ int print_spice_generic_nmos_modeling(std::fstream& fp,
   fp << input_port_name << " "; 
   fp << gate_port_name << " "; 
   fp << output_port_name << " "; 
-  fp << "LGND "; 
+  fp << SPICE_SUBCKT_GND_PORT_NAME << " "; 
   fp << tech_lib.transistor_model_name(tech_model, TECH_LIB_TRANSISTOR_NMOS) << TRANSISTOR_WRAPPER_POSTFIX; 
   fp << " W=" << std::setprecision(10) << trans_width;
   fp << "\n";

From 26a0a769eabe06658c576d601b91c5e7cb3bdd41 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 16:45:26 -0600
Subject: [PATCH 090/148] [FPGA-SPICE] Split essential gate SPICE netlists into
 separated files

---
 openfpga/src/fpga_spice/spice_constants.h     |  1 -
 .../src/fpga_spice/spice_essential_gates.cpp  | 78 +++++++++++--------
 2 files changed, 44 insertions(+), 35 deletions(-)

diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 80a13af36..48482d703 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -8,7 +8,6 @@ constexpr char* SPICE_NETLIST_FILE_POSTFIX = ".sp";
 constexpr char* TRANSISTOR_WRAPPER_POSTFIX = "_wrapper";
 
 constexpr char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
-constexpr char* ESSENTIALS_SPICE_FILE_NAME = "inv_buf_passgate.sp";
 
 constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
 constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index 6cad5c6f6..780a31776 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -43,21 +43,6 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
                                 const TechnologyLibrary& tech_lib,
                                 const std::map<CircuitModelId, TechnologyModelId>& circuit_tech_binding,
                                 const std::string& submodule_dir) {
-  std::string spice_fname = submodule_dir + std::string(ESSENTIALS_SPICE_FILE_NAME);
-
-  std::fstream fp;
-
-  /* Create the file stream */
-  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
-  /* Check if the file stream if valid or not */
-  check_file_stream(spice_fname.c_str(), fp); 
-
-  /* Create file */
-  VTR_LOG("Generating SPICE netlist '%s' for essential gates...",
-          spice_fname.c_str()); 
-
-  print_spice_file_header(fp, std::string("Essential gates"));
-
   int status = CMD_EXEC_SUCCESS;
 
   /* Iterate over the circuit models */
@@ -89,6 +74,26 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       VTR_ASSERT(TECH_LIB_MODEL_TRANSISTOR == tech_lib.model_type(tech_model));
     }
 
+    /* Create file stream */
+    std::string spice_fname = submodule_dir + circuit_lib.model_name(circuit_model);
+  
+    std::fstream fp;
+  
+    /* Create the file stream */
+    fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+    /* Check if the file stream if valid or not */
+    check_file_stream(spice_fname.c_str(), fp); 
+  
+    /* Create file */
+    VTR_LOG("Generating SPICE netlist '%s' for circuit model '%s'...",
+            spice_fname.c_str(),
+            circuit_lib.model_name(circuit_model).c_str());
+  
+    print_spice_file_header(fp, circuit_lib.model_name(circuit_model));
+
+    /* A flag to record if any logic has been filled to the netlist */
+    bool netlist_filled = false;
+
     /* Now branch on netlist writing: for inverter/buffers */
     if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
       if (CIRCUIT_MODEL_BUF_INV == circuit_lib.buffer_type(circuit_model)) {
@@ -97,20 +102,19 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
                                              module_manager, module_id,
                                              circuit_lib, circuit_model,
                                              tech_lib, tech_model);
+        netlist_filled = true;
       } else {
         VTR_ASSERT(CIRCUIT_MODEL_BUF_BUF == circuit_lib.buffer_type(circuit_model));
         status = print_spice_buffer_subckt(fp,
                                            module_manager, module_id,
                                            circuit_lib, circuit_model,
                                            tech_lib, tech_model);
+        netlist_filled = true;
       }
 
       if (CMD_EXEC_FATAL_ERROR == status) {
         break;
       }
-
-      /* Finish, go to the next */
-      continue;
     }
 
     /* Now branch on netlist writing: for pass-gate logic */
@@ -119,13 +123,11 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
                                            module_manager, module_id,
                                            circuit_lib, circuit_model,
                                            tech_lib, tech_model);
+      netlist_filled = true;
 
       if (CMD_EXEC_FATAL_ERROR == status) {
         break;
       }
-
-      /* Finish, go to the next */
-      continue;
     }
 
     /* Now branch on netlist writing: for logic gate */
@@ -135,33 +137,41 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
                                              module_manager, module_id,
                                              circuit_lib, circuit_model,
                                              tech_lib, tech_model);
+        netlist_filled = true;
       } else if (CIRCUIT_MODEL_GATE_OR == circuit_lib.gate_type(circuit_model)) {
         status = print_spice_or_gate_subckt(fp,
                                             module_manager, module_id,
                                             circuit_lib, circuit_model,
                                             tech_lib, tech_model);
+        netlist_filled = true;
       }
 
       if (CMD_EXEC_FATAL_ERROR == status) {
         break;
       }
-
-      /* Finish, go to the next */
-      continue;
     }
 
+    /* Check if the netlist has been filled or not.
+     * If not, flag a fatal error
+     */
+    if (false == netlist_filled) {
+      VTR_LOG_ERROR("Cannot auto-generate netlist for circuit model '%s'!\n\tThe circuit topology is not supported yet!\n",
+                    circuit_lib.model_name(circuit_model).c_str());
+      status = CMD_EXEC_FATAL_ERROR; 
+      break;
+    }
+
+    /* Close file handler*/
+    fp.close();
+
+    /* Add fname to the netlist name list */
+    NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+    VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+    netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
+
+    VTR_LOG("Done\n");
   } 
 
-  /* Close file handler*/
-  fp.close();
-
-  /* Add fname to the netlist name list */
-  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
-  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
-  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
-
-  VTR_LOG("Done\n");
-
   return status;
 }
 

From 1b2762386cfa5b56bd67ee2406f5fd7b465140e4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 16:52:30 -0600
Subject: [PATCH 091/148] [FPGA-SPICE] Bug fix for essential gate netlist
 writing

---
 .../src/fpga_spice/spice_essential_gates.cpp  | 26 ++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index 780a31776..107077bcc 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -52,6 +52,15 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       continue;
     }
 
+    /* Output only the model type is supported in auto-generation */
+    if ( (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(circuit_model))
+      && (CIRCUIT_MODEL_PASSGATE != circuit_lib.model_type(circuit_model))
+      && (CIRCUIT_MODEL_CHAN_WIRE != circuit_lib.model_type(circuit_model))
+      && (CIRCUIT_MODEL_WIRE != circuit_lib.model_type(circuit_model))
+      && (CIRCUIT_MODEL_GATE != circuit_lib.model_type(circuit_model))) {
+      continue; 
+    }
+
     /* Spot module id */
     const ModuleId& module_id = module_manager.find_module(circuit_lib.model_name(circuit_model));
 
@@ -75,7 +84,7 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
     }
 
     /* Create file stream */
-    std::string spice_fname = submodule_dir + circuit_lib.model_name(circuit_model);
+    std::string spice_fname = submodule_dir + circuit_lib.model_name(circuit_model) + std::string(SPICE_NETLIST_FILE_POSTFIX);
   
     std::fstream fp;
   
@@ -151,6 +160,21 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       }
     }
 
+    /* Now branch on netlist writing: for routing channel wires */
+    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(circuit_model)) {
+      netlist_filled = true;
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        break;
+      }
+    }
+    /* Now branch on netlist writing: for regular wires */
+    if (CIRCUIT_MODEL_WIRE == circuit_lib.model_type(circuit_model)) {
+      netlist_filled = true;
+      if (CMD_EXEC_FATAL_ERROR == status) {
+        break;
+      }
+    }
+
     /* Check if the netlist has been filled or not.
      * If not, flag a fatal error
      */

From 82e137cbe40c2edf652d8a4df4284660727cb4d2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 19:31:16 -0600
Subject: [PATCH 092/148] [FPGA-SPICE] Add wire module SPICE writer

---
 .../src/fpga_spice/spice_essential_gates.cpp  |  14 +-
 openfpga/src/fpga_spice/spice_wire.cpp        | 408 ++++++++++++++++++
 openfpga/src/fpga_spice/spice_wire.h          |  27 ++
 .../src/fpga_spice/spice_writer_utils.cpp     | 155 +++++++
 openfpga/src/fpga_spice/spice_writer_utils.h  |  20 +
 5 files changed, 615 insertions(+), 9 deletions(-)
 create mode 100644 openfpga/src/fpga_spice/spice_wire.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_wire.h

diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index 107077bcc..eafe37a24 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -25,6 +25,7 @@
 #include "spice_buffer.h"
 #include "spice_passgate.h"
 #include "spice_logic_gate.h"
+#include "spice_wire.h"
 #include "spice_essential_gates.h"
 
 /* begin namespace openfpga */
@@ -55,7 +56,6 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
     /* Output only the model type is supported in auto-generation */
     if ( (CIRCUIT_MODEL_INVBUF != circuit_lib.model_type(circuit_model))
       && (CIRCUIT_MODEL_PASSGATE != circuit_lib.model_type(circuit_model))
-      && (CIRCUIT_MODEL_CHAN_WIRE != circuit_lib.model_type(circuit_model))
       && (CIRCUIT_MODEL_WIRE != circuit_lib.model_type(circuit_model))
       && (CIRCUIT_MODEL_GATE != circuit_lib.model_type(circuit_model))) {
       continue; 
@@ -160,15 +160,11 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
       }
     }
 
-    /* Now branch on netlist writing: for routing channel wires */
-    if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(circuit_model)) {
-      netlist_filled = true;
-      if (CMD_EXEC_FATAL_ERROR == status) {
-        break;
-      }
-    }
-    /* Now branch on netlist writing: for regular wires */
+    /* Now branch on netlist writing: for wires */
     if (CIRCUIT_MODEL_WIRE == circuit_lib.model_type(circuit_model)) {
+      status = print_spice_wire_subckt(fp,
+                                       module_manager, module_id,
+                                       circuit_lib, circuit_model);
       netlist_filled = true;
       if (CMD_EXEC_FATAL_ERROR == status) {
         break;
diff --git a/openfpga/src/fpga_spice/spice_wire.cpp b/openfpga/src/fpga_spice/spice_wire.cpp
new file mode 100644
index 000000000..097515899
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_wire.cpp
@@ -0,0 +1,408 @@
+/************************************************
+ * This file includes functions on 
+ * outputting SPICE netlists for routing wires:
+ * - regular wires (1 input and 1 output)
+ * - routing track wires (1 input and 2 outputs)
+ ***********************************************/
+#include <fstream>
+#include <cmath>
+#include <iomanip>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "circuit_library_utils.h"
+#include "build_module_graph_utils.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_wire.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print SPICE modeling for pie-type RC network
+ *
+ * Schematic
+ *                      middle out
+ *                          |
+ *   in ---wwww----wwww--- ... --wwww---out 
+ *       |       |      |             |
+ *       =       =      =             =
+ *       |       |      |             |
+ *      GND     GND    GND           GND
+ *******************************************************************/
+static 
+int print_spice_wire_pi_type_rc_modeling(std::fstream& fp,
+                                         const std::string& input_port_name,
+                                         const std::string& output_port_name,
+                                         const std::string& middle_output_port_name,
+                                         const float& res_total, 
+                                         const float& cap_total, 
+                                         const size_t& num_levels) {
+
+  /* Determine the resistance and capacitance of each level*/
+  float res_per_level = res_total / ((float)(2 * num_levels));
+  float cap_per_level = cap_total / ((float)(2 * num_levels));
+
+  /* All the resistance and capacitance value should be larger than or equal to zero*/
+  VTR_ASSERT(0. <= res_per_level);
+  VTR_ASSERT(0. <= cap_per_level);
+
+  for (size_t ilvl = 0; ilvl < num_levels; ++ilvl) {
+    /* Print the first capacitor if this is the first level */
+    if ((0 == ilvl) && (0. < cap_per_level)) {
+      print_spice_capacitor(fp, input_port_name, std::string(SPICE_SUBCKT_GND_PORT_NAME), cap_per_level);
+    }
+    /* Output a regular RC pair 
+     *
+     *           midnode
+     *              ^
+     *              |
+     *   ------+-ww-+-ww-+------
+     *         |         |
+     *         =         =
+     *         |         |
+     *        GND       GND
+     */
+
+    std::string lvl_input_port_name = std::string("rc_network_node") + std::to_string(ilvl);
+    if (0 == ilvl) {
+      lvl_input_port_name = input_port_name;
+    } 
+
+    std::string lvl_middle_port_name = std::string("rc_network_midnode") + std::to_string(ilvl);
+
+    std::string lvl_output_port_name = std::string("rc_network_node") + std::to_string(ilvl + 1);
+    if (ilvl == num_levels - 1) {
+      lvl_output_port_name = output_port_name;
+    }
+
+    print_spice_resistor(fp, lvl_input_port_name, lvl_middle_port_name, res_per_level); 
+    print_spice_resistor(fp, lvl_middle_port_name, lvl_output_port_name, res_per_level); 
+
+    /* Last level only require 1 unit of cap_per_level */
+    float cap_curr_level = 2. * cap_per_level;
+    if (ilvl == num_levels - 1) {
+      cap_curr_level = cap_per_level;
+    }
+
+    if (0. < cap_curr_level) {
+      print_spice_capacitor(fp, lvl_output_port_name, std::string(SPICE_SUBCKT_GND_PORT_NAME), cap_curr_level);
+    }
+  }
+
+  /* If the middle output is required, create a short connection to
+   * - when the number of levels is odd
+   *
+   *         middle_output
+   *              ^
+   *              |
+   *   ---ww-+-ww-+-ww-+-ww---
+   *         |         |
+   *         =         =
+   *         |         |
+   *        GND       GND
+   *
+   * - when the number of levels is even:
+   *    
+   *         middle_output
+   *             ^
+   *             |
+   *   -+-ww--ww-+-ww--ww-+-
+   *    |        |        |
+   *    =        =        =
+   *    |        |        |
+   *   GND      GND      GND
+   *          
+   */
+  if (!middle_output_port_name.empty()) {
+    print_spice_comment(fp, std::string("Connect to the middle output"));
+    std::string rc_midnode_name = std::string("rc_network_node") + std::to_string(num_levels / 2 + 1);
+    if (1 == num_levels % 2) {
+      rc_midnode_name = std::string("rc_network_midnode") + std::to_string(num_levels / 2);
+    }
+    print_spice_short_connection(fp, rc_midnode_name, middle_output_port_name); 
+  }
+
+  return CMD_EXEC_SUCCESS;
+}
+
+/********************************************************************
+ * Print SPICE modeling for T-type RC network
+ *
+ * Schematic
+ *                                middle out
+ *                                    |
+ *   in ---ww-+--ww--+--ww--+--ww--- ... --ww--+--ww--- out 
+ *            |      |      |                  |
+ *            =      =      =                  =
+ *            |      |      |                  |
+ *           GND    GND    GND                GND
+ *******************************************************************/
+static 
+int print_spice_wire_t_type_rc_modeling(std::fstream& fp,
+                                        const std::string& input_port_name,
+                                        const std::string& output_port_name,
+                                        const std::string& middle_output_port_name,
+                                        const float& res_total, 
+                                        const float& cap_total, 
+                                        const size_t& num_levels) {
+
+  /* Determine the resistance and capacitance of each level*/
+  float res_per_level = res_total / ((float)(2 * num_levels));
+  float cap_per_level = cap_total / ((float)(num_levels));
+
+  /* All the resistance and capacitance value should be larger than or equal to zero*/
+  VTR_ASSERT(0. <= res_per_level);
+  VTR_ASSERT(0. <= cap_per_level);
+
+  for (size_t ilvl = 0; ilvl < num_levels; ++ilvl) {
+    /* Output a regular RC pair 
+     *
+     *           midnode
+     *              ^
+     *              |
+     *   --------ww-+-ww--------
+     *              |         
+     *              =         
+     *              |         
+     *             GND      
+     */
+
+    std::string lvl_input_port_name = std::string("rc_network_node") + std::to_string(ilvl);
+    if (0 == ilvl) {
+      lvl_input_port_name = input_port_name;
+    } 
+
+    std::string lvl_middle_port_name = std::string("rc_network_midnode") + std::to_string(ilvl);
+
+    std::string lvl_output_port_name = std::string("rc_network_node") + std::to_string(ilvl + 1);
+    if (ilvl == num_levels - 1) {
+      lvl_output_port_name = output_port_name;
+    }
+
+    print_spice_resistor(fp, lvl_input_port_name, lvl_middle_port_name, res_per_level); 
+    print_spice_resistor(fp, lvl_middle_port_name, lvl_output_port_name, res_per_level); 
+
+    if (0. < cap_per_level) {
+      print_spice_capacitor(fp, lvl_middle_port_name, std::string(SPICE_SUBCKT_GND_PORT_NAME), cap_per_level);
+    }
+  }
+
+  /* If the middle output is required, create a short connection to
+   * - when the number of levels is even
+   *
+   *         middle_output
+   *              ^
+   *              |
+   *   ---ww-+-ww-+-ww-+-ww---
+   *         |         |
+   *         =         =
+   *         |         |
+   *        GND       GND
+   *
+   * - when the number of levels is odd:
+   *    
+   *         middle_output
+   *             ^
+   *             |
+   *   -+-ww--ww-+-ww--ww-+-
+   *    |        |        |
+   *    =        =        =
+   *    |        |        |
+   *   GND      GND      GND
+   *          
+   */
+  if (!middle_output_port_name.empty()) {
+    print_spice_comment(fp, std::string("Connect to the middle output"));
+    std::string rc_midnode_name = std::string("rc_network_midnode") + std::to_string(num_levels / 2);
+    if (0 == num_levels % 2) {
+      rc_midnode_name = std::string("rc_network_node") + std::to_string(num_levels / 2 + 1);
+    }
+    print_spice_short_connection(fp, rc_midnode_name, middle_output_port_name); 
+  }
+
+  return CMD_EXEC_SUCCESS;
+}
+
+
+/********************************************************************
+ * Generate the SPICE subckt for a regular wire
+ *
+ * Schematic
+ *
+ *                                 Middle output (only for routing track wires)
+ *                                      ^
+ *                                      |
+ *      +--------------------+    +---------------+     +--------------------+
+ * in ->| Inverter or buffer |--->|   RC Network  |---->| Inverter or buffer |---> out
+ *      |  Optional          |    |               |     | Optional           |
+ *      +---------------------    +---------------+     +--------------------+
+ *     
+ *******************************************************************/
+int print_spice_wire_subckt(std::fstream& fp,
+                            const ModuleManager& module_manager,
+                            const ModuleId& module_id,
+                            const CircuitLibrary& circuit_lib,
+                            const CircuitModelId& circuit_model) {
+
+ if (false == valid_file_stream(fp)) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Find the input and output ports:
+   * we do NOT support global ports here, 
+   * it should be handled in another type of inverter subckt (power-gated)
+   */
+  std::vector<CircuitPortId> input_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_INPUT, true);
+  std::vector<CircuitPortId> output_ports = circuit_lib.model_ports_by_type(circuit_model, CIRCUIT_MODEL_PORT_OUTPUT, true);
+
+  /* Make sure:
+   * There are 1 input ports and 1 output port, 
+   * each size of which is 1
+   */
+  VTR_ASSERT( (1 == input_ports.size()) && (1 == circuit_lib.port_size(input_ports[0])) );
+  VTR_ASSERT( (1 == output_ports.size()) && (1 == circuit_lib.port_size(output_ports[0])) );
+
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Print the inverter subckt definition */
+  print_spice_subckt_definition(fp, module_manager, module_id); 
+
+  std::string input_port_name = circuit_lib.port_prefix(input_ports[0]);
+  std::string output_port_name = circuit_lib.port_prefix(output_ports[0]);
+  std::string middle_output_port_name;
+  if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(circuit_model)) {
+    middle_output_port_name = std::string("middle") + output_port_name;
+  }
+
+  std::string rc_ntwk_input_port_name = std::string("rc_network_node") + std::to_string(0);
+  std::string rc_ntwk_output_port_name = std::string("rc_network_node") + std::to_string(circuit_lib.wire_num_level(circuit_model) - 1);
+  std::string rc_ntwk_middle_output_port_name;
+  if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(circuit_model)) {
+    rc_ntwk_middle_output_port_name = std::string("middle") + rc_ntwk_output_port_name;
+  }
+  
+  ModulePortId wire_module_input_port = module_manager.find_module_port(module_id, input_port_name);
+  ModulePortId wire_module_output_port = module_manager.find_module_port(module_id, output_port_name);
+  ModulePortId wire_module_middle_output_port = ModulePortId::INVALID();
+  if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(circuit_model)) {
+    wire_module_middle_output_port = module_manager.find_module_port(module_id, output_port_name);
+  }
+
+  /* Add input buffer:
+   * - There is a valid buffer model, instanciate it
+   * - There is no buffer, set a short connection
+   */
+  if (circuit_lib.input_buffer_model(circuit_model)) {
+    std::string instance_name = std::string("input_buffer");
+    std::map<std::string, BasicPort> port2port_name_map;
+
+    ModuleId buffer_module = module_manager.find_module(circuit_lib.model_name(circuit_lib.input_buffer_model(circuit_model)));
+    VTR_ASSERT(true == module_manager.valid_module_id(buffer_module));
+  
+    ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, buffer_module, circuit_lib, circuit_model, CIRCUIT_MODEL_PORT_INPUT);
+    ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, buffer_module, circuit_lib, circuit_model, CIRCUIT_MODEL_PORT_OUTPUT);
+
+    /* Port size should be 1 ! */
+    VTR_ASSERT(1 == module_manager.module_port(buffer_module, module_input_port_id).get_width());
+    VTR_ASSERT(1 == module_manager.module_port(buffer_module, module_output_port_id).get_width());
+
+    port2port_name_map[module_manager.module_port(buffer_module, module_input_port_id).get_name()] = module_manager.module_port(module_id, wire_module_input_port);
+    port2port_name_map[module_manager.module_port(buffer_module, module_output_port_id).get_name()] = BasicPort(rc_ntwk_input_port_name, 1);
+
+    print_spice_subckt_instance(fp, 
+                                module_manager, 
+                                buffer_module,
+                                instance_name,
+                                port2port_name_map);
+  } else {
+    print_spice_short_connection(fp, circuit_lib.port_prefix(input_ports[0]), rc_ntwk_input_port_name); 
+  }
+
+  /* Determine which type of model to print*/
+  switch (circuit_lib.wire_type(circuit_model)) {
+  case WIRE_MODEL_PI:
+   status = print_spice_wire_pi_type_rc_modeling(fp,
+                                                 rc_ntwk_input_port_name,
+                                                 rc_ntwk_output_port_name,
+                                                 rc_ntwk_middle_output_port_name,
+                                                 circuit_lib.wire_r(circuit_model), 
+                                                 circuit_lib.wire_c(circuit_model), 
+                                                 circuit_lib.wire_num_level(circuit_model)); 
+    break;
+  case WIRE_MODEL_T: 
+    status = print_spice_wire_t_type_rc_modeling(fp,
+                                                 rc_ntwk_input_port_name,
+                                                 rc_ntwk_output_port_name,
+                                                 rc_ntwk_middle_output_port_name,
+                                                 circuit_lib.wire_r(circuit_model), 
+                                                 circuit_lib.wire_c(circuit_model), 
+                                                 circuit_lib.wire_num_level(circuit_model)); 
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Unsupport wire model type for circuit model '%s.\n",
+                   circuit_lib.model_name(circuit_model).c_str());
+    return CMD_EXEC_FATAL_ERROR;
+  } 
+
+  /* Add output buffer:
+   * - There is a valid buffer model, instanciate it
+   * - There is no buffer, set a short connection
+   */
+  if (circuit_lib.output_buffer_model(circuit_model)) {
+    std::string instance_name = std::string("output_buffer");
+    std::map<std::string, BasicPort> port2port_name_map;
+
+    ModuleId buffer_module = module_manager.find_module(circuit_lib.model_name(circuit_lib.output_buffer_model(circuit_model)));
+    VTR_ASSERT(true == module_manager.valid_module_id(buffer_module));
+  
+    ModulePortId module_input_port_id = find_inverter_buffer_module_port(module_manager, buffer_module, circuit_lib, circuit_model, CIRCUIT_MODEL_PORT_INPUT);
+    ModulePortId module_output_port_id = find_inverter_buffer_module_port(module_manager, buffer_module, circuit_lib, circuit_model, CIRCUIT_MODEL_PORT_OUTPUT);
+
+    /* Port size should be 1 ! */
+    VTR_ASSERT(1 == module_manager.module_port(buffer_module, module_input_port_id).get_width());
+    VTR_ASSERT(1 == module_manager.module_port(buffer_module, module_output_port_id).get_width());
+
+    port2port_name_map[module_manager.module_port(buffer_module, module_input_port_id).get_name()] = BasicPort(rc_ntwk_output_port_name, 1);
+    port2port_name_map[module_manager.module_port(buffer_module, module_output_port_id).get_name()] = module_manager.module_port(module_id, wire_module_output_port);
+
+    print_spice_subckt_instance(fp, 
+                                module_manager, 
+                                buffer_module,
+                                instance_name,
+                                port2port_name_map);
+
+    if (!rc_ntwk_middle_output_port_name.empty()) {
+      instance_name = std::string("middle_output_buffer");
+      port2port_name_map[module_manager.module_port(buffer_module, module_output_port_id).get_name()] = module_manager.module_port(module_id, wire_module_middle_output_port);
+
+    print_spice_subckt_instance(fp, 
+                                module_manager, 
+                                buffer_module,
+                                instance_name,
+                                port2port_name_map);
+    }
+  } else {
+    print_spice_short_connection(fp, rc_ntwk_output_port_name, circuit_lib.port_prefix(output_ports[0])); 
+    if (!rc_ntwk_middle_output_port_name.empty()) {
+      print_spice_short_connection(fp, rc_ntwk_middle_output_port_name, circuit_lib.port_prefix(output_ports[0])); 
+    }
+  }
+
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  return status;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_wire.h b/openfpga/src/fpga_spice/spice_wire.h
new file mode 100644
index 000000000..5af9542a0
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_wire.h
@@ -0,0 +1,27 @@
+#ifndef SPICE_WIRE_H
+#define SPICE_WIRE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include <map>
+#include "module_manager.h"
+#include "circuit_library.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_wire_subckt(std::fstream& fp,
+                            const ModuleManager& module_manager,
+                            const ModuleId& module_id,
+                            const CircuitLibrary& circuit_lib,
+                            const CircuitModelId& circuit_model);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_spice/spice_writer_utils.cpp b/openfpga/src/fpga_spice/spice_writer_utils.cpp
index 89b82a027..889ee8c19 100644
--- a/openfpga/src/fpga_spice/spice_writer_utils.cpp
+++ b/openfpga/src/fpga_spice/spice_writer_utils.cpp
@@ -168,4 +168,159 @@ void print_spice_subckt_end(std::fstream& fp,
   fp << std::endl;
 }
 
+/************************************************
+ * Print a resistor in SPICE syntax
+ ***********************************************/
+void print_spice_resistor(std::fstream& fp,
+                          const std::string& input_port,
+                          const std::string& output_port,
+                          const float& resistance) {
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Set an unique name to the resistor */
+  fp << "R" << input_port << "_to_"  << output_port;
+  fp << " " << input_port;
+  fp << " " << output_port;
+  fp << " " << std::setprecision(10) << resistance;
+  fp << std::endl;
+}
+
+/************************************************
+ * Print a capacitor in SPICE syntax
+ ***********************************************/
+void print_spice_capacitor(std::fstream& fp,
+                          const std::string& input_port,
+                          const std::string& output_port,
+                          const float& capacitance) {
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Set an unique name to the capacitor */
+  fp << "C" << input_port << "_to_"  << output_port;
+  fp << " " << input_port;
+  fp << " " << output_port;
+  fp << " " << std::setprecision(10) << capacitance;
+  fp << std::endl;
+}
+
+/************************************************
+ * Print a short-connected wire using zero resistance in SPICE syntax
+ ***********************************************/
+void print_spice_short_connection(std::fstream& fp,
+                                  const std::string& input_port,
+                                  const std::string& output_port) {
+  print_spice_resistor(fp, input_port, output_port, 0.);
+}
+
+/********************************************************************
+ * Print an instance in SPICE format (a generic version)
+ * This function will require user to provide an instance name
+ *
+ * This function will output the port map by referring to a port-to-port 
+ * mapping:
+ *   <module_port_name> -> <instance_port_name>
+ * The key of the port-to-port mapping is the port name of the module: 
+ * The value of the port-to-port mapping is the port information of the instance
+ * With link between module and instance, the function can output a SPICE 
+ * instance easily, by following the define port sequence of the module
+ *
+ * Note that, it is not necessary that the port-to-port mapping 
+ * covers all the module ports.
+ * Any instance/module port which are not specified in the port-to-port 
+ * mapping will be output by the module port name.
+ *******************************************************************/
+void print_spice_subckt_instance(std::fstream& fp, 
+                                 const ModuleManager& module_manager, 
+                                 const ModuleId& module_id,
+                                 const std::string& instance_name,
+                                 const std::map<std::string, BasicPort>& port2port_name_map) {
+
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Check: all the key ports in the port2port_name_map does exist in the child module */
+  for (const auto& kv : port2port_name_map) {
+    ModulePortId module_port_id = module_manager.find_module_port(module_id, kv.first);
+    VTR_ASSERT(ModulePortId::INVALID() != module_port_id);
+  }
+
+  /* Print instance name */
+  std::string instance_head_line = "X " + instance_name + " ";
+  fp << instance_head_line;
+  
+  /* Port sequence: global, inout, input, output and clock ports, */
+  bool fit_one_line = true;
+  bool new_line = false;
+  size_t pin_cnt = 0;
+  for (int port_type = ModuleManager::MODULE_GLOBAL_PORT;
+       port_type < ModuleManager::NUM_MODULE_PORT_TYPES;
+       ++port_type) {
+    for (const auto& port : module_manager.module_ports_by_type(module_id, static_cast<ModuleManager::e_module_port_type>(port_type))) {
+      /* Deposit a default port name */
+      BasicPort port_to_print = port;
+      /* Try to find the instanced port name in the name map */
+      auto port_search_result = port2port_name_map.find(port.get_name());
+      if (port_search_result != port2port_name_map.end()) {
+        /* Found it, we assign the port name */ 
+        /* TODO: make sure the port width matches! */
+        ModulePortId module_port_id = module_manager.find_module_port(module_id, port.get_name());
+        /* Get the port from module */
+        BasicPort module_port = module_manager.module_port(module_id, module_port_id);
+        VTR_ASSERT(module_port.get_width() == port_search_result->second.get_width());
+
+        port_to_print = port_search_result->second;
+      }
+
+      /* Print port: only the port name is enough */
+      for (const auto& pin : port_to_print.pins()) {
+
+        if (true == new_line) {
+          std::string port_whitespace(instance_head_line.length() - 2, ' ');
+          fp << "+ " << port_whitespace;
+        }
+ 
+        if (0 != pin_cnt) {
+          write_space_to_file(fp, 1);
+        }
+        
+        BasicPort port_pin(port.get_name(), pin, pin);
+
+        /* For single-bit port,
+         * we can print the port name directly
+         */
+        bool omit_pin_zero = false;
+        if ((1 == port.pins().size())
+           && (0 == pin)) {
+          omit_pin_zero = true;
+        }
+
+        fp << generate_spice_port(port_pin, omit_pin_zero);
+
+        /* Increase the counter */
+        pin_cnt++;
+
+        /* Currently we limit 10 ports per line to keep a clean netlist */
+        new_line = false;
+        if (10 == pin_cnt) {
+          pin_cnt = 0;
+          fp << std::endl;
+          new_line = true;
+          fit_one_line = false;
+        }
+      }
+    }
+  }
+
+  /* Print module name: 
+   * if port print cannot fit one line, we create a new line for the module for a clean format
+   */
+  if (false == fit_one_line) {
+    fp << std::endl;
+    fp << "+";
+  }
+  write_space_to_file(fp, 1);
+  fp << module_manager.module_name(module_id);
+  
+  /* Print an end to the instance */
+  fp << std::endl;
+}
+
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_writer_utils.h b/openfpga/src/fpga_spice/spice_writer_utils.h
index 3da2a6339..b01d5a35c 100644
--- a/openfpga/src/fpga_spice/spice_writer_utils.h
+++ b/openfpga/src/fpga_spice/spice_writer_utils.h
@@ -48,6 +48,26 @@ void print_spice_subckt_definition(std::fstream& fp,
 void print_spice_subckt_end(std::fstream& fp, 
                             const std::string& module_name);
 
+void print_spice_resistor(std::fstream& fp,
+                          const std::string& input_port,
+                          const std::string& output_port,
+                          const float& resistance);
+
+void print_spice_capacitor(std::fstream& fp,
+                          const std::string& input_port,
+                          const std::string& output_port,
+                          const float& capacitance);
+
+void print_spice_short_connection(std::fstream& fp,
+                                  const std::string& input_port,
+                                  const std::string& output_port);
+
+void print_spice_subckt_instance(std::fstream& fp, 
+                                 const ModuleManager& module_manager, 
+                                 const ModuleId& module_id,
+                                 const std::string& instance_name,
+                                 const std::map<std::string, BasicPort>& port2port_name_map);
+
 } /* end namespace openfpga */
 
 #endif

From 15df9b3893515a66f392f23197444de90b62e630 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 19 Sep 2020 23:01:44 -0600
Subject: [PATCH 093/148] [FPGA-SPICE] Add SPICE subcircuit writer

---
 .../src/fpga_spice/spice_subckt_writer.cpp    | 449 ++++++++++++++++++
 openfpga/src/fpga_spice/spice_subckt_writer.h |  23 +
 2 files changed, 472 insertions(+)
 create mode 100644 openfpga/src/fpga_spice/spice_subckt_writer.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_subckt_writer.h

diff --git a/openfpga/src/fpga_spice/spice_subckt_writer.cpp b/openfpga/src/fpga_spice/spice_subckt_writer.cpp
new file mode 100644
index 000000000..c90c0b5ac
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_subckt_writer.cpp
@@ -0,0 +1,449 @@
+/********************************************************************
+ * This file includes functions to write a SPICE module
+ * based on its definition in Module Manager
+ *
+ * Note that SPICE writer functions are just an outputter for the
+ * module definition. 
+ * You should NOT modify any content of the module manager
+ * Please use const keyword to restrict this!
+ *******************************************************************/
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_port.h"
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "module_manager_utils.h"
+#include "spice_writer_utils.h"
+#include "spice_subckt_writer.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Generate the name of a local wire for a undriven port inside SPICE 
+ * module 
+ *******************************************************************/
+static 
+std::string generate_spice_undriven_local_wire_name(const ModuleManager& module_manager, 
+                                                    const ModuleId& parent, 
+                                                    const ModuleId& child, 
+                                                    const size_t& instance_id, 
+                                                    const ModulePortId& child_port_id) {
+  std::string wire_name;
+  if (!module_manager.instance_name(parent, child, instance_id).empty()) {
+    wire_name = module_manager.instance_name(parent, child, instance_id);
+  } else {
+    wire_name = module_manager.module_name(parent) + std::string("_") + std::to_string(instance_id); 
+    wire_name += std::string("_");
+  }
+  
+  wire_name += std::string("_undriven_");
+  wire_name += module_manager.module_port(child, child_port_id).get_name();
+  
+  return wire_name;
+}
+
+
+/********************************************************************
+ * Name a net for a local wire for a SPICE subckt
+ * 1. If this is a local wire, name it after the <src_module_name>_<instance_id>_<src_port_name>
+ * 2. If this is not a local wire, name it after the port name of parent module 
+ *
+ * In addition, it will assign the pin index as well  
+ *
+ * Restriction: this function requires each net has single driver
+ * which is definitely always true in circuits.
+ *******************************************************************/
+static 
+BasicPort generate_spice_port_for_module_net(const ModuleManager& module_manager,
+                                             const ModuleId& module_id,
+                                             const ModuleNetId& module_net) {
+  /* Check all the sink modules of the net, 
+   * if we have a source module is the current module, this is not local wire 
+   */
+  for (ModuleNetSrcId src_id : module_manager.module_net_sources(module_id, module_net)) {
+    if (module_id == module_manager.net_source_modules(module_id, module_net)[src_id]) {
+      /* Here, this is not a local wire, return the port name of the src_port */
+      ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[src_id];
+      size_t src_pin_index = module_manager.net_source_pins(module_id, module_net)[src_id];
+      return BasicPort(module_manager.module_port(module_id, net_src_port).get_name(), src_pin_index, src_pin_index);
+    }
+  }
+
+  /* Check all the sink modules of the net */
+  for (ModuleNetSinkId sink_id : module_manager.module_net_sinks(module_id, module_net)) {
+    if (module_id == module_manager.net_sink_modules(module_id, module_net)[sink_id]) {
+      /* Here, this is not a local wire, return the port name of the sink_port */
+      ModulePortId net_sink_port = module_manager.net_sink_ports(module_id, module_net)[sink_id];
+      size_t sink_pin_index = module_manager.net_sink_pins(module_id, module_net)[sink_id];
+      return BasicPort(module_manager.module_port(module_id, net_sink_port).get_name(), sink_pin_index, sink_pin_index);
+    }
+  }
+
+  /* Reach here, this is a local wire */
+  std::string net_name;
+
+  /* Each net must only one 1 source */ 
+  VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size());
+
+  /* Get the source module */
+  ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)];
+  /* Get the instance id */
+  size_t net_src_instance = module_manager.net_source_instances(module_id, module_net)[ModuleNetSrcId(0)]; 
+  /* Get the port id */
+  ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[ModuleNetSrcId(0)]; 
+  /* Get the pin id */
+  size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)]; 
+
+  /* Load user-defined name if we have it */
+  if (false == module_manager.net_name(module_id, module_net).empty()) {
+    net_name = module_manager.net_name(module_id, module_net);
+  } else {
+    net_name  = module_manager.module_name(net_src_module); 
+    net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_");
+    net_name += module_manager.module_port(net_src_module, net_src_port).get_name();
+  }
+  
+  return BasicPort(net_name, net_src_pin, net_src_pin);
+}
+
+/********************************************************************
+ * Print a SPICE wire connection 
+ * We search all the sinks of the net, 
+ * if we find a module output, we try to find the next module output 
+ * among the sinks of the net
+ * For each module output (except the first one), we print a wire connection 
+ *******************************************************************/
+static 
+void print_spice_subckt_output_short_connection(std::fstream& fp, 
+                                                const ModuleManager& module_manager,
+                                                const ModuleId& module_id,
+                                                const ModuleNetId& module_net) {
+  /* Ensure a valid file stream */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  bool first_port = true;
+  BasicPort src_port;
+
+  /* We have found a module input, now check all the sink modules of the net */
+  for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
+    ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
+    if (module_id != sink_module) {
+      continue;
+    }
+
+    /* Find the sink port and pin information */
+    ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
+    size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
+    BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
+
+    /* For the first module output, this is the source port, we do nothing and go to the next */
+    if (true == first_port) {
+      src_port = sink_port;
+      /* Flip the flag */
+      first_port = false;
+      continue;
+    }
+
+    /* We need to print a wire connection here */
+    VTR_ASSERT(src_port.get_width() == sink_port.get_width());
+    for (size_t ipin = 0; ipin < src_port.pins().size(); ++ipin) {
+      BasicPort src_spice_pin(src_port.get_name(), src_port.pins()[ipin], src_port.pins()[ipin]);
+      BasicPort sink_spice_pin(sink_port.get_name(), sink_port.pins()[ipin], sink_port.pins()[ipin]);
+      print_spice_short_connection(fp,
+                                   generate_spice_port(src_spice_pin),
+                                   generate_spice_port(sink_spice_pin));
+    }
+  }
+}
+
+
+/********************************************************************
+ * Print a SPICE wire connection 
+ * We search all the sources of the net, 
+ * if we find a module input, we try to find a module output 
+ * among the sinks of the net
+ * If we find such a pair, we print a wire connection 
+ *******************************************************************/
+static 
+void print_spice_subckt_local_short_connection(std::fstream& fp, 
+                                               const ModuleManager& module_manager,
+                                               const ModuleId& module_id,
+                                               const ModuleNetId& module_net) {
+  /* Ensure a valid file stream */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  for (ModuleNetSrcId net_src : module_manager.module_net_sources(module_id, module_net)) {
+    ModuleId src_module = module_manager.net_source_modules(module_id, module_net)[net_src];
+    if (module_id != src_module) {
+      continue;
+    }
+    /* Find the source port and pin information */
+    print_spice_comment(fp, std::string("Net source id " + std::to_string(size_t(net_src))));
+    ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src];
+    size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src];
+    BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin);
+
+    /* We have found a module input, now check all the sink modules of the net */
+    for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
+      ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
+      if (module_id != sink_module) {
+        continue;
+      }
+
+      /* Find the sink port and pin information */
+      print_spice_comment(fp, std::string("Net sink id " + std::to_string(size_t(net_sink))));
+      ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
+      size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
+      BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
+
+      /* We need to print a wire connection here */
+      VTR_ASSERT(src_port.get_width() == sink_port.get_width());
+      for (size_t ipin = 0; ipin < src_port.pins().size(); ++ipin) {
+        BasicPort src_spice_pin(src_port.get_name(), src_port.pins()[ipin], src_port.pins()[ipin]);
+        BasicPort sink_spice_pin(sink_port.get_name(), sink_port.pins()[ipin], sink_port.pins()[ipin]);
+        print_spice_short_connection(fp,
+                                     generate_spice_port(src_spice_pin),
+                                     generate_spice_port(sink_spice_pin));
+      }
+    }
+  }
+}
+
+/********************************************************************
+ * Print short connections inside a SPICE module
+ * The short connection is defined as the direct connection
+ * between an input port of the module and an output port of the module
+ * This type of connection is not covered when printing SPICE instances
+ * Therefore, they are covered in this function 
+ *
+ *            module
+ *            +-----------------------------+
+ *            |                             |
+ *  inputA--->|---------------------------->|--->outputB
+ *            |                             |
+ *            |                             |
+ *            |                             |
+ *            +-----------------------------+
+ *******************************************************************/
+static 
+void print_spice_subckt_local_short_connections(std::fstream& fp, 
+                                                const ModuleManager& module_manager,
+                                                const ModuleId& module_id) {
+  /* Local wires come from the child modules */
+  for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
+    /* We only care the nets that indicate short connections */ 
+    if (false == module_net_include_local_short_connection(module_manager, module_id, module_net)) {
+      continue;
+    }
+    print_spice_comment(fp, std::string("Local connection due to Wire " + std::to_string(size_t(module_net))));
+    print_spice_subckt_local_short_connection(fp, module_manager, module_id, module_net); 
+  }
+}
+
+/********************************************************************
+ * Print output short connections inside a SPICE module
+ * The output short connection is defined as the direct connection
+ * between two output ports of the module
+ * This type of connection is not covered when printing SPICE instances
+ * Therefore, they are covered in this function 
+ *
+ *            module
+ *            +-----------------------------+
+ *                                          |
+ *               src------>+--------------->|--->outputA
+ *                         |                |
+ *                         |                |
+ *                         +--------------->|--->outputB
+ *            +-----------------------------+
+ *******************************************************************/
+static 
+void print_spice_subckt_output_short_connections(std::fstream& fp, 
+                                                 const ModuleManager& module_manager,
+                                                 const ModuleId& module_id) {
+  /* Local wires come from the child modules */
+  for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
+    /* We only care the nets that indicate short connections */ 
+    if (false == module_net_include_output_short_connection(module_manager, module_id, module_net)) {
+      continue;
+    }
+    print_spice_subckt_output_short_connection(fp, module_manager, module_id, module_net); 
+  }
+}
+
+/********************************************************************
+ * Write a SPICE instance to a file
+ * This function will name the input and output connections to
+ * the inputs/output or local wires available in the parent module
+ *      
+ *    Parent_module
+ *    +-----------------------------+
+ *    |                             |
+ *    |       +--------------+      |
+ *    |       |              |      |
+ *    |       | child_module |      |
+ *    |       |  [instance]  |      |
+ *    |       +--------------+      |
+ *    |                             |
+ *    +-----------------------------+
+ *
+ *******************************************************************/
+static 
+void write_spice_instance_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& parent_module,
+                                  const ModuleId& child_module,
+                                  const size_t& instance_id) {
+  /* Ensure a valid file stream */
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Print instance name: 
+   * if we have an instance name, use it;
+   * if not, we use a default name <name>_<num_instance_in_parent_module> 
+   */
+  std::string instance_head_line = "X ";
+  if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) {
+    instance_head_line += generate_instance_name(module_manager.module_name(child_module), instance_id);
+  } else {
+    instance_head_line += module_manager.instance_name(parent_module, child_module, instance_id);
+  }
+  instance_head_line += " ";
+  fp << instance_head_line;
+
+  /* Port sequence: global, inout, input, output and clock ports, */
+  bool fit_one_line = true;
+  bool new_line = false;
+  size_t pin_cnt = 0;
+  for (int port_type = ModuleManager::MODULE_GLOBAL_PORT;
+       port_type < ModuleManager::NUM_MODULE_PORT_TYPES;
+       ++port_type) {
+    for (const auto& child_port_id : module_manager.module_port_ids_by_type(child_module, static_cast<ModuleManager::e_module_port_type>(port_type))) {
+
+      BasicPort child_port = module_manager.module_port(child_module, child_port_id);
+
+      /* Create the port name and width to be used by the instance */
+      std::vector<BasicPort> instance_ports; 
+      for (size_t child_pin : child_port.pins()) {
+        /* Find the net linked to the pin */
+        ModuleNetId net = module_manager.module_instance_port_net(parent_module, child_module, instance_id, 
+                                                                  child_port_id, child_pin);
+        BasicPort instance_port;
+        if (ModuleNetId::INVALID() == net) {
+          /* We give the same port name as child module, this case happens to global ports */
+          instance_port.set_name(generate_spice_undriven_local_wire_name(module_manager, parent_module, child_module, instance_id, child_port_id));
+          instance_port.set_width(child_pin, child_pin); 
+        } else {
+          /* Find the name for this child port */
+          instance_port = generate_spice_port_for_module_net(module_manager, parent_module, net);
+        }
+
+        if (true == new_line) {
+          std::string port_whitespace(instance_head_line.length() - 2, ' ');
+          fp << "+ " << port_whitespace;
+        }
+ 
+        if (0 != pin_cnt) {
+          write_space_to_file(fp, 1);
+        }
+        
+        VTR_ASSERT(1 == instance_port.get_width());
+
+        /* For single-bit port,
+         * we can print the port name directly
+         */
+        bool omit_pin_zero = false;
+        if ((1 == instance_port.pins().size())
+           && (0 == instance_port.get_lsb())) {
+          omit_pin_zero = true;
+        }
+
+        fp << generate_spice_port(instance_port, omit_pin_zero);
+
+        /* Increase the counter */
+        pin_cnt++;
+
+        /* Currently we limit 10 ports per line to keep a clean netlist */
+        new_line = false;
+        if (10 == pin_cnt) {
+          pin_cnt = 0;
+          fp << std::endl;
+          new_line = true;
+          fit_one_line = false;
+        }
+      } 
+    }
+  }
+
+  /* Print module name: 
+   * if port print cannot fit one line, we create a new line for the module for a clean format
+   */
+  if (false == fit_one_line) {
+    fp << std::endl;
+    fp << "+";
+  }
+  write_space_to_file(fp, 1);
+  fp << module_manager.module_name(child_module);
+  
+  /* Print an end to the instance */
+  fp << std::endl;
+}
+
+/********************************************************************
+ * Write a SPICE sub-circuit to a file
+ * This is a key function, maybe most frequently called in our SPICE writer
+ * Note that file stream must be valid 
+ *******************************************************************/
+void write_spice_subckt_to_file(std::fstream& fp,
+                                  const ModuleManager& module_manager,
+                                  const ModuleId& module_id) {
+
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* Ensure we have a valid module_id */
+  VTR_ASSERT(module_manager.valid_module_id(module_id)); 
+
+  /* Print module declaration */
+  print_spice_subckt_definition(fp, module_manager, module_id);
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+
+  /* Print local connection (from module inputs to output! */
+  print_spice_comment(fp, std::string("BEGIN Local short connections"));
+  print_spice_subckt_local_short_connections(fp, module_manager, module_id);
+  print_spice_comment(fp, std::string("END Local short connections"));
+
+  print_spice_comment(fp, std::string("BEGIN Local output short connections"));
+  print_spice_subckt_output_short_connections(fp, module_manager, module_id);
+ 
+  print_spice_comment(fp, std::string("END Local output short connections"));
+  /* Print an empty line as splitter */
+  fp << std::endl;
+
+  /* Print instances */
+  for (ModuleId child_module : module_manager.child_modules(module_id)) {
+    for (size_t instance : module_manager.child_module_instances(module_id, child_module)) {
+      /* Print an instance */
+      write_spice_instance_to_file(fp, module_manager, module_id, child_module, instance); 
+      /* Print an empty line as splitter */
+      fp << std::endl;
+    }
+  }
+
+  /* Print an end for the module */
+  print_spice_subckt_end(fp, module_manager.module_name(module_id)); 
+
+  /* Print an empty line as splitter */
+  fp << std::endl;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_subckt_writer.h b/openfpga/src/fpga_spice/spice_subckt_writer.h
new file mode 100644
index 000000000..f47e3915f
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_subckt_writer.h
@@ -0,0 +1,23 @@
+#ifndef SPICE_SUBCKT_WRITER_H
+#define SPICE_SUBCKT_WRITER_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_spice_subckt_to_file(std::fstream& fp,
+                                const ModuleManager& module_manager,
+                                const ModuleId& module_id);
+
+} /* end namespace openfpga */
+
+#endif

From c7e3d97d1b2b3a99fd39a6f5220e359fbd784a92 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 11:19:06 -0600
Subject: [PATCH 094/148] [FPGA-SPICE] Add supply voltage generator

---
 openfpga/src/fpga_spice/spice_constants.h     |  1 +
 .../src/fpga_spice/spice_essential_gates.cpp  | 87 +++++++++++++++++++
 .../src/fpga_spice/spice_essential_gates.h    |  4 +
 openfpga/src/fpga_spice/spice_submodule.cpp   | 43 ++++++++-
 4 files changed, 134 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 48482d703..ab5991de3 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -8,6 +8,7 @@ constexpr char* SPICE_NETLIST_FILE_POSTFIX = ".sp";
 constexpr char* TRANSISTOR_WRAPPER_POSTFIX = "_wrapper";
 
 constexpr char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
+constexpr char* SUPPLY_WRAPPER_SPICE_FILE_NAME = "supply_wrapper.sp";
 
 constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
 constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index eafe37a24..889e9d8c1 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -18,6 +18,7 @@
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
+#include "openfpga_naming.h"
 #include "circuit_library_utils.h"
 
 #include "spice_constants.h"
@@ -31,6 +32,92 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/************************************************
+ * Generate the SPICE netlist for a constant generator,
+ * i.e., either VDD or GND
+ ***********************************************/
+static 
+void print_spice_supply_wrapper_subckt(const ModuleManager& module_manager, 
+                                       std::fstream& fp, 
+                                       const size_t& const_value) {
+  /* Find the module in module manager */
+  std::string module_name = generate_const_value_module_name(const_value);
+  ModuleId const_val_module = module_manager.find_module(module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(const_val_module));
+
+  /* Ensure a valid file handler*/
+  VTR_ASSERT(true == valid_file_stream(fp));
+
+  /* dump module definition + ports */
+  print_spice_subckt_definition(fp, module_manager, const_val_module);
+  /* Finish dumping ports */
+
+  /* Find the only output*/
+  for (const ModulePortId& module_port_id : module_manager.module_ports(const_val_module)) {
+    BasicPort module_port = module_manager.module_port(const_val_module, module_port_id);
+    for (const auto& pin : module_port.pins()) {
+      BasicPort spice_pin(module_port.get_name(), pin, pin);
+      std::string const_pin_name = std::string(SPICE_SUBCKT_VDD_PORT_NAME);
+      if (0 == const_value) {
+        const_pin_name = std::string(SPICE_SUBCKT_GND_PORT_NAME);
+      } else {
+        VTR_ASSERT(1 == const_value);
+      }
+         
+      print_spice_short_connection(fp,
+                                   generate_spice_port(spice_pin, true),
+                                   const_pin_name);
+    }
+  }
+  
+  /* Put an end to the SPICE subcircuit */
+  print_spice_subckt_end(fp, module_name);
+}
+
+/********************************************************************
+ * Create supply voltage wrappers
+ * The wrappers are used for constant inputs of routing multiplexers
+ *
+ *******************************************************************/
+int print_spice_supply_wrappers(NetlistManager& netlist_manager,
+                                const ModuleManager& module_manager,
+                                const std::string& submodule_dir) {
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Create file stream */
+  std::string spice_fname = submodule_dir + std::string(SUPPLY_WRAPPER_SPICE_FILE_NAME);
+  
+  std::fstream fp;
+  
+  /* Create the file stream */
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+  /* Check if the file stream if valid or not */
+  check_file_stream(spice_fname.c_str(), fp); 
+  
+  /* Create file */
+  VTR_LOG("Generating SPICE netlist '%s' for voltage supply wrappers...",
+          spice_fname.c_str());
+  
+  print_spice_file_header(fp, std::string("Voltage Supply Wrappers"));
+
+  /* VDD */
+  print_spice_supply_wrapper_subckt(module_manager, fp, 0);
+  /* GND */
+  print_spice_supply_wrapper_subckt(module_manager, fp, 1);
+
+  /* Close file handler*/
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
+
+  VTR_LOG("Done\n");
+
+  return status;
+}
+
 /********************************************************************
  * Generate the SPICE netlist for essential gates:
  * - inverters and their templates
diff --git a/openfpga/src/fpga_spice/spice_essential_gates.h b/openfpga/src/fpga_spice/spice_essential_gates.h
index 0fbd1895d..dc40a2531 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.h
+++ b/openfpga/src/fpga_spice/spice_essential_gates.h
@@ -18,6 +18,10 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+int print_spice_supply_wrappers(NetlistManager& netlist_manager,
+                                const ModuleManager& module_manager,
+                                const std::string& submodule_dir);
+
 int print_spice_essential_gates(NetlistManager& netlist_manager,
                                 const ModuleManager& module_manager,
                                 const CircuitLibrary& circuit_lib,
diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp
index ad72e8515..a0c93de1b 100644
--- a/openfpga/src/fpga_spice/spice_submodule.cpp
+++ b/openfpga/src/fpga_spice/spice_submodule.cpp
@@ -25,7 +25,7 @@ namespace openfpga {
  * 2. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
  * 3. TODO: Routing multiplexers
  * 4. TODO: Local encoders for routing multiplexers
- * 5. TODO: Wires
+ * 5. Wires
  * 6. TODO: Configuration memory blocks
  ********************************************************************/
 int print_spice_submodule(NetlistManager& netlist_manager,
@@ -35,10 +35,32 @@ int print_spice_submodule(NetlistManager& netlist_manager,
 
   int status = CMD_EXEC_SUCCESS;
 
+  /* Transistor wrapper */
   status = print_spice_transistor_wrapper(netlist_manager,
                                           openfpga_arch.tech_lib,
                                           submodule_dir);
 
+  /* Error out if fatal errors have been reported */
+  if (CMD_EXEC_SUCCESS != status) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Constant modules: VDD and GND */
+  status = print_spice_supply_wrappers(netlist_manager,
+                                       module_manager,
+                                       submodule_dir);
+
+  /* Error out if fatal errors have been reported */
+  if (CMD_EXEC_SUCCESS != status) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Logic gates: 
+   *   - AND/OR, 
+   *   - inverter, buffer
+   *   - transmission-gate/pass-transistor
+   *   - wires
+   */
   status = print_spice_essential_gates(netlist_manager,
                                        module_manager,
                                        openfpga_arch.circuit_lib,
@@ -46,6 +68,25 @@ int print_spice_submodule(NetlistManager& netlist_manager,
                                        openfpga_arch.circuit_tech_binding,
                                        submodule_dir);
 
+  /* Error out if fatal errors have been reported */
+  if (CMD_EXEC_SUCCESS != status) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
+  /* Routing multiplexers */
+  /*
+  status = print_spice_submodule_muxes(netlist_manager,
+                                       module_manager,
+                                       mux_lib,
+                                       openfpga_arch.circuit_lib,
+                                       submodule_dir);
+   */
+
+  /* Error out if fatal errors have been reported */
+  if (CMD_EXEC_SUCCESS != status) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
   return status;
 }
 

From 0f9fce92b245f7bbe506a5c7e614d9a0f939301f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 11:49:02 -0600
Subject: [PATCH 095/148] [FPGA-SPICE] Add SPICE writer for routing
 multiplexers

---
 openfpga/src/base/openfpga_spice.cpp        |   1 +
 openfpga/src/fpga_spice/spice_api.cpp       |   2 +
 openfpga/src/fpga_spice/spice_api.h         |   2 +
 openfpga/src/fpga_spice/spice_constants.h   |   4 +
 openfpga/src/fpga_spice/spice_mux.cpp       | 189 ++++++++++++++++++++
 openfpga/src/fpga_spice/spice_mux.h         |  31 ++++
 openfpga/src/fpga_spice/spice_submodule.cpp |   6 +-
 openfpga/src/fpga_spice/spice_submodule.h   |   2 +
 8 files changed, 234 insertions(+), 3 deletions(-)
 create mode 100644 openfpga/src/fpga_spice/spice_mux.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_mux.h

diff --git a/openfpga/src/base/openfpga_spice.cpp b/openfpga/src/base/openfpga_spice.cpp
index 4ef4058ee..e47acba3a 100644
--- a/openfpga/src/base/openfpga_spice.cpp
+++ b/openfpga/src/base/openfpga_spice.cpp
@@ -40,6 +40,7 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx,
   status = fpga_fabric_spice(openfpga_ctx.module_graph(),
                              openfpga_ctx.mutable_spice_netlists(),
                              openfpga_ctx.arch(),
+                             openfpga_ctx.mux_lib(),
                              options);
 
   return status;
diff --git a/openfpga/src/fpga_spice/spice_api.cpp b/openfpga/src/fpga_spice/spice_api.cpp
index 658d43851..299a62950 100644
--- a/openfpga/src/fpga_spice/spice_api.cpp
+++ b/openfpga/src/fpga_spice/spice_api.cpp
@@ -40,6 +40,7 @@ namespace openfpga {
 int fpga_fabric_spice(const ModuleManager& module_manager,
                       NetlistManager& netlist_manager,
                       const Arch& openfpga_arch,
+                      const MuxLibrary& mux_lib,
                       const FabricSpiceOption& options) {
 
   vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n");
@@ -73,6 +74,7 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
   status = print_spice_submodule(netlist_manager,
                                  module_manager,
                                  openfpga_arch,
+                                 mux_lib,
                                  submodule_dir_path);
  
   if (CMD_EXEC_SUCCESS != status) {
diff --git a/openfpga/src/fpga_spice/spice_api.h b/openfpga/src/fpga_spice/spice_api.h
index cf1ce5a0a..4ab8994bc 100644
--- a/openfpga/src/fpga_spice/spice_api.h
+++ b/openfpga/src/fpga_spice/spice_api.h
@@ -10,6 +10,7 @@
 #include "netlist_manager.h"
 #include "module_manager.h"
 #include "openfpga_arch.h"
+#include "mux_library.h"
 #include "fabric_spice_options.h"
 
 /********************************************************************
@@ -22,6 +23,7 @@ namespace openfpga {
 int fpga_fabric_spice(const ModuleManager& module_manager,
                       NetlistManager& netlist_manager,
                       const Arch& openfpga_arch,
+                      const MuxLibrary& mux_lib,
                       const FabricSpiceOption& options);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index ab5991de3..774591d02 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -9,8 +9,12 @@ constexpr char* TRANSISTOR_WRAPPER_POSTFIX = "_wrapper";
 
 constexpr char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
 constexpr char* SUPPLY_WRAPPER_SPICE_FILE_NAME = "supply_wrapper.sp";
+constexpr char* MUXES_SPICE_FILE_NAME = "muxes.sp";
 
 constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
 constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
 
+constexpr char* SPICE_MUX_BASIS_POSTFIX = "_basis";
+constexpr char* SPICE_MEM_POSTFIX = "_mem";
+
 #endif
diff --git a/openfpga/src/fpga_spice/spice_mux.cpp b/openfpga/src/fpga_spice/spice_mux.cpp
new file mode 100644
index 000000000..b1436d57e
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_mux.cpp
@@ -0,0 +1,189 @@
+/***********************************************
+ * This file includes functions to generate
+ * SPICE subcircuits for multiplexers.
+ * including both fundamental submodules
+ * such as a branch in a multiplexer 
+ * and the full multiplexer
+ **********************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+/* Headers from readarcopenfpga library */
+#include "circuit_types.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "mux_utils.h"
+#include "circuit_library_utils.h"
+#include "decoder_library_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_subckt_writer.h"
+#include "spice_mux.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/***********************************************
+ * Generate SPICE modeling for an branch circuit 
+ * for a multiplexer with the given size 
+ **********************************************/
+static 
+void generate_spice_mux_branch_subckt(const ModuleManager& module_manager,
+                                      const CircuitLibrary& circuit_lib, 
+                                      std::fstream& fp, 
+                                      const CircuitModelId& mux_model, 
+                                      const size_t& mux_size, 
+                                      const MuxGraph& mux_graph) {
+  std::string module_name = generate_mux_branch_subckt_name(circuit_lib, mux_model, mux_size, mux_graph.num_inputs(), SPICE_MUX_BASIS_POSTFIX);
+
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS: {
+    /* Skip module writing if the branch subckt is a standard cell! */
+    if (true == circuit_lib.valid_model_id(circuit_lib.model(module_name))) {
+      /* This model must be a MUX2 gate */
+      VTR_ASSERT(CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_lib.model(module_name)));
+      VTR_ASSERT(CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(circuit_lib.model(module_name)));
+      break;
+    }
+    /* Structural verilog can be easily generated by module writer */
+    ModuleId mux_module = module_manager.find_module(module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+    write_spice_subckt_to_file(fp, module_manager, mux_module);
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+    break;
+  }
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* TODO: RRAM-based Multiplexer SPICE module generation */
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "RRAM multiplexer '%s' is not supported yet\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology of multiplexer '%s'\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+/***********************************************
+ * Generate SPICE modeling for a multiplexer 
+ * with the given graph-level description
+ **********************************************/
+static 
+void generate_spice_mux_subckt(const ModuleManager& module_manager,
+                               const CircuitLibrary& circuit_lib, 
+                               std::fstream& fp, 
+                               const CircuitModelId& mux_model, 
+                               const MuxGraph& mux_graph) {
+  std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                     find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                     std::string(""));
+ 
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS: {
+    /* Use Verilog writer to print the module to file */
+    ModuleId mux_module = module_manager.find_module(module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mux_module));
+    write_spice_subckt_to_file(fp, module_manager, mux_module);
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+    break;
+  }
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* TODO: RRAM-based Multiplexer SPICE module generation */
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "RRAM multiplexer '%s' is not supported yet\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology of multiplexer '%s'\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+/***********************************************
+ * Generate SPICE subcircuits for all the unique
+ * multiplexers in the FPGA device
+ **********************************************/
+int print_spice_submodule_muxes(NetlistManager& netlist_manager,
+                                const ModuleManager& module_manager,
+                                const MuxLibrary& mux_lib,
+                                const CircuitLibrary& circuit_lib,
+                                const std::string& submodule_dir) {
+  int status = CMD_EXEC_SUCCESS;
+
+  std::string spice_fname(submodule_dir + std::string(MUXES_SPICE_FILE_NAME));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Writing SPICE netlist for Multiplexers '%s' ...",
+          spice_fname.c_str()); 
+
+  print_spice_file_header(fp, "Multiplexers"); 
+
+  /* Generate basis sub-circuit for unique branches shared by the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* Create a mux graph for the branch circuit */
+    std::vector<MuxGraph> branch_mux_graphs = mux_graph.build_mux_branch_graphs();
+    /* Create branch circuits, which are N:1 one-level or 2:1 tree-like MUXes */
+    for (auto branch_mux_graph : branch_mux_graphs) {
+      generate_spice_mux_branch_subckt(module_manager, circuit_lib, fp, mux_circuit_model, 
+                                       find_mux_num_datapath_inputs(circuit_lib, mux_circuit_model, mux_graph.num_inputs()), 
+                                       branch_mux_graph);
+    }
+  }
+
+  /* Generate unique Verilog modules for the multiplexers */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_circuit_model = mux_lib.mux_circuit_model(mux); 
+    /* Create MUX circuits */
+    generate_spice_mux_subckt(module_manager, circuit_lib, fp, mux_circuit_model, mux_graph);
+  }
+
+  /* Close the file stream */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
+
+  VTR_LOG("Done\n");
+
+  return status;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_mux.h b/openfpga/src/fpga_spice/spice_mux.h
new file mode 100644
index 000000000..a7658667e
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_mux.h
@@ -0,0 +1,31 @@
+#ifndef SPICE_MUX_H
+#define SPICE_MUX_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <vector>
+
+#include "circuit_library.h"
+#include "mux_graph.h"
+#include "mux_library.h"
+#include "module_manager.h"
+#include "netlist_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_submodule_muxes(NetlistManager& netlist_manager,
+                                const ModuleManager& module_manager,
+                                const MuxLibrary& mux_lib,
+                                const CircuitLibrary& circuit_lib,
+                                const std::string& submodule_dir);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp
index a0c93de1b..4e7505b60 100644
--- a/openfpga/src/fpga_spice/spice_submodule.cpp
+++ b/openfpga/src/fpga_spice/spice_submodule.cpp
@@ -1,5 +1,5 @@
 /*********************************************************************
- * This file includes top-level function to generate Spice primitive modules
+ * This file includes top-level function to generate SPICE primitive modules
  * and print them to files
  ********************************************************************/
 
@@ -12,6 +12,7 @@
 
 #include "spice_transistor_wrapper.h"
 #include "spice_essential_gates.h"
+#include "spice_mux.h"
 
 #include "spice_constants.h"
 #include "spice_submodule.h"
@@ -31,6 +32,7 @@ namespace openfpga {
 int print_spice_submodule(NetlistManager& netlist_manager,
                           const ModuleManager& module_manager,
                           const Arch& openfpga_arch,
+                          const MuxLibrary& mux_lib,
                           const std::string& submodule_dir) {
 
   int status = CMD_EXEC_SUCCESS;
@@ -74,13 +76,11 @@ int print_spice_submodule(NetlistManager& netlist_manager,
   }
 
   /* Routing multiplexers */
-  /*
   status = print_spice_submodule_muxes(netlist_manager,
                                        module_manager,
                                        mux_lib,
                                        openfpga_arch.circuit_lib,
                                        submodule_dir);
-   */
 
   /* Error out if fatal errors have been reported */
   if (CMD_EXEC_SUCCESS != status) {
diff --git a/openfpga/src/fpga_spice/spice_submodule.h b/openfpga/src/fpga_spice/spice_submodule.h
index 27a49de87..551fd772e 100644
--- a/openfpga/src/fpga_spice/spice_submodule.h
+++ b/openfpga/src/fpga_spice/spice_submodule.h
@@ -7,6 +7,7 @@
 #include "netlist_manager.h"
 #include "module_manager.h"
 #include "openfpga_arch.h"
+#include "mux_library.h"
 
 /********************************************************************
  * Function declaration
@@ -18,6 +19,7 @@ namespace openfpga {
 int print_spice_submodule(NetlistManager& netlist_manager,
                           const ModuleManager& module_manager,
                           const Arch& openfpga_arch,
+                          const MuxLibrary& mux_lib,
                           const std::string& submodule_dir);
 
 } /* end namespace openfpga */

From 6801d260e97ad84fd8018bce431cb56de5c59748 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 11:58:11 -0600
Subject: [PATCH 096/148] [FPGA-SPICE] Add SPICE writer for LUT

---
 openfpga/src/fpga_spice/spice_constants.h   |  1 +
 openfpga/src/fpga_spice/spice_lut.cpp       | 82 +++++++++++++++++++++
 openfpga/src/fpga_spice/spice_lut.h         | 28 +++++++
 openfpga/src/fpga_spice/spice_submodule.cpp | 12 +++
 4 files changed, 123 insertions(+)
 create mode 100644 openfpga/src/fpga_spice/spice_lut.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_lut.h

diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 774591d02..4b983aa42 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -10,6 +10,7 @@ constexpr char* TRANSISTOR_WRAPPER_POSTFIX = "_wrapper";
 constexpr char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
 constexpr char* SUPPLY_WRAPPER_SPICE_FILE_NAME = "supply_wrapper.sp";
 constexpr char* MUXES_SPICE_FILE_NAME = "muxes.sp";
+constexpr char* LUTS_SPICE_FILE_NAME = "luts.sp";
 
 constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
 constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
diff --git a/openfpga/src/fpga_spice/spice_lut.cpp b/openfpga/src/fpga_spice/spice_lut.cpp
new file mode 100644
index 000000000..af8dadda1
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_lut.cpp
@@ -0,0 +1,82 @@
+/********************************************************************
+ * This file includes functions to generate SPICE subcircuits for LUTs
+ ********************************************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_subckt_writer.h"
+#include "spice_lut.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************** 
+ * Print SPICE modules for the Look-Up Tables (LUTs) 
+ * in the circuit library
+ ********************************************************************/
+int print_spice_submodule_luts(NetlistManager& netlist_manager,
+                               const ModuleManager& module_manager,
+                               const CircuitLibrary& circuit_lib,
+                               const std::string& submodule_dir) {
+  int status = CMD_EXEC_SUCCESS;
+
+  std::string spice_fname = submodule_dir + std::string(LUTS_SPICE_FILE_NAME);
+
+  std::fstream fp;
+
+  /* Create the file stream */
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+  /* Check if the file stream if valid or not */
+  check_file_stream(spice_fname.c_str(), fp); 
+
+  /* Create file */
+  VTR_LOG("Writing SPICE netlist for LUTs '%s'...",
+          spice_fname.c_str()); 
+
+  print_spice_file_header(fp, "Look-Up Tables"); 
+
+  /* Search for each LUT circuit model */
+  for (const auto& lut_model : circuit_lib.models()) {
+    /* Bypass user-defined and non-LUT modules */
+    if ( (!circuit_lib.model_circuit_netlist(lut_model).empty()) 
+      || (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) ) {
+      continue;
+    }
+    /* Find the module id */
+    ModuleId lut_module = module_manager.find_module(circuit_lib.model_name(lut_model));
+    VTR_ASSERT(true == module_manager.valid_module_id(lut_module));
+    write_spice_subckt_to_file(fp, module_manager, lut_module);
+  }
+
+  /* Close the file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
+
+  VTR_LOG("Done\n");
+
+  return status;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_lut.h b/openfpga/src/fpga_spice/spice_lut.h
new file mode 100644
index 000000000..5ca3f4368
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_lut.h
@@ -0,0 +1,28 @@
+#ifndef SPICE_LUT_H
+#define SPICE_LUT_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <string>
+
+#include "circuit_library.h"
+#include "module_manager.h"
+#include "netlist_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_submodule_luts(NetlistManager& netlist_manager,
+                               const ModuleManager& module_manager,
+                               const CircuitLibrary& circuit_lib,
+                               const std::string& submodule_dir);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp
index 4e7505b60..714747dce 100644
--- a/openfpga/src/fpga_spice/spice_submodule.cpp
+++ b/openfpga/src/fpga_spice/spice_submodule.cpp
@@ -13,6 +13,7 @@
 #include "spice_transistor_wrapper.h"
 #include "spice_essential_gates.h"
 #include "spice_mux.h"
+#include "spice_lut.h"
 
 #include "spice_constants.h"
 #include "spice_submodule.h"
@@ -87,6 +88,17 @@ int print_spice_submodule(NetlistManager& netlist_manager,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  /* Look-Up Tables */
+  status = print_spice_submodule_luts(netlist_manager,
+                                      module_manager,
+                                      openfpga_arch.circuit_lib,
+                                      submodule_dir);
+
+  /* Error out if fatal errors have been reported */
+  if (CMD_EXEC_SUCCESS != status) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
   return status;
 }
 

From f284f6f8d05cb9b763621d9d5eda4f5a4d0f715a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:03:10 -0600
Subject: [PATCH 097/148] [OPENFPGA LIBRARY] change method names to be
 consistent with FPGA-SPICE needs

---
 .../libarchopenfpga/src/circuit_library.cpp        | 14 +++++++-------
 libopenfpga/libarchopenfpga/src/circuit_library.h  |  8 ++++----
 .../src/read_xml_circuit_library.cpp               |  2 +-
 .../src/write_xml_circuit_library.cpp              |  4 ++--
 openfpga/src/fabric/build_essential_modules.cpp    |  4 ++--
 openfpga/src/fabric/build_wire_modules.cpp         |  2 +-
 openfpga/src/fpga_spice/spice_essential_gates.cpp  |  2 +-
 openfpga/src/fpga_spice/spice_lut.cpp              |  2 +-
 8 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
index 42df84407..bbf9c50c4 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp
@@ -79,11 +79,11 @@ std::string CircuitLibrary::model_verilog_netlist(const CircuitModelId& model_id
   return model_verilog_netlists_[model_id]; 
 }
 
-/* Access the path + file of user-defined circuit netlist of a circuit model */
-std::string CircuitLibrary::model_circuit_netlist(const CircuitModelId& model_id) const {
+/* Access the path + file of user-defined spice netlist of a circuit model */
+std::string CircuitLibrary::model_spice_netlist(const CircuitModelId& model_id) const {
   /* validate the model_id */
   VTR_ASSERT(valid_model_id(model_id));
-  return model_circuit_netlists_[model_id]; 
+  return model_spice_netlists_[model_id]; 
 }
 
 /* Access the is_default flag (check if this is the default circuit model in the type) of a circuit model */
@@ -1132,7 +1132,7 @@ CircuitModelId CircuitLibrary::add_model(const enum e_circuit_model_type& type)
   model_names_.emplace_back();
   model_prefix_.emplace_back();
   model_verilog_netlists_.emplace_back();
-  model_circuit_netlists_.emplace_back();
+  model_spice_netlists_.emplace_back();
   model_is_default_.push_back(false);
   sub_models_.emplace_back();
 
@@ -1226,11 +1226,11 @@ void CircuitLibrary::set_model_verilog_netlist(const CircuitModelId& model_id, c
   return;
 }
 
-/* Set the circuit_netlist of a Circuit Model */
-void CircuitLibrary::set_model_circuit_netlist(const CircuitModelId& model_id, const std::string& circuit_netlist) {
+/* Set the spice_netlist of a Circuit Model */
+void CircuitLibrary::set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist) {
   /* validate the model_id */
   VTR_ASSERT(valid_model_id(model_id));
-  model_circuit_netlists_[model_id] = circuit_netlist;
+  model_spice_netlists_[model_id] = spice_netlist;
   return;
 }
 
diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h
index 5e023c665..bd082f738 100644
--- a/libopenfpga/libarchopenfpga/src/circuit_library.h
+++ b/libopenfpga/libarchopenfpga/src/circuit_library.h
@@ -48,7 +48,7 @@
  *                          It should be the same as user-defined Verilog modules, if it is not auto-generated
  * 4. model_prefix_: the prefix of a circuit model when it is instanciated  
  * 5. verilog_netlist_: specified path and file name of Verilog netlist if a circuit model is not auto-generated
- * 6. circuit_netlist_: specified path and file name of CIRCUIT netlist if a circuit model is not auto-generated
+ * 6. spice_netlist_: specified path and file name of CIRCUIT netlist if a circuit model is not auto-generated
  * 7. is_default_: indicate if the circuit model is the default one among all those in the same type 
  * 8. sub_models_: the sub circuit models included by a circuit model. It is a collection of unique circuit model ids
  *                 found in the CircuitModelId of pass-gate/buffers/port-related circuit models.
@@ -190,7 +190,7 @@ class CircuitLibrary {
     std::string model_name(const CircuitModelId& model_id) const;
     std::string model_prefix(const CircuitModelId& model_id) const;
     std::string model_verilog_netlist(const CircuitModelId& model_id) const;
-    std::string model_circuit_netlist(const CircuitModelId& model_id) const;
+    std::string model_spice_netlist(const CircuitModelId& model_id) const;
     bool model_is_default(const CircuitModelId& model_id) const;
     bool dump_structural_verilog(const CircuitModelId& model_id) const;
     bool dump_explicit_port_map(const CircuitModelId& model_id) const;
@@ -314,7 +314,7 @@ class CircuitLibrary {
     void set_model_name(const CircuitModelId& model_id, const std::string& name);
     void set_model_prefix(const CircuitModelId& model_id, const std::string& prefix);
     void set_model_verilog_netlist(const CircuitModelId& model_id, const std::string& verilog_netlist);
-    void set_model_circuit_netlist(const CircuitModelId& model_id, const std::string& circuit_netlist);
+    void set_model_spice_netlist(const CircuitModelId& model_id, const std::string& spice_netlist);
     void set_model_is_default(const CircuitModelId& model_id, const bool& is_default);
     /* Verilog generator options */ 
     void set_model_dump_structural_verilog(const CircuitModelId& model_id, const bool& dump_structural_verilog);
@@ -499,7 +499,7 @@ class CircuitLibrary {
     vtr::vector<CircuitModelId, std::string> model_names_;
     vtr::vector<CircuitModelId, std::string> model_prefix_;
     vtr::vector<CircuitModelId, std::string> model_verilog_netlists_;
-    vtr::vector<CircuitModelId, std::string> model_circuit_netlists_;
+    vtr::vector<CircuitModelId, std::string> model_spice_netlists_;
     vtr::vector<CircuitModelId, bool> model_is_default_;
 
     /* Submodules that a circuit model contains */
diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
index 0954a0086..36e837814 100644
--- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp
@@ -674,7 +674,7 @@ void read_xml_circuit_model(pugi::xml_node& xml_model,
   circuit_lib.set_model_prefix(model, std::string(prefix_attr));
 
   /* Find a SPICE netlist which is an optional attribute*/
-  circuit_lib.set_model_circuit_netlist(model, get_attribute(xml_model, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
+  circuit_lib.set_model_spice_netlist(model, get_attribute(xml_model, "spice_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
 
   /* Find a Verilog netlist which is an optional attribute*/
   circuit_lib.set_model_verilog_netlist(model, get_attribute(xml_model, "verilog_netlist", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string(""));
diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
index 5dd69ca8e..b141b0fe2 100644
--- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
+++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp
@@ -409,8 +409,8 @@ void write_xml_circuit_model(std::fstream& fp,
   if (true == circuit_lib.dump_structural_verilog(model)) { 
     write_xml_attribute(fp, "dump_structural_verilog", "true"); 
   }
-  if (!circuit_lib.model_circuit_netlist(model).empty()) {
-    write_xml_attribute(fp, "circuit_netlist", circuit_lib.model_circuit_netlist(model).c_str()); 
+  if (!circuit_lib.model_spice_netlist(model).empty()) {
+    write_xml_attribute(fp, "spice_netlist", circuit_lib.model_spice_netlist(model).c_str()); 
   }
   if (!circuit_lib.model_verilog_netlist(model).empty()) {
     write_xml_attribute(fp, "verilog_netlist", circuit_lib.model_verilog_netlist(model).c_str()); 
diff --git a/openfpga/src/fabric/build_essential_modules.cpp b/openfpga/src/fabric/build_essential_modules.cpp
index 481781c5a..19e1a10ea 100644
--- a/openfpga/src/fabric/build_essential_modules.cpp
+++ b/openfpga/src/fabric/build_essential_modules.cpp
@@ -187,7 +187,7 @@ void build_user_defined_modules(ModuleManager& module_manager,
   for (const auto& model : circuit_lib.models()) {
     /* We only care about user-defined models */
     if ( (true == circuit_lib.model_verilog_netlist(model).empty())
-      && (true == circuit_lib.model_circuit_netlist(model).empty()) ) {
+      && (true == circuit_lib.model_spice_netlist(model).empty()) ) {
       continue;
     }
     /* Skip Routing channel wire models because they need a different name. Do it later */
@@ -255,7 +255,7 @@ void rename_primitive_module_port_names(ModuleManager& module_manager,
   for (const CircuitModelId& model : circuit_lib.models()) {
     /* We only care about user-defined models */
     if ( (true == circuit_lib.model_verilog_netlist(model).empty())
-      && (true == circuit_lib.model_circuit_netlist(model).empty()) ) {
+      && (true == circuit_lib.model_spice_netlist(model).empty()) ) {
       continue;
     }
     /* Skip Routing channel wire models because they need a different name. Do it later */
diff --git a/openfpga/src/fabric/build_wire_modules.cpp b/openfpga/src/fabric/build_wire_modules.cpp
index da3b03e23..d505f93e6 100644
--- a/openfpga/src/fabric/build_wire_modules.cpp
+++ b/openfpga/src/fabric/build_wire_modules.cpp
@@ -62,7 +62,7 @@ void build_wire_modules(ModuleManager& module_manager,
   /* Print Verilog models for regular wires*/
   for (const auto& wire_model : circuit_lib.models_by_type(CIRCUIT_MODEL_WIRE)) { 
     /* Bypass user-defined circuit models */
-    if ( (!circuit_lib.model_circuit_netlist(wire_model).empty()) 
+    if ( (!circuit_lib.model_spice_netlist(wire_model).empty()) 
       && (!circuit_lib.model_verilog_netlist(wire_model).empty()) ) {
       continue;
     }
diff --git a/openfpga/src/fpga_spice/spice_essential_gates.cpp b/openfpga/src/fpga_spice/spice_essential_gates.cpp
index 889e9d8c1..301b81de1 100644
--- a/openfpga/src/fpga_spice/spice_essential_gates.cpp
+++ b/openfpga/src/fpga_spice/spice_essential_gates.cpp
@@ -136,7 +136,7 @@ int print_spice_essential_gates(NetlistManager& netlist_manager,
   /* Iterate over the circuit models */
   for (const CircuitModelId& circuit_model : circuit_lib.models()) {
     /* Bypass models require extern netlists */
-    if (!circuit_lib.model_circuit_netlist(circuit_model).empty()) {
+    if (!circuit_lib.model_spice_netlist(circuit_model).empty()) {
       continue;
     }
 
diff --git a/openfpga/src/fpga_spice/spice_lut.cpp b/openfpga/src/fpga_spice/spice_lut.cpp
index af8dadda1..2d68d014b 100644
--- a/openfpga/src/fpga_spice/spice_lut.cpp
+++ b/openfpga/src/fpga_spice/spice_lut.cpp
@@ -56,7 +56,7 @@ int print_spice_submodule_luts(NetlistManager& netlist_manager,
   /* Search for each LUT circuit model */
   for (const auto& lut_model : circuit_lib.models()) {
     /* Bypass user-defined and non-LUT modules */
-    if ( (!circuit_lib.model_circuit_netlist(lut_model).empty()) 
+    if ( (!circuit_lib.model_spice_netlist(lut_model).empty()) 
       || (CIRCUIT_MODEL_LUT != circuit_lib.model_type(lut_model)) ) {
       continue;
     }

From 2fae311c8e6be2f769c7e875e1106c713f01ec34 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:14:34 -0600
Subject: [PATCH 098/148] [FPGA-SPICE] Add SPICE writer for memories

---
 openfpga/src/fpga_spice/spice_constants.h   |   1 +
 openfpga/src/fpga_spice/spice_memory.cpp    | 196 ++++++++++++++++++++
 openfpga/src/fpga_spice/spice_memory.h      |  30 +++
 openfpga/src/fpga_spice/spice_submodule.cpp |  13 ++
 4 files changed, 240 insertions(+)
 create mode 100644 openfpga/src/fpga_spice/spice_memory.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_memory.h

diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 4b983aa42..95e7f00b9 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -11,6 +11,7 @@ constexpr char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
 constexpr char* SUPPLY_WRAPPER_SPICE_FILE_NAME = "supply_wrapper.sp";
 constexpr char* MUXES_SPICE_FILE_NAME = "muxes.sp";
 constexpr char* LUTS_SPICE_FILE_NAME = "luts.sp";
+constexpr char* MEMORIES_SPICE_FILE_NAME = "memories.sp";
 
 constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
 constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
diff --git a/openfpga/src/fpga_spice/spice_memory.cpp b/openfpga/src/fpga_spice/spice_memory.cpp
new file mode 100644
index 000000000..e1da21d28
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_memory.cpp
@@ -0,0 +1,196 @@
+/*********************************************************************
+ * This file includes functions to generate SPICE sub-circuits for 
+ * the memories that are affiliated to multiplexers and other programmable
+ * circuit models, such as IOPADs, LUTs, etc.
+ ********************************************************************/
+#include <string>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+/* Headers from openfpgashell library */
+#include "command_exit_codes.h"
+
+#include "mux_graph.h"
+#include "module_manager.h"
+#include "circuit_library_utils.h"
+#include "mux_utils.h"
+
+#include "openfpga_naming.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_subckt_writer.h"
+#include "spice_memory.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/*********************************************************************
+ * Generate Verilog modules for the memories that are used
+ * by multiplexers  
+ *
+ *            +----------------+
+ * mem_in --->|  Memory Module |---> mem_out
+ *            +----------------+
+ *              |  |  ... |  | 
+ *              v  v      v  v SRAM ports of multiplexer
+ *          +---------------------+
+ *    in--->|  Multiplexer Module |---> out
+ *          +---------------------+
+ ********************************************************************/
+static 
+void print_spice_mux_memory_module(const ModuleManager& module_manager,
+                                   const CircuitLibrary& circuit_lib,
+                                   std::fstream& fp,
+                                   const CircuitModelId& mux_model,
+                                   const MuxGraph& mux_graph) {
+  /* Multiplexers built with different technology is in different organization */
+  switch (circuit_lib.design_tech_type(mux_model)) {
+  case CIRCUIT_MODEL_DESIGN_CMOS: {
+    /* Generate module name */
+    std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model, 
+                                                       find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()), 
+                                                       std::string(SPICE_MEM_POSTFIX));
+    ModuleId mem_module = module_manager.find_module(module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+    /* Write the module content in Verilog format */
+    write_spice_subckt_to_file(fp, module_manager, mem_module);
+
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+    break;
+  }
+  case CIRCUIT_MODEL_DESIGN_RRAM:
+    /* We do not need a memory submodule for RRAM MUX,
+     * RRAM are embedded in the datapath  
+     * TODO: generate local encoders for RRAM-based multiplexers here!!!
+     */ 
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid design technology of multiplexer '%s'\n",
+                   circuit_lib.model_name(mux_model).c_str()); 
+    exit(1);
+  }
+}
+
+/*********************************************************************
+ * Generate Verilog modules for 
+ * the memories that are affiliated to multiplexers and other programmable
+ * circuit models, such as IOPADs, LUTs, etc.
+ *
+ * We keep the memory modules separated from the multiplexers and other 
+ * programmable circuit models, for the sake of supporting
+ * various configuration schemes.
+ * By following such organiztion, the Verilog modules of the circuit models
+ * implements the functionality (circuit logic) only, while the memory Verilog
+ * modules implements the memory circuits as well as configuration protocols.
+ * For example, the local decoders of multiplexers are implemented in the
+ * memory modules. 
+ * Take another example, the memory circuit can implement the scan-chain or 
+ * memory-bank organization for the memories.
+ ********************************************************************/
+int print_spice_submodule_memories(NetlistManager& netlist_manager,
+                                   const ModuleManager& module_manager,
+                                   const MuxLibrary& mux_lib,
+                                   const CircuitLibrary& circuit_lib,
+                                   const std::string& submodule_dir) {
+  int status = CMD_EXEC_SUCCESS;
+
+  /* Plug in with the mux subckt */
+  std::string spice_fname(submodule_dir + std::string(MEMORIES_SPICE_FILE_NAME));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  /* Print out debugging information for if the file is not opened/created properly */
+  VTR_LOG("Writing SPICE netlist for memories '%s' ...",
+          spice_fname.c_str()); 
+
+  print_spice_file_header(fp, "Memories used in FPGA"); 
+
+  /* Create the memory circuits for the multiplexer */
+  for (auto mux : mux_lib.muxes()) {
+    const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
+    CircuitModelId mux_model = mux_lib.mux_circuit_model(mux); 
+    /* Bypass the non-MUX circuit models (i.e., LUTs). 
+     * They should be handled in a different way 
+     * Memory circuits of LUT includes both regular and mode-select ports
+     */
+    if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
+      continue;
+    }
+    /* Create a Verilog module for the memories used by the multiplexer */
+    print_spice_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph);
+  }
+
+  /* Create the memory circuits for non-MUX circuit models.
+   * In this case, the memory modules are designed to interface
+   * the mode-select ports 
+   */
+  for (const auto& model : circuit_lib.models()) {
+    /* Bypass MUXes, they have already been considered */
+    if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) {
+      continue;
+    }
+    /* Bypass those modules without any SRAM ports */
+    std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM, true);
+    if (0 == sram_ports.size()) {
+      continue;
+    }
+    /* Find the name of memory module */
+    /* Get the total number of SRAMs */
+    size_t num_mems = 0; 
+    for (const auto& port : sram_ports) {
+      num_mems += circuit_lib.port_size(port);
+    }
+    /* Get the circuit model for the memory circuit used by the multiplexer */
+    std::vector<CircuitModelId> sram_models;
+    for (const auto& port : sram_ports) {
+      CircuitModelId sram_model = circuit_lib.port_tri_state_model(port);
+      VTR_ASSERT(CircuitModelId::INVALID() != sram_model);
+      /* Found in the vector of sram_models, do not update and go to the next */
+      if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) {
+        continue;
+      }
+      /* sram_model not found in the vector, update the sram_models */
+      sram_models.push_back(sram_model);
+    }
+    /* Should have only 1 SRAM model */
+    VTR_ASSERT( 1 == sram_models.size() );
+  
+    /* Create the module name for the memory block */
+    std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(SPICE_MEM_POSTFIX));
+
+    ModuleId mem_module = module_manager.find_module(module_name);
+    VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
+    /* Write the module content in Verilog format */
+    write_spice_subckt_to_file(fp, module_manager, mem_module);
+
+    /* Add an empty line as a splitter */
+    fp << std::endl;
+  }
+
+  /* Close the file stream */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::SUBMODULE_NETLIST);
+
+  VTR_LOG("Done\n");
+
+  return status;
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_memory.h b/openfpga/src/fpga_spice/spice_memory.h
new file mode 100644
index 000000000..48eaf5651
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_memory.h
@@ -0,0 +1,30 @@
+#ifndef SPICE_MEMORY_H
+#define SPICE_MEMORY_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+
+#include "circuit_library.h"
+#include "mux_graph.h"
+#include "mux_library.h"
+#include "module_manager.h"
+#include "netlist_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+int print_spice_submodule_memories(NetlistManager& netlist_manager,
+                                   const ModuleManager& module_manager,
+                                   const MuxLibrary& mux_lib,
+                                   const CircuitLibrary& circuit_lib,
+                                   const std::string& submodule_dir);
+
+} /* end namespace openfpga */
+
+#endif
diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp
index 714747dce..7fd5564be 100644
--- a/openfpga/src/fpga_spice/spice_submodule.cpp
+++ b/openfpga/src/fpga_spice/spice_submodule.cpp
@@ -14,6 +14,7 @@
 #include "spice_essential_gates.h"
 #include "spice_mux.h"
 #include "spice_lut.h"
+#include "spice_memory.h"
 
 #include "spice_constants.h"
 #include "spice_submodule.h"
@@ -99,6 +100,18 @@ int print_spice_submodule(NetlistManager& netlist_manager,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  /* Memories */
+  status = print_spice_submodule_memories(netlist_manager,
+                                          module_manager,
+                                          mux_lib,
+                                          openfpga_arch.circuit_lib,
+                                          submodule_dir);
+
+  /* Error out if fatal errors have been reported */
+  if (CMD_EXEC_SUCCESS != status) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
   return status;
 }
 

From 0f25b529075ff73aaf1b3774a1c5a50937587ff7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:18:22 -0600
Subject: [PATCH 099/148] [FPGA-Verilog] code format fix

---
 openfpga/src/fpga_spice/spice_submodule.cpp |   8 +-
 openfpga/src/fpga_verilog/verilog_api.cpp   | 327 ++++++++++----------
 2 files changed, 165 insertions(+), 170 deletions(-)

diff --git a/openfpga/src/fpga_spice/spice_submodule.cpp b/openfpga/src/fpga_spice/spice_submodule.cpp
index 7fd5564be..26b166a59 100644
--- a/openfpga/src/fpga_spice/spice_submodule.cpp
+++ b/openfpga/src/fpga_spice/spice_submodule.cpp
@@ -26,10 +26,10 @@ namespace openfpga {
  * Top-level function to generate primitive modules:
  * 1. Transistor wrapper
  * 2. Logic gates: AND/OR, inverter, buffer and transmission-gate/pass-transistor
- * 3. TODO: Routing multiplexers
+ * 3. Routing multiplexers
  * 4. TODO: Local encoders for routing multiplexers
  * 5. Wires
- * 6. TODO: Configuration memory blocks
+ * 6. Configuration memory blocks
  ********************************************************************/
 int print_spice_submodule(NetlistManager& netlist_manager,
                           const ModuleManager& module_manager,
@@ -77,6 +77,8 @@ int print_spice_submodule(NetlistManager& netlist_manager,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  /* TODO: local decoders for routing multiplexers */
+
   /* Routing multiplexers */
   status = print_spice_submodule_muxes(netlist_manager,
                                        module_manager,
@@ -112,6 +114,8 @@ int print_spice_submodule(NetlistManager& netlist_manager,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  /* TODO: architecture decoders */
+
   return status;
 }
 
diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index 7f4c0d9b7..d02ced128 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -33,7 +33,7 @@
 namespace openfpga
 {
 
-  /********************************************************************
+/********************************************************************
  * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation
  * This function will generate
  *  - primitive modules required by the full fabric
@@ -52,97 +52,93 @@ namespace openfpga
  * The only exception now is the user-defined modules.
  * We should think clearly about how to handle them for both Verilog and SPICE generators!
  ********************************************************************/
-  void fpga_fabric_verilog(ModuleManager &module_manager,
-                           NetlistManager &netlist_manager,
-                           const CircuitLibrary &circuit_lib,
-                           const MuxLibrary &mux_lib,
-                           const DecoderLibrary &decoder_lib,
-                           const DeviceContext &device_ctx,
-                           const VprDeviceAnnotation &device_annotation,
-                           const DeviceRRGSB &device_rr_gsb,
-                           const FabricVerilogOption &options)
-  {
+void fpga_fabric_verilog(ModuleManager &module_manager,
+                         NetlistManager &netlist_manager,
+                         const CircuitLibrary &circuit_lib,
+                         const MuxLibrary &mux_lib,
+                         const DecoderLibrary &decoder_lib,
+                         const DeviceContext &device_ctx,
+                         const VprDeviceAnnotation &device_annotation,
+                         const DeviceRRGSB &device_rr_gsb,
+                         const FabricVerilogOption &options) {
 
-    vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
+  vtr::ScopedStartFinishTimer timer("Write Verilog netlists for FPGA fabric\n");
 
-    std::string src_dir_path = format_dir_path(options.output_directory());
+  std::string src_dir_path = format_dir_path(options.output_directory());
 
-    /* Create directories */
-    create_directory(src_dir_path);
+  /* Create directories */
+  create_directory(src_dir_path);
 
-    /* Sub directory under SRC directory to contain all the primitive block netlists */
-    std::string submodule_dir_path = src_dir_path + std::string(DEFAULT_SUBMODULE_DIR_NAME);
-    create_directory(submodule_dir_path);
+  /* Sub directory under SRC directory to contain all the primitive block netlists */
+  std::string submodule_dir_path = src_dir_path + std::string(DEFAULT_SUBMODULE_DIR_NAME);
+  create_directory(submodule_dir_path);
 
-    /* Sub directory under SRC directory to contain all the logic block netlists */
-    std::string lb_dir_path = src_dir_path + std::string(DEFAULT_LB_DIR_NAME);
-    create_directory(lb_dir_path);
+  /* Sub directory under SRC directory to contain all the logic block netlists */
+  std::string lb_dir_path = src_dir_path + std::string(DEFAULT_LB_DIR_NAME);
+  create_directory(lb_dir_path);
 
-    /* Sub directory under SRC directory to contain all the routing block netlists */
-    std::string rr_dir_path = src_dir_path + std::string(DEFAULT_RR_DIR_NAME);
-    create_directory(rr_dir_path);
+  /* Sub directory under SRC directory to contain all the routing block netlists */
+  std::string rr_dir_path = src_dir_path + std::string(DEFAULT_RR_DIR_NAME);
+  create_directory(rr_dir_path);
 
-    /* Print Verilog files containing preprocessing flags */
-    print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
-                                              options);
+  /* Print Verilog files containing preprocessing flags */
+  print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
+                                            options);
 
-    /* Generate primitive Verilog modules, which are corner stones of FPGA fabric
-   * Note that this function MUST be called before Verilog generation of
-   * core logic (i.e., logic blocks and routing resources) !!!
-   * This is because that this function will add the primitive Verilog modules to
-   * the module manager.
-   * Without the modules in the module manager, core logic generation is not possible!!!
-   */
-    print_verilog_submodule(module_manager, netlist_manager,
-                            mux_lib, decoder_lib, circuit_lib,
-                            submodule_dir_path,
-                            options);
+  /* Generate primitive Verilog modules, which are corner stones of FPGA fabric
+ * Note that this function MUST be called before Verilog generation of
+ * core logic (i.e., logic blocks and routing resources) !!!
+ * This is because that this function will add the primitive Verilog modules to
+ * the module manager.
+ * Without the modules in the module manager, core logic generation is not possible!!!
+ */
+  print_verilog_submodule(module_manager, netlist_manager,
+                          mux_lib, decoder_lib, circuit_lib,
+                          submodule_dir_path,
+                          options);
 
-    /* Generate routing blocks */
-    if (true == options.compress_routing())
-    {
-      print_verilog_unique_routing_modules(netlist_manager,
-                                           const_cast<const ModuleManager &>(module_manager),
-                                           device_rr_gsb,
-                                           rr_dir_path,
-                                           options.explicit_port_mapping());
-    }
-    else
-    {
-      VTR_ASSERT(false == options.compress_routing());
-      print_verilog_flatten_routing_modules(netlist_manager,
-                                            const_cast<const ModuleManager &>(module_manager),
-                                            device_rr_gsb,
-                                            rr_dir_path,
-                                            options.explicit_port_mapping());
-    }
-
-    /* Generate grids */
-    print_verilog_grids(netlist_manager,
-                        const_cast<const ModuleManager &>(module_manager),
-                        device_ctx, device_annotation,
-                        lb_dir_path,
-                        options.explicit_port_mapping(),
-                        options.verbose_output());
-
-    /* Generate FPGA fabric */
-    print_verilog_top_module(netlist_manager,
-                             const_cast<const ModuleManager &>(module_manager),
-                             src_dir_path,
-                             options.explicit_port_mapping());
-
-    /* Generate an netlist including all the fabric-related netlists */
-    print_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
-                                 src_dir_path,
-                                 circuit_lib);
-
-    /* Given a brief stats on how many Verilog modules have been written to files */
-    VTR_LOGV(options.verbose_output(),
-             "Written %lu Verilog modules in total\n",
-             module_manager.num_modules());
+  /* Generate routing blocks */
+  if (true == options.compress_routing()) {
+    print_verilog_unique_routing_modules(netlist_manager,
+                                         const_cast<const ModuleManager &>(module_manager),
+                                         device_rr_gsb,
+                                         rr_dir_path,
+                                         options.explicit_port_mapping());
+  } else {
+    VTR_ASSERT(false == options.compress_routing());
+    print_verilog_flatten_routing_modules(netlist_manager,
+                                          const_cast<const ModuleManager &>(module_manager),
+                                          device_rr_gsb,
+                                          rr_dir_path,
+                                          options.explicit_port_mapping());
   }
 
-  /********************************************************************
+  /* Generate grids */
+  print_verilog_grids(netlist_manager,
+                      const_cast<const ModuleManager &>(module_manager),
+                      device_ctx, device_annotation,
+                      lb_dir_path,
+                      options.explicit_port_mapping(),
+                      options.verbose_output());
+
+  /* Generate FPGA fabric */
+  print_verilog_top_module(netlist_manager,
+                           const_cast<const ModuleManager &>(module_manager),
+                           src_dir_path,
+                           options.explicit_port_mapping());
+
+  /* Generate an netlist including all the fabric-related netlists */
+  print_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
+                               src_dir_path,
+                               circuit_lib);
+
+  /* Given a brief stats on how many Verilog modules have been written to files */
+  VTR_LOGV(options.verbose_output(),
+           "Written %lu Verilog modules in total\n",
+           module_manager.num_modules());
+}
+
+/********************************************************************
  * A top-level function of FPGA-Verilog which focuses on fabric Verilog generation
  * This function will generate
  *  - A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark
@@ -151,100 +147,95 @@ namespace openfpga
  *    This testbench is created for quick verification and formal verification purpose.
  *  - Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
  ********************************************************************/
-  void fpga_verilog_testbench(const ModuleManager &module_manager,
-                              const BitstreamManager &bitstream_manager,
-                              const FabricBitstream &fabric_bitstream,
-                              const AtomContext &atom_ctx,
-                              const PlacementContext &place_ctx,
-                              const IoLocationMap &io_location_map,
-                              const VprNetlistAnnotation &netlist_annotation,
-                              const CircuitLibrary &circuit_lib,
-                              const SimulationSetting &simulation_setting,
-                              const e_config_protocol_type &config_protocol_type,
-                              const VerilogTestbenchOption &options)
-  {
+void fpga_verilog_testbench(const ModuleManager &module_manager,
+                            const BitstreamManager &bitstream_manager,
+                            const FabricBitstream &fabric_bitstream,
+                            const AtomContext &atom_ctx,
+                            const PlacementContext &place_ctx,
+                            const IoLocationMap &io_location_map,
+                            const VprNetlistAnnotation &netlist_annotation,
+                            const CircuitLibrary &circuit_lib,
+                            const SimulationSetting &simulation_setting,
+                            const e_config_protocol_type &config_protocol_type,
+                            const VerilogTestbenchOption &options) {
 
-    vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n");
+  vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n");
 
-    std::string src_dir_path = format_dir_path(options.output_directory());
+  std::string src_dir_path = format_dir_path(options.output_directory());
 
-    std::string netlist_name = atom_ctx.nlist.netlist_name();
+  std::string netlist_name = atom_ctx.nlist.netlist_name();
 
-    /* Create directories */
-    create_directory(src_dir_path);
+  /* Create directories */
+  create_directory(src_dir_path);
 
-    /* TODO: check if this works here. This function was in fabric generator */
-    print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
-                                                 options);
+  /* TODO: check if this works here. This function was in fabric generator */
+  print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
+                                               options);
 
-    /* Collect global ports from the circuit library:
-   * TODO: should we place this in the OpenFPGA context?
-   */
-    std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(circuit_lib);
+  /* Collect global ports from the circuit library:
+ * TODO: should we place this in the OpenFPGA context?
+ */
+  std::vector<CircuitPortId> global_ports = find_circuit_library_global_ports(circuit_lib);
 
-    /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */
-    if (true == options.print_formal_verification_top_netlist())
-    {
-      std::string formal_verification_top_netlist_file_path = src_dir_path + netlist_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX);
-      print_verilog_preconfig_top_module(module_manager, bitstream_manager,
-                                         circuit_lib, global_ports,
-                                         atom_ctx, place_ctx, io_location_map,
-                                         netlist_annotation,
-                                         netlist_name,
-                                         formal_verification_top_netlist_file_path,
-                                         options.explicit_port_mapping());
-    }
-
-    if (true == options.print_preconfig_top_testbench())
-    {
-      /* Generate top-level testbench using random vectors */
-      std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
-      print_verilog_random_top_testbench(netlist_name,
-                                         random_top_testbench_file_path,
-                                         atom_ctx,
-                                         netlist_annotation,
-                                         simulation_setting,
-                                         options.explicit_port_mapping());
-    }
-
-    /* Generate full testbench for verification, including configuration phase and operating phase */
-    if (true == options.print_top_testbench())
-    {
-      std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
-      print_verilog_top_testbench(module_manager,
-                                  bitstream_manager, fabric_bitstream,
-                                  config_protocol_type,
-                                  circuit_lib, global_ports,
-                                  atom_ctx, place_ctx, io_location_map,
-                                  netlist_annotation,
-                                  netlist_name,
-                                  top_testbench_file_path,
-                                  simulation_setting,
-                                  options.fast_configuration(),
-                                  options.explicit_port_mapping());
-    }
-
-    /* Generate exchangeable files which contains simulation settings */
-    if (true == options.print_simulation_ini())
-    {
-      std::string simulation_ini_file_name = options.simulation_ini_path();
-      VTR_ASSERT(true != options.simulation_ini_path().empty());
-      print_verilog_simulation_info(simulation_ini_file_name,
-                                    netlist_name,
-                                    src_dir_path,
-                                    atom_ctx, place_ctx, io_location_map,
-                                    module_manager,
-                                    config_protocol_type,
-                                    bitstream_manager.num_bits(),
-                                    simulation_setting.num_clock_cycles(),
-                                    simulation_setting.programming_clock_frequency(),
-                                    simulation_setting.operating_clock_frequency());
-    }
-
-    /* Generate a Verilog file including all the netlists that have been generated */
-    print_include_netlists(src_dir_path,
-                           netlist_name,
-                           options.reference_benchmark_file_path());
+  /* Generate wrapper module for FPGA fabric (mapped by the input benchmark and pre-configured testbench for verification */
+  if (true == options.print_formal_verification_top_netlist()) {
+    std::string formal_verification_top_netlist_file_path = src_dir_path + netlist_name + std::string(FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX);
+    print_verilog_preconfig_top_module(module_manager, bitstream_manager,
+                                       circuit_lib, global_ports,
+                                       atom_ctx, place_ctx, io_location_map,
+                                       netlist_annotation,
+                                       netlist_name,
+                                       formal_verification_top_netlist_file_path,
+                                       options.explicit_port_mapping());
   }
 
+  if (true == options.print_preconfig_top_testbench()) {
+    /* Generate top-level testbench using random vectors */
+    std::string random_top_testbench_file_path = src_dir_path + netlist_name + std::string(RANDOM_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
+    print_verilog_random_top_testbench(netlist_name,
+                                       random_top_testbench_file_path,
+                                       atom_ctx,
+                                       netlist_annotation,
+                                       simulation_setting,
+                                       options.explicit_port_mapping());
+  }
+
+  /* Generate full testbench for verification, including configuration phase and operating phase */
+  if (true == options.print_top_testbench()) {
+    std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
+    print_verilog_top_testbench(module_manager,
+                                bitstream_manager, fabric_bitstream,
+                                config_protocol_type,
+                                circuit_lib, global_ports,
+                                atom_ctx, place_ctx, io_location_map,
+                                netlist_annotation,
+                                netlist_name,
+                                top_testbench_file_path,
+                                simulation_setting,
+                                options.fast_configuration(),
+                                options.explicit_port_mapping());
+  }
+
+  /* Generate exchangeable files which contains simulation settings */
+  if (true == options.print_simulation_ini()) {
+    std::string simulation_ini_file_name = options.simulation_ini_path();
+    VTR_ASSERT(true != options.simulation_ini_path().empty());
+    print_verilog_simulation_info(simulation_ini_file_name,
+                                  netlist_name,
+                                  src_dir_path,
+                                  atom_ctx, place_ctx, io_location_map,
+                                  module_manager,
+                                  config_protocol_type,
+                                  bitstream_manager.num_bits(),
+                                  simulation_setting.num_clock_cycles(),
+                                  simulation_setting.programming_clock_frequency(),
+                                  simulation_setting.operating_clock_frequency());
+  }
+
+  /* Generate a Verilog file including all the netlists that have been generated */
+  print_include_netlists(src_dir_path,
+                         netlist_name,
+                         options.reference_benchmark_file_path());
+}
+
 } /* end namespace openfpga */

From 5e78e91fdf15ca21ddd27c41fd58d3f5146b0f3c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:27:48 -0600
Subject: [PATCH 100/148] [FPGA-SPICE] Add SPICE writer for routing blocks

---
 openfpga/src/base/openfpga_spice.cpp      |   1 +
 openfpga/src/fpga_spice/spice_api.cpp     |  16 +
 openfpga/src/fpga_spice/spice_api.h       |   2 +
 openfpga/src/fpga_spice/spice_constants.h |   4 +
 openfpga/src/fpga_spice/spice_routing.cpp | 346 ++++++++++++++++++++++
 openfpga/src/fpga_spice/spice_routing.h   |  32 ++
 6 files changed, 401 insertions(+)
 create mode 100644 openfpga/src/fpga_spice/spice_routing.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_routing.h

diff --git a/openfpga/src/base/openfpga_spice.cpp b/openfpga/src/base/openfpga_spice.cpp
index e47acba3a..0ddab0c91 100644
--- a/openfpga/src/base/openfpga_spice.cpp
+++ b/openfpga/src/base/openfpga_spice.cpp
@@ -41,6 +41,7 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx,
                              openfpga_ctx.mutable_spice_netlists(),
                              openfpga_ctx.arch(),
                              openfpga_ctx.mux_lib(),
+                             openfpga_ctx.device_rr_gsb(),
                              options);
 
   return status;
diff --git a/openfpga/src/fpga_spice/spice_api.cpp b/openfpga/src/fpga_spice/spice_api.cpp
index 299a62950..852d29a8d 100644
--- a/openfpga/src/fpga_spice/spice_api.cpp
+++ b/openfpga/src/fpga_spice/spice_api.cpp
@@ -16,6 +16,7 @@
 
 #include "spice_constants.h"
 #include "spice_submodule.h"
+#include "spice_routing.h"
 
 /* Header file for this source file */
 #include "spice_api.h"
@@ -41,6 +42,7 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
                       NetlistManager& netlist_manager,
                       const Arch& openfpga_arch,
                       const MuxLibrary& mux_lib,
+                      const DeviceRRGSB &device_rr_gsb,
                       const FabricSpiceOption& options) {
 
   vtr::ScopedStartFinishTimer timer("Write SPICE netlists for FPGA fabric\n");
@@ -81,6 +83,20 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
     return status;
   }
 
+  /* Generate routing blocks */
+  if (true == options.compress_routing()) {
+    print_spice_unique_routing_modules(netlist_manager,
+                                       module_manager,
+                                       device_rr_gsb,
+                                       rr_dir_path);
+  } else {
+    VTR_ASSERT(false == options.compress_routing());
+    print_spice_flatten_routing_modules(netlist_manager,
+                                        module_manager,
+                                        device_rr_gsb,
+                                        rr_dir_path);
+  }
+
   /* Given a brief stats on how many Spice modules have been written to files */
   VTR_LOGV(options.verbose_output(),
            "Written %lu SPICE modules in total\n",
diff --git a/openfpga/src/fpga_spice/spice_api.h b/openfpga/src/fpga_spice/spice_api.h
index 4ab8994bc..2d418432d 100644
--- a/openfpga/src/fpga_spice/spice_api.h
+++ b/openfpga/src/fpga_spice/spice_api.h
@@ -11,6 +11,7 @@
 #include "module_manager.h"
 #include "openfpga_arch.h"
 #include "mux_library.h"
+#include "device_rr_gsb.h"
 #include "fabric_spice_options.h"
 
 /********************************************************************
@@ -24,6 +25,7 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
                       NetlistManager& netlist_manager,
                       const Arch& openfpga_arch,
                       const MuxLibrary& mux_lib,
+                      const DeviceRRGSB &device_rr_gsb,
                       const FabricSpiceOption& options);
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 95e7f00b9..97b1733c2 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -19,4 +19,8 @@ constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
 constexpr char* SPICE_MUX_BASIS_POSTFIX = "_basis";
 constexpr char* SPICE_MEM_POSTFIX = "_mem";
 
+constexpr char* SB_SPICE_FILE_NAME_PREFIX = "sb_";
+constexpr char* LOGICAL_MODULE_SPICE_FILE_NAME_PREFIX = "logical_tile_";
+constexpr char* GRID_SPICE_FILE_NAME_PREFIX = "grid_";
+
 #endif
diff --git a/openfpga/src/fpga_spice/spice_routing.cpp b/openfpga/src/fpga_spice/spice_routing.cpp
new file mode 100644
index 000000000..9c83aef3c
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_routing.cpp
@@ -0,0 +1,346 @@
+/*********************************************************************
+ * This file includes functions that are used for 
+ * SPICE generation of FPGA routing architecture (global routing) 
+ *********************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+/* Include FPGA-Verilog header files*/
+#include "openfpga_naming.h"
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_subckt_writer.h"
+#include "spice_routing.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/******************************************************************** 
+ * Print the sub-circuit of a connection Box (Type: [CHANX|CHANY])
+ * Actually it is very similiar to switch box but
+ * the difference is connection boxes connect Grid INPUT Pins to channels
+ * NOTE: direct connection between CLBs should NOT be included inside this
+ *       module! They should be added in the top-level module as their connection
+ *       is not limited to adjacent CLBs!!!
+ *
+ * Location of a X- and Y-direction Connection Block in FPGA fabric
+ *               +------------+       +-------------+ 
+ *               |            |------>|             |
+ *               |     CLB    |<------| Y-direction |
+ *               |            | ...   |  Connection |
+ *               |            |------>|    Block    |
+ *               +------------+       +-------------+
+ *                 |  ^ ... |            | ^ ... |
+ *                 v  |     v            v |     v
+ *           +-------------------+    +-------------+
+ *       --->|                   |--->|             |
+ *       <---|     X-direction   |<---|    Switch   |                           
+ *        ...|  Connection block |... |    Block    |
+ *       --->|                   |--->|             |
+ *           +-------------------+    +-------------+
+ *
+ *  Internal structure:
+ *  This is an example of a X-direction connection block  
+ *  Note that middle output ports are shorted wire from inputs of routing tracks, 
+ *  which are also the inputs of routing multiplexer of the connection block 
+ *
+ *                      CLB Input Pins
+ *                         (IPINs)
+ *                       ^   ^     ^
+ *                       |   | ... |
+ *              +--------------------------+
+ *              |       ^    ^     ^       |
+ *              |       |    | ... |       |   
+ *              |  +--------------------+  | 
+ *              |  |       routing      |  |
+ *              |  |    multiplexers    |  |
+ *              |  +--------------------+  | 
+ *              |      middle outputs      |
+ *              |    of routing channel    |
+ *              |    ^ ^ ^ ^     ^ ^ ^ ^   |
+ *              |    | | | | ... | | | |   |
+ *     in[0] -->|------------------------->|---> out[0]
+ *    out[1] <--|<-------------------------|<--- in[1]
+ *              |           ...            |
+ *   in[W-2] -->|------------------------->|---> out[W-2]
+ *  out[W-1] <--|<-------------------------|<--- in[W-1]
+ *              +--------------------------+
+ *
+ *  W: routing channel width
+ *              
+ ********************************************************************/
+static 
+void print_spice_routing_connection_box_unique_module(NetlistManager& netlist_manager,
+                                                      const ModuleManager& module_manager, 
+                                                      const std::string& subckt_dir, 
+                                                      const RRGSB& rr_gsb,
+                                                      const t_rr_type& cb_type) {
+  /* Create the netlist */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_cb_x(cb_type), rr_gsb.get_cb_y(cb_type));
+  std::string spice_fname(subckt_dir + generate_connection_block_netlist_name(cb_type, gsb_coordinate, std::string(SPICE_NETLIST_FILE_POSTFIX)));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  print_spice_file_header(fp, std::string("SPICE modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]")); 
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(cb_module));
+
+  /* Write the spice module */
+  write_spice_subckt_to_file(fp, module_manager, cb_module);
+ 
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
+}
+
+/*********************************************************************
+ * Generate the SPICE module for a Switch Box.
+ * A Switch Box module consists of following ports:
+ * 1. Channel Y [x][y] inputs 
+ * 2. Channel X [x+1][y] inputs
+ * 3. Channel Y [x][y-1] outputs
+ * 4. Channel X [x][y] outputs
+ * 5. Grid[x][y+1] Right side outputs pins
+ * 6. Grid[x+1][y+1] Left side output pins
+ * 7. Grid[x+1][y+1] Bottom side output pins
+ * 8. Grid[x+1][y] Top side output pins
+ * 9. Grid[x+1][y] Left side output pins
+ * 10. Grid[x][y] Right side output pins
+ * 11. Grid[x][y] Top side output pins
+ * 12. Grid[x][y+1] Bottom side output pins
+ *
+ * Location of a Switch Box in FPGA fabric:
+ *
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |  [x][y+1]  | [x][y+1] | [x+1][y+1] |
+ *    |            |          |            |
+ *    --------------          --------------
+ *                  ----------
+ *       ChanX      | Switch |     ChanX 
+ *       [x][y]     |   Box  |    [x+1][y]
+ *                  | [x][y] |
+ *                  ----------
+ *    --------------          --------------
+ *    |            |          |            |
+ *    |    Grid    |  ChanY   |    Grid    |
+ *    |   [x][y]   |  [x][y]  |  [x+1][y]  |
+ *    |            |          |            |
+ *    --------------          --------------
+ *
+ * Switch Block pin location map
+ *
+ *                       Grid[x][y+1]   ChanY[x][y+1]  Grid[x+1][y+1] 
+ *                        right_pins  inputs/outputs     left_pins
+ *                            |             ^                |
+ *                            |             |                |
+ *                            v             v                v
+ *                    +-----------------------------------------------+
+ *                    |                                               |
+ *    Grid[x][y+1]    |                                               |    Grid[x+1][y+1]
+ *    bottom_pins---->|                                               |<---- bottom_pins
+ *                    |                                               |
+ * ChanX[x][y]        |              Switch Box [x][y]                |     ChanX[x+1][y]
+ * inputs/outputs<--->|                                               |<---> inputs/outputs
+ *                    |                                               |
+ *    Grid[x][y+1]    |                                               |    Grid[x+1][y+1]
+ *       top_pins---->|                                               |<---- top_pins
+ *                    |                                               |
+ *                    +-----------------------------------------------+
+ *                            ^             ^                ^
+ *                            |             |                |
+ *                            |             v                |
+ *                       Grid[x][y]     ChanY[x][y]      Grid[x+1][y] 
+ *                       right_pins    inputs/outputs      left_pins
+ *
+ *
+ ********************************************************************/
+static 
+void print_spice_routing_switch_box_unique_module(NetlistManager& netlist_manager,
+                                                  const ModuleManager& module_manager, 
+                                                  const std::string& subckt_dir, 
+                                                  const RRGSB& rr_gsb) {
+  /* Create the netlist */
+  vtr::Point<size_t> gsb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y());
+  std::string spice_fname(subckt_dir + generate_routing_block_netlist_name(SB_SPICE_FILE_NAME_PREFIX, gsb_coordinate, std::string(SPICE_NETLIST_FILE_POSTFIX)));
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  print_spice_file_header(fp, std::string("SPICE subcircuits for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]")); 
+
+  /* Create a Verilog Module based on the circuit model, and add to module manager */
+  ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate)); 
+  VTR_ASSERT(true == module_manager.valid_module_id(sb_module));
+
+  /* Write the spice module */
+  write_spice_subckt_to_file(fp, module_manager, sb_module);
+ 
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::ROUTING_MODULE_NETLIST);
+}
+
+/********************************************************************
+ * Iterate over all the connection blocks in a device
+ * and build a module for each of them 
+ *******************************************************************/
+static 
+void print_spice_flatten_connection_block_modules(NetlistManager& netlist_manager,
+                                                  const ModuleManager& module_manager, 
+                                                  const DeviceRRGSB& device_rr_gsb,
+                                                  const std::string& subckt_dir,
+                                                  const t_rr_type& cb_type) {
+  /* Build unique X-direction connection block modules */
+  vtr::Point<size_t> cb_range = device_rr_gsb.get_gsb_range();
+
+  for (size_t ix = 0; ix < cb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < cb_range.y(); ++iy) {
+      /* Check if the connection block exists in the device!
+       * Some of them do NOT exist due to heterogeneous blocks (height > 1) 
+       * We will skip those modules
+       */
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (true != rr_gsb.is_cb_exist(cb_type)) {
+        continue;
+      }
+      print_spice_routing_connection_box_unique_module(netlist_manager, 
+                                                       module_manager,
+                                                       subckt_dir, 
+                                                       rr_gsb, cb_type);
+    }
+  }
+}
+
+/********************************************************************
+ * A top-level function of this file
+ * Print all the modules for global routing architecture of a FPGA fabric
+ * in Verilog format  in a flatten way:
+ *   Each connection block and switch block will be generated as a unique module
+ * Covering:
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *******************************************************************/
+void print_spice_flatten_routing_modules(NetlistManager& netlist_manager,
+                                         const ModuleManager& module_manager,
+                                         const DeviceRRGSB& device_rr_gsb,
+                                         const std::string& subckt_dir) {
+  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
+  std::vector<std::string> netlist_names;
+
+  vtr::Point<size_t> sb_range = device_rr_gsb.get_gsb_range();
+
+  /* Build unique switch block modules */
+  for (size_t ix = 0; ix < sb_range.x(); ++ix) {
+    for (size_t iy = 0; iy < sb_range.y(); ++iy) {
+      const RRGSB& rr_gsb = device_rr_gsb.get_gsb(ix, iy);
+      if (true != rr_gsb.is_sb_exist()) {
+        continue;
+      }
+      print_spice_routing_switch_box_unique_module(netlist_manager,
+                                                   module_manager, 
+                                                   subckt_dir, 
+                                                   rr_gsb);
+    }
+  }
+
+  print_spice_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANX);
+
+  print_spice_flatten_connection_block_modules(netlist_manager, module_manager, device_rr_gsb, subckt_dir, CHANY);
+
+  /*
+  VTR_LOG("Writing header file for routing submodules '%s'...",
+          ROUTING_VERILOG_FILE_NAME);
+  print_spice_netlist_include_header_file(netlist_names,
+                                          subckt_dir.c_str(),
+                                          ROUTING_VERILOG_FILE_NAME);
+  VTR_LOG("Done\n");
+  VTR_LOG("\n");
+   */
+}
+
+
+/********************************************************************
+ * A top-level function of this file
+ * Print all the unique modules for global routing architecture of a FPGA fabric
+ * in Verilog format, including: 
+ * 1. Connection blocks
+ * 2. Switch blocks
+ *
+ * Note: this function SHOULD be called only when 
+ * the option compact_routing_hierarchy is turned on!!!
+ *******************************************************************/
+void print_spice_unique_routing_modules(NetlistManager& netlist_manager,
+                                          const ModuleManager& module_manager,
+                                          const DeviceRRGSB& device_rr_gsb,
+                                          const std::string& subckt_dir) {
+  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
+  std::vector<std::string> netlist_names;
+
+  /* Build unique switch block modules */
+  for (size_t isb = 0; isb < device_rr_gsb.get_num_sb_unique_module(); ++isb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_sb_unique_module(isb);
+    print_spice_routing_switch_box_unique_module(netlist_manager,
+                                                 module_manager,
+                                                 subckt_dir, 
+                                                 unique_mirror);
+  }
+
+  /* Build unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANX); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANX, icb);
+
+    print_spice_routing_connection_box_unique_module(netlist_manager,
+                                                     module_manager,
+                                                     subckt_dir, 
+                                                     unique_mirror, CHANX);
+  }
+
+  /* Build unique X-direction connection block modules */
+  for (size_t icb = 0; icb < device_rr_gsb.get_num_cb_unique_module(CHANY); ++icb) {
+    const RRGSB& unique_mirror = device_rr_gsb.get_cb_unique_module(CHANY, icb);
+
+    print_spice_routing_connection_box_unique_module(netlist_manager, 
+                                                     module_manager,
+                                                     subckt_dir, 
+                                                     unique_mirror, CHANY);
+  }
+
+  /*
+  VTR_LOG("Writing header file for routing submodules '%s'...",
+          ROUTING_VERILOG_FILE_NAME);
+  print_spice_netlist_include_header_file(netlist_names,
+                                          subckt_dir.c_str(),
+                                          ROUTING_VERILOG_FILE_NAME);
+  VTR_LOG("Done\n");
+   */
+  VTR_LOG("\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_routing.h b/openfpga/src/fpga_spice/spice_routing.h
new file mode 100644
index 000000000..3d2e499cc
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_routing.h
@@ -0,0 +1,32 @@
+#ifndef SPICE_ROUTING_H
+#define SPICE_ROUTING_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+
+#include "mux_library.h"
+#include "module_manager.h"
+#include "netlist_manager.h"
+#include "device_rr_gsb.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_spice_flatten_routing_modules(NetlistManager& netlist_manager,
+                                         const ModuleManager& module_manager,
+                                         const DeviceRRGSB& device_rr_gsb,
+                                         const std::string& subckt_dir);
+
+void print_spice_unique_routing_modules(NetlistManager& netlist_manager,
+                                        const ModuleManager& module_manager,
+                                        const DeviceRRGSB& device_rr_gsb,
+                                        const std::string& subckt_dir);
+
+} /* end namespace openfpga */
+
+#endif

From 1dfb3e06ccafc68fecef77860807b48bf85bbdba Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:38:24 -0600
Subject: [PATCH 101/148] [FPGA-SPICE] add SPICE writer for logic blocks

---
 openfpga/src/base/openfpga_spice.cpp   |   2 +
 openfpga/src/fpga_spice/spice_api.cpp  |  10 +
 openfpga/src/fpga_spice/spice_api.h    |   4 +
 openfpga/src/fpga_spice/spice_grid.cpp | 434 +++++++++++++++++++++++++
 openfpga/src/fpga_spice/spice_grid.h   |  30 ++
 5 files changed, 480 insertions(+)
 create mode 100644 openfpga/src/fpga_spice/spice_grid.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_grid.h

diff --git a/openfpga/src/base/openfpga_spice.cpp b/openfpga/src/base/openfpga_spice.cpp
index 0ddab0c91..c1b418835 100644
--- a/openfpga/src/base/openfpga_spice.cpp
+++ b/openfpga/src/base/openfpga_spice.cpp
@@ -41,6 +41,8 @@ int write_fabric_spice(OpenfpgaContext& openfpga_ctx,
                              openfpga_ctx.mutable_spice_netlists(),
                              openfpga_ctx.arch(),
                              openfpga_ctx.mux_lib(),
+                             g_vpr_ctx.device(),
+                             openfpga_ctx.vpr_device_annotation(),
                              openfpga_ctx.device_rr_gsb(),
                              options);
 
diff --git a/openfpga/src/fpga_spice/spice_api.cpp b/openfpga/src/fpga_spice/spice_api.cpp
index 852d29a8d..7787f8ba0 100644
--- a/openfpga/src/fpga_spice/spice_api.cpp
+++ b/openfpga/src/fpga_spice/spice_api.cpp
@@ -17,6 +17,7 @@
 #include "spice_constants.h"
 #include "spice_submodule.h"
 #include "spice_routing.h"
+#include "spice_grid.h"
 
 /* Header file for this source file */
 #include "spice_api.h"
@@ -42,6 +43,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
                       NetlistManager& netlist_manager,
                       const Arch& openfpga_arch,
                       const MuxLibrary& mux_lib,
+                      const DeviceContext &device_ctx,
+                      const VprDeviceAnnotation &device_annotation,
                       const DeviceRRGSB &device_rr_gsb,
                       const FabricSpiceOption& options) {
 
@@ -97,6 +100,13 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
                                         rr_dir_path);
   }
 
+  /* Generate grids */
+  print_spice_grids(netlist_manager,
+                    module_manager,
+                    device_ctx, device_annotation,
+                    lb_dir_path,
+                    options.verbose_output());
+
   /* Given a brief stats on how many Spice modules have been written to files */
   VTR_LOGV(options.verbose_output(),
            "Written %lu SPICE modules in total\n",
diff --git a/openfpga/src/fpga_spice/spice_api.h b/openfpga/src/fpga_spice/spice_api.h
index 2d418432d..0e08aa440 100644
--- a/openfpga/src/fpga_spice/spice_api.h
+++ b/openfpga/src/fpga_spice/spice_api.h
@@ -11,6 +11,8 @@
 #include "module_manager.h"
 #include "openfpga_arch.h"
 #include "mux_library.h"
+#include "vpr_context.h"
+#include "vpr_device_annotation.h"
 #include "device_rr_gsb.h"
 #include "fabric_spice_options.h"
 
@@ -25,6 +27,8 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
                       NetlistManager& netlist_manager,
                       const Arch& openfpga_arch,
                       const MuxLibrary& mux_lib,
+                      const DeviceContext &device_ctx,
+                      const VprDeviceAnnotation &device_annotation,
                       const DeviceRRGSB &device_rr_gsb,
                       const FabricSpiceOption& options);
 
diff --git a/openfpga/src/fpga_spice/spice_grid.cpp b/openfpga/src/fpga_spice/spice_grid.cpp
new file mode 100644
index 000000000..c04ed8920
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_grid.cpp
@@ -0,0 +1,434 @@
+/********************************************************************
+ * This file includes functions to print SPICE subckts for a Grid
+ * (CLBs, I/Os, heterogeneous blocks etc.) 
+ *******************************************************************/
+/* System header files */
+#include <vector>
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_geometry.h"
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from readarch library */
+#include "physical_types.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+#include "openfpga_side_manager.h"
+
+/* Headers from vpr library */
+#include "vpr_utils.h"
+
+#include "openfpga_reserved_words.h"
+#include "openfpga_naming.h"
+#include "openfpga_physical_tile_utils.h"
+#include "pb_type_utils.h"
+#include "circuit_library_utils.h"
+#include "module_manager_utils.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_subckt_writer.h"
+#include "spice_grid.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print SPICE subckts of a primitive node in the pb_graph_node graph
+ * This generic function can support all the different types of primitive nodes
+ * i.e., Look-Up Tables (LUTs), Flip-flops (FFs) and hard logic blocks such as adders.
+ *
+ * The SPICE subckt will consist of two parts:
+ * 1. Logic module of the primitive node
+ *    This module performs the logic function of the block
+ * 2. Memory module of the primitive node
+ *    This module stores the configuration bits for the logic module
+ *    if the logic module is a programmable resource, such as LUT
+ *
+ * SPICE subckt structure:
+ *
+ *       Primitive block
+ *     +---------------------------------------+
+ *     |                                       | 
+ *     |      +---------+    +---------+       |
+ *  in |----->|         |--->|         |<------|configuration lines
+ *     |      |  Logic  |... |  Memory |       |
+ *  out|<-----|         |--->|         |       |
+ *     |      +---------+    +---------+       |
+ *     |                                       | 
+ *     +---------------------------------------+
+ *
+ *******************************************************************/
+static 
+void print_spice_primitive_block(NetlistManager& netlist_manager,
+                                 const ModuleManager& module_manager,
+                                 const std::string& subckt_dir,
+                                 t_pb_graph_node* primitive_pb_graph_node,
+                                 const bool& verbose) {
+  /* Ensure a valid pb_graph_node */ 
+  if (nullptr == primitive_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid primitive_pb_graph_node!\n");
+    exit(1);
+  }
+
+  /* Give a name to the Verilog netlist */
+  /* Create the file name for Verilog */
+  std::string spice_fname(subckt_dir 
+                          + generate_logical_tile_netlist_name(std::string(), primitive_pb_graph_node, std::string(SPICE_NETLIST_FILE_POSTFIX))
+                           );
+
+  VTR_LOG("Writing SPICE netlist '%s' for primitive pb_type '%s' ...",
+          spice_fname.c_str(), primitive_pb_graph_node->pb_type->name);
+  VTR_LOGV(verbose, "\n");
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  print_spice_file_header(fp, std::string("SPICE subckts for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name))); 
+
+  /* Generate the module name for this primitive pb_graph_node*/
+  std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
+
+  /* Create a module of the primitive LUT and register it to module manager */
+  ModuleId primitive_module = module_manager.find_module(primitive_module_name);
+  /* Ensure that the module has been created and thus unique! */
+  VTR_ASSERT(true == module_manager.valid_module_id(primitive_module));
+
+  VTR_LOGV(verbose,
+          "Writing SPICE codes of logical tile primitive block '%s'...",
+           module_manager.module_name(primitive_module).c_str());
+  
+  /* Write the spice module */
+  write_spice_subckt_to_file(fp, module_manager, primitive_module);
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
+
+  VTR_LOGV(verbose, "Done\n");
+}
+
+/********************************************************************
+ * Print SPICE subckts of physical blocks inside a grid (CLB, I/O. etc.)
+ * This function will traverse the graph of complex logic block (t_pb_graph_node)
+ * in a recursive way, using a Depth First Search (DFS) algorithm.
+ * As such, primitive physical blocks (LUTs, FFs, etc.), leaf node of the pb_graph
+ * will be printed out first, while the top-level will be printed out in the last
+ *
+ * Note: this function will print a unique SPICE subckt for each type of 
+ * t_pb_graph_node, i.e., t_pb_type, in the graph, in order to enable highly 
+ * hierarchical Verilog organization as well as simplify the Verilog file sizes.
+ *
+ * Note: DFS is the right way. Do NOT use BFS.
+ * DFS can guarantee that all the sub-modules can be registered properly
+ * to its parent in module manager  
+ *******************************************************************/
+static 
+void rec_print_spice_logical_tile(NetlistManager& netlist_manager,
+                                  const ModuleManager& module_manager,
+                                  const VprDeviceAnnotation& device_annotation,
+                                  const std::string& subckt_dir,
+                                  t_pb_graph_node* physical_pb_graph_node,
+                                  const bool& verbose) {
+
+  /* Check cur_pb_graph_node*/
+  if (nullptr == physical_pb_graph_node) {
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid physical_pb_graph_node\n"); 
+    exit(1);
+  }
+
+  /* Get the pb_type definition related to the node */
+  t_pb_type* physical_pb_type = physical_pb_graph_node->pb_type; 
+
+  /* Find the mode that physical implementation of a pb_type */
+  t_mode* physical_mode = device_annotation.physical_mode(physical_pb_type);
+
+  /* For non-leaf node in the pb_type graph: 
+   * Recursively Depth-First Generate all the child pb_type at the level 
+   */
+  if (false == is_primitive_pb_type(physical_pb_type)) { 
+    for (int ipb = 0; ipb < physical_mode->num_pb_type_children; ++ipb) {
+      /* Go recursive to visit the children */
+      rec_print_spice_logical_tile(netlist_manager,
+                                   module_manager, device_annotation,
+                                   subckt_dir, 
+                                   &(physical_pb_graph_node->child_pb_graph_nodes[physical_mode->index][ipb][0]),
+                                   verbose);
+    }
+  }
+
+  /* For leaf node, a primitive SPICE subckt will be generated.
+   * Note that the primitive may be mapped to a standard cell, we force to use 
+   * explict port mapping. This aims to avoid any port sequence issues!!!
+   */
+  if (true == is_primitive_pb_type(physical_pb_type)) { 
+    print_spice_primitive_block(netlist_manager,
+                                module_manager,
+                                subckt_dir,
+                                physical_pb_graph_node, 
+                                verbose);
+    /* Finish for primitive node, return */
+    return;
+  }
+
+  /* Give a name to the Verilog netlist */
+  /* Create the file name for Verilog */
+  std::string spice_fname(subckt_dir 
+                          + generate_logical_tile_netlist_name(std::string(), physical_pb_graph_node, std::string(SPICE_NETLIST_FILE_POSTFIX))
+                           );
+
+  VTR_LOG("Writing SPICE netlist '%s' for pb_type '%s' ...",
+          spice_fname.c_str(), physical_pb_type->name);
+  VTR_LOGV(verbose, "\n");
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  print_spice_file_header(fp, std::string("SPICE subckts for pb_type: " + std::string(physical_pb_type->name))); 
+
+  /* Generate the name of the SPICE subckt for this pb_type */
+  std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
+
+  /* Register the SPICE subckt in module manager */
+  ModuleId pb_module = module_manager.find_module(pb_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(pb_module));
+
+  VTR_LOGV(verbose,
+          "Writing SPICE codes of pb_type '%s'...",
+           module_manager.module_name(pb_module).c_str());
+
+  /* Comment lines */
+  print_spice_comment(fp, std::string("BEGIN Physical programmable logic block SPICE subckt: " + std::string(physical_pb_type->name)));
+
+  /* Write the spice module */
+  write_spice_subckt_to_file(fp, module_manager, pb_module);
+
+  print_spice_comment(fp, std::string("END Physical programmable logic block SPICE subckt: " + std::string(physical_pb_type->name)));
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
+
+  VTR_LOGV(verbose, "Done\n");
+}
+
+/*****************************************************************************
+ * This function will create a Verilog file and print out a Verilog netlist 
+ * for the logical tile (pb_graph/pb_type) 
+ *****************************************************************************/
+static 
+void print_spice_logical_tile_netlist(NetlistManager& netlist_manager,
+                                        const ModuleManager& module_manager,
+                                        const VprDeviceAnnotation& device_annotation,
+                                        const std::string& subckt_dir,
+                                        t_pb_graph_node* pb_graph_head,
+                                        const bool& verbose) {
+
+  VTR_LOG("Writing Verilog netlists for logic tile '%s' ...",
+          pb_graph_head->pb_type->name);
+  VTR_LOG("\n");
+
+  /* Print SPICE subckts for all the pb_types/pb_graph_nodes
+   * use a Depth-First Search Algorithm to print the sub-modules 
+   * Note: DFS is the right way. Do NOT use BFS.
+   * DFS can guarantee that all the sub-modules can be registered properly
+   * to its parent in module manager  
+   */
+  /* Print SPICE subckts starting from the top-level pb_type/pb_graph_node, and traverse the graph in a recursive way */
+  rec_print_spice_logical_tile(netlist_manager,
+                               module_manager,
+                               device_annotation, 
+                               subckt_dir,
+                               pb_graph_head,
+                               verbose);
+
+  VTR_LOG("Done\n");
+  VTR_LOG("\n");
+}
+
+/*****************************************************************************
+ * This function will create a Verilog file and print out a Verilog netlist 
+ * for a type of physical block 
+ *
+ * For IO blocks: 
+ * The param 'border_side' is required, which is specify which side of fabric
+ * the I/O block locates at.
+ *****************************************************************************/
+static 
+void print_spice_physical_tile_netlist(NetlistManager& netlist_manager,
+                                       const ModuleManager& module_manager,
+                                       const std::string& subckt_dir,
+                                       t_physical_tile_type_ptr phy_block_type,
+                                       const e_side& border_side) {
+  /* Check code: if this is an IO block, the border side MUST be valid */
+  if (true == is_io_type(phy_block_type)) {
+    VTR_ASSERT(NUM_SIDES != border_side);
+  }
+  
+  /* Give a name to the Verilog netlist */
+  /* Create the file name for Verilog */
+  std::string spice_fname(subckt_dir 
+                          + generate_grid_block_netlist_name(std::string(GRID_MODULE_NAME_PREFIX) + std::string(phy_block_type->name), 
+                                                             is_io_type(phy_block_type), 
+                                                             border_side, 
+                                                             std::string(SPICE_NETLIST_FILE_POSTFIX))
+                           );
+
+  /* Echo status */
+  if (true == is_io_type(phy_block_type)) {
+    SideManager side_manager(border_side);
+    VTR_LOG("Writing SPICE Netlist '%s' for physical tile '%s' at %s side ...",
+            spice_fname.c_str(), phy_block_type->name, 
+            side_manager.c_str());
+  } else { 
+    VTR_LOG("Writing SPICE Netlist '%s' for physical_tile '%s'...",
+            spice_fname.c_str(), phy_block_type->name);
+  }
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  print_spice_file_header(fp, std::string("SPICE subckts for physical tile: " + std::string(phy_block_type->name) + "]")); 
+
+  /* Create a Verilog Module for the top-level physical block, and add to module manager */
+  std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_SPICE_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);
+  ModuleId grid_module = module_manager.find_module(grid_module_name); 
+  VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
+
+  /* Write the spice module */
+  print_spice_comment(fp, std::string("BEGIN Grid SPICE subckt: " + module_manager.module_name(grid_module)));
+  write_spice_subckt_to_file(fp, module_manager, grid_module);
+
+  print_spice_comment(fp, std::string("END Grid SPICE subckt: " + module_manager.module_name(grid_module)));
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::LOGIC_BLOCK_NETLIST);
+
+  VTR_LOG("Done\n");
+}
+
+/*****************************************************************************
+ * Create logic block modules in a compact way:
+ * 1. Only one module for each I/O on each border side (IO_TYPE)
+ * 2. Only one module for each CLB (FILL_TYPE)
+ * 3. Only one module for each heterogeneous block
+ ****************************************************************************/
+void print_spice_grids(NetlistManager& netlist_manager,
+                       const ModuleManager& module_manager,
+                       const DeviceContext& device_ctx,
+                       const VprDeviceAnnotation& device_annotation,
+                       const std::string& subckt_dir,
+                       const bool& verbose) {
+  /* Create a vector to contain all the Verilog netlist names that have been generated in this function */
+  std::vector<std::string> netlist_names;
+
+  /* Enumerate the types of logical tiles, and build a module for each 
+   * Write modules for all the pb_types/pb_graph_nodes
+   * use a Depth-First Search Algorithm to print the sub-modules 
+   * Note: DFS is the right way. Do NOT use BFS.
+   * DFS can guarantee that all the sub-modules can be registered properly
+   * to its parent in module manager  
+   */
+  VTR_LOG("Writing logical tiles...");
+  VTR_LOGV(verbose, "\n");
+  for (const t_logical_block_type& logical_tile : device_ctx.logical_block_types) {
+    /* Bypass empty pb_graph */
+    if (nullptr == logical_tile.pb_graph_head) {
+      continue;
+    }
+    print_spice_logical_tile_netlist(netlist_manager,
+                                       module_manager,
+                                       device_annotation,
+                                       subckt_dir,
+                                       logical_tile.pb_graph_head,
+                                       verbose);
+  }
+  VTR_LOG("Writing logical tiles...");
+  VTR_LOG("Done\n");
+
+  VTR_LOG("\n");
+
+  /* Enumerate the types of physical tiles
+   * Use the logical tile module to build the physical tiles
+   */
+  VTR_LOG("Building physical tiles...");
+  VTR_LOGV(verbose, "\n");
+  for (const t_physical_tile_type& physical_tile : device_ctx.physical_tile_types) {
+    /* Bypass empty type or nullptr */
+    if (true == is_empty_type(&physical_tile)) {
+      continue;
+    } else if (true == is_io_type(&physical_tile)) {
+      /* Special for I/O block:
+       * We will search the grids and see where the I/O blocks are located:
+       * - If a I/O block locates on border sides of FPGA fabric:
+       *   i.e., one or more from {TOP, RIGHT, BOTTOM, LEFT},
+       *   we will generate one module for each border side 
+       * - If a I/O block locates in the center of FPGA fabric:
+       *   we will generate one module with NUM_SIDES (same treatment as regular grids) 
+       */
+      std::set<e_side> io_type_sides = find_physical_io_tile_located_sides(device_ctx.grid,
+                                                                           &physical_tile);
+      for (const e_side& io_type_side : io_type_sides) {
+        print_spice_physical_tile_netlist(netlist_manager,
+                                          module_manager,
+                                          subckt_dir, 
+                                          &physical_tile,
+                                          io_type_side);
+      } 
+      continue;
+    } else {
+      /* For CLB and heterogenenous blocks */
+      print_spice_physical_tile_netlist(netlist_manager,
+                                        module_manager,
+                                        subckt_dir, 
+                                        &physical_tile,
+                                        NUM_SIDES);
+    }
+  }
+  VTR_LOG("Building physical tiles...");
+  VTR_LOG("Done\n");
+  VTR_LOG("\n");
+
+  /* Output a header file for all the logic blocks */
+  /*
+  std::string grid_spice_fname(LOGIC_BLOCK_VERILOG_FILE_NAME);
+  VTR_LOG("Writing header file for grid SPICE subckts '%s' ...",
+          grid_spice_fname.c_str());
+  print_spice_netlist_include_header_file(netlist_names,
+                                          subckt_dir.c_str(),
+                                          grid_spice_fname.c_str());
+  VTR_LOG("Done\n");
+   */
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_grid.h b/openfpga/src/fpga_spice/spice_grid.h
new file mode 100644
index 000000000..5f45e2d61
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_grid.h
@@ -0,0 +1,30 @@
+#ifndef SPICE_GRID_H
+#define SPICE_GRID_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "vpr_context.h"
+#include "module_manager.h"
+#include "netlist_manager.h"
+#include "vpr_device_annotation.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_spice_grids(NetlistManager& netlist_manager,
+                      const ModuleManager& module_manager,
+                      const DeviceContext& device_ctx,
+                      const VprDeviceAnnotation& device_annotation,
+                      const std::string& subckt_dir,
+                      const bool& verbose);
+
+
+} /* end namespace openfpga */
+
+#endif

From 06c0073a3ea49d4610d680e02699b3a7e0267ffa Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:43:48 -0600
Subject: [PATCH 102/148] [FPGA-SPICE] Add SPICE writer for fpga top module

---
 openfpga/src/fpga_spice/spice_api.cpp        | 13 ++++
 openfpga/src/fpga_spice/spice_top_module.cpp | 76 ++++++++++++++++++++
 openfpga/src/fpga_spice/spice_top_module.h   | 24 +++++++
 3 files changed, 113 insertions(+)
 create mode 100644 openfpga/src/fpga_spice/spice_top_module.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_top_module.h

diff --git a/openfpga/src/fpga_spice/spice_api.cpp b/openfpga/src/fpga_spice/spice_api.cpp
index 7787f8ba0..a06a3fb8e 100644
--- a/openfpga/src/fpga_spice/spice_api.cpp
+++ b/openfpga/src/fpga_spice/spice_api.cpp
@@ -18,6 +18,7 @@
 #include "spice_submodule.h"
 #include "spice_routing.h"
 #include "spice_grid.h"
+#include "spice_top_module.h"
 
 /* Header file for this source file */
 #include "spice_api.h"
@@ -107,6 +108,18 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
                     lb_dir_path,
                     options.verbose_output());
 
+  /* Generate FPGA fabric */
+  print_spice_top_module(netlist_manager,
+                         module_manager,
+                         src_dir_path);
+
+  /* Generate an netlist including all the fabric-related netlists */
+  /*
+  print_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
+                               src_dir_path,
+                               circuit_lib);
+   */
+
   /* Given a brief stats on how many Spice modules have been written to files */
   VTR_LOGV(options.verbose_output(),
            "Written %lu SPICE modules in total\n",
diff --git a/openfpga/src/fpga_spice/spice_top_module.cpp b/openfpga/src/fpga_spice/spice_top_module.cpp
new file mode 100644
index 000000000..d153d9ef7
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_top_module.cpp
@@ -0,0 +1,76 @@
+/********************************************************************
+ * This file includes functions that are used to print the top-level
+ * module for the FPGA fabric in SPICE format
+ *******************************************************************/
+#include <fstream>
+#include <map>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_subckt_writer.h"
+#include "spice_top_module.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print the top-level module for the FPGA fabric in SPICE format
+ * This function will 
+ * 1. name the top-level module
+ * 2. include dependent netlists 
+ *    - User defined netlists
+ *    - Auto-generated netlists
+ * 3. Add the submodules to the top-level graph
+ * 4. Add module nets to connect datapath ports
+ * 5. Add module nets/submodules to connect configuration ports
+ *******************************************************************/
+void print_spice_top_module(NetlistManager& netlist_manager,
+                            const ModuleManager& module_manager,
+                            const std::string& spice_dir) {
+  /* Create a module as the top-level fabric, and add it to the module manager */
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Create the file name for SPICE netlist */
+  std::string spice_fname(spice_dir + generate_fpga_top_netlist_name(std::string(SPICE_NETLIST_FILE_POSTFIX)));
+
+  VTR_LOG("Writing SPICE netlist for top-level module of FPGA fabric '%s'...",
+          spice_fname.c_str());
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(spice_fname.c_str(), fp);
+
+  print_spice_file_header(fp, std::string("Top-level SPICE subckt for FPGA")); 
+
+  /* Write the module content in Verilog format */
+  write_spice_subckt_to_file(fp, module_manager, top_module);
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  /* Add fname to the netlist name list */
+  NetlistId nlist_id = netlist_manager.add_netlist(spice_fname);
+  VTR_ASSERT(NetlistId::INVALID() != nlist_id);
+  netlist_manager.set_netlist_type(nlist_id, NetlistManager::TOP_MODULE_NETLIST);
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_top_module.h b/openfpga/src/fpga_spice/spice_top_module.h
new file mode 100644
index 000000000..9cea104cc
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_top_module.h
@@ -0,0 +1,24 @@
+#ifndef SPICE_TOP_MODULE_H
+#define SPICE_TOP_MODULE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "module_manager.h"
+#include "netlist_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_spice_top_module(NetlistManager& netlist_manager,
+                            const ModuleManager& module_manager,
+                            const std::string& spice_dir);
+
+} /* end namespace openfpga */
+
+#endif

From 222bc86cbfaa00bb5ad54df6c2f28008b58f0b12 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:53:28 -0600
Subject: [PATCH 103/148] [FPGA-SPICE] Add auxiliary SPICE netlist writer

---
 openfpga/src/fpga_spice/spice_api.cpp         |  9 +-
 .../fpga_spice/spice_auxiliary_netlists.cpp   | 86 +++++++++++++++++++
 .../src/fpga_spice/spice_auxiliary_netlists.h | 24 ++++++
 openfpga/src/fpga_spice/spice_constants.h     |  1 +
 openfpga/src/utils/circuit_library_utils.cpp  | 23 +++++
 openfpga/src/utils/circuit_library_utils.h    |  2 +
 6 files changed, 140 insertions(+), 5 deletions(-)
 create mode 100644 openfpga/src/fpga_spice/spice_auxiliary_netlists.cpp
 create mode 100644 openfpga/src/fpga_spice/spice_auxiliary_netlists.h

diff --git a/openfpga/src/fpga_spice/spice_api.cpp b/openfpga/src/fpga_spice/spice_api.cpp
index a06a3fb8e..22c433bd6 100644
--- a/openfpga/src/fpga_spice/spice_api.cpp
+++ b/openfpga/src/fpga_spice/spice_api.cpp
@@ -19,6 +19,7 @@
 #include "spice_routing.h"
 #include "spice_grid.h"
 #include "spice_top_module.h"
+#include "spice_auxiliary_netlists.h"
 
 /* Header file for this source file */
 #include "spice_api.h"
@@ -114,11 +115,9 @@ int fpga_fabric_spice(const ModuleManager& module_manager,
                          src_dir_path);
 
   /* Generate an netlist including all the fabric-related netlists */
-  /*
-  print_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
-                               src_dir_path,
-                               circuit_lib);
-   */
+  print_spice_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
+                                     src_dir_path,
+                                     openfpga_arch.circuit_lib);
 
   /* Given a brief stats on how many Spice modules have been written to files */
   VTR_LOGV(options.verbose_output(),
diff --git a/openfpga/src/fpga_spice/spice_auxiliary_netlists.cpp b/openfpga/src/fpga_spice/spice_auxiliary_netlists.cpp
new file mode 100644
index 000000000..f76464898
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_auxiliary_netlists.cpp
@@ -0,0 +1,86 @@
+/********************************************************************
+ * This file includes functions that are used to generate SPICE files
+ * or code blocks, with a focus on 
+ * `include user-defined or auto-generated netlists in SPICE format
+ *******************************************************************/
+#include <fstream>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+#include "circuit_library_utils.h"
+#include "spice_constants.h"
+#include "spice_writer_utils.h"
+#include "spice_auxiliary_netlists.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Local constant variables
+ *******************************************************************/
+
+/********************************************************************
+ * Print a file that includes all the fabric netlists 
+ * that have been generated  and user-defined.
+ * This does NOT include any testbenches!
+ * Some netlists are open to compile under specific preprocessing flags
+ *******************************************************************/
+void print_spice_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                        const std::string& src_dir,
+                                        const CircuitLibrary& circuit_lib) {
+  std::string spice_fname = src_dir + std::string(FABRIC_INCLUDE_SPICE_NETLIST_FILE_NAME);
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(spice_fname, std::fstream::out | std::fstream::trunc);
+
+  /* Validate the file stream */
+  check_file_stream(spice_fname.c_str(), fp);
+
+  /* Print the title */
+  print_spice_file_header(fp, std::string("Fabric Netlist Summary")); 
+
+  /* Include all the user-defined netlists */
+  print_spice_comment(fp, std::string("Include user-defined netlists"));
+  for (const std::string& user_defined_netlist : find_circuit_library_unique_spice_netlists(circuit_lib)) {
+    print_spice_include_netlist(fp, user_defined_netlist);
+  }
+
+  /* Include all the primitive modules */
+  print_spice_comment(fp, std::string("Include primitive module netlists"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::SUBMODULE_NETLIST)) {
+    print_spice_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include all the CLB, heterogeneous block modules */
+  print_spice_comment(fp, std::string("Include logic block netlists"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::LOGIC_BLOCK_NETLIST)) {
+    print_spice_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include all the routing architecture modules */
+  print_spice_comment(fp, std::string("Include routing module netlists"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::ROUTING_MODULE_NETLIST)) {
+    print_spice_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Include FPGA top module */
+  print_spice_comment(fp, std::string("Include fabric top-level netlists"));
+  for (const NetlistId& nlist_id : netlist_manager.netlists_by_type(NetlistManager::TOP_MODULE_NETLIST)) {
+    print_spice_include_netlist(fp, netlist_manager.netlist_name(nlist_id));
+  }
+  fp << std::endl;
+
+  /* Close the file stream */
+  fp.close();
+}
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/fpga_spice/spice_auxiliary_netlists.h b/openfpga/src/fpga_spice/spice_auxiliary_netlists.h
new file mode 100644
index 000000000..aa04a54b9
--- /dev/null
+++ b/openfpga/src/fpga_spice/spice_auxiliary_netlists.h
@@ -0,0 +1,24 @@
+#ifndef SPICE_AUXILIARY_NETLISTS_H
+#define SPICE_AUXILIARY_NETLISTS_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "circuit_library.h"
+#include "netlist_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_spice_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                        const std::string& src_dir,
+                                        const CircuitLibrary& circuit_lib);
+
+} /* end namespace openfpga */
+
+#endif 
diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 97b1733c2..68026a0be 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -12,6 +12,7 @@ constexpr char* SUPPLY_WRAPPER_SPICE_FILE_NAME = "supply_wrapper.sp";
 constexpr char* MUXES_SPICE_FILE_NAME = "muxes.sp";
 constexpr char* LUTS_SPICE_FILE_NAME = "luts.sp";
 constexpr char* MEMORIES_SPICE_FILE_NAME = "memories.sp";
+constexpr char* FABRIC_INCLUDE_SPICE_NETLIST_FILE_NAME = "fabric_netlists.sp";
 
 constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
 constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
diff --git a/openfpga/src/utils/circuit_library_utils.cpp b/openfpga/src/utils/circuit_library_utils.cpp
index cd59545ae..8fb5aa7bc 100644
--- a/openfpga/src/utils/circuit_library_utils.cpp
+++ b/openfpga/src/utils/circuit_library_utils.cpp
@@ -251,6 +251,29 @@ std::vector<std::string> find_circuit_library_unique_verilog_netlists(const Circ
  return netlists;
 }
 
+/********************************************************************
+ * A generic function to find all the unique user-defined
+ * Verilog netlists in a circuit library
+ * Netlists with same names will be considered as one
+ *******************************************************************/
+std::vector<std::string> find_circuit_library_unique_spice_netlists(const CircuitLibrary& circuit_lib) {
+  std::vector<std::string> netlists;
+
+  for (const CircuitModelId& model : circuit_lib.models()) {
+    /* Skip empty netlist names */
+    if (true == circuit_lib.model_spice_netlist(model).empty()) {
+      continue;
+    }
+    /* See if the netlist name is already in the list */
+    std::vector<std::string>::iterator it = std::find(netlists.begin(), netlists.end(), circuit_lib.model_spice_netlist(model));
+    if (it == netlists.end()) {
+      netlists.push_back(circuit_lib.model_spice_netlist(model));
+    }
+  }
+
+ return netlists;
+}
+
 /************************************************************************
  * Advanced check if the circuit model of configurable memory
  * satisfy the needs of configuration protocol
diff --git a/openfpga/src/utils/circuit_library_utils.h b/openfpga/src/utils/circuit_library_utils.h
index 584871868..dc7fd0e34 100644
--- a/openfpga/src/utils/circuit_library_utils.h
+++ b/openfpga/src/utils/circuit_library_utils.h
@@ -39,6 +39,8 @@ std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrar
 
 std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
 
+std::vector<std::string> find_circuit_library_unique_spice_netlists(const CircuitLibrary& circuit_lib);
+
 bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
                                              const CircuitLibrary& circuit_lib,
                                              const CircuitModelId& config_mem_circuit_model);

From 460fef580717ff23285102bbf098578a2bc009b8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 12:58:55 -0600
Subject: [PATCH 104/148] [FPGA-Verilog] Rename files and functions to
 distinguish from FPGA-SPICE files and functions

---
 openfpga/src/fpga_verilog/verilog_api.cpp      | 14 +++++++-------
 .../verilog_auxiliary_netlists.cpp             | 18 +++++++++---------
 .../fpga_verilog/verilog_auxiliary_netlists.h  | 12 ++++++------
 openfpga/src/fpga_verilog/verilog_constants.h  |  4 ++--
 ....cpp => verilog_simulation_info_writer.cpp} |  4 ++--
 ...iter.h => verilog_simulation_info_writer.h} |  4 ++--
 6 files changed, 28 insertions(+), 28 deletions(-)
 rename openfpga/src/fpga_verilog/{simulation_info_writer.cpp => verilog_simulation_info_writer.cpp} (98%)
 rename openfpga/src/fpga_verilog/{simulation_info_writer.h => verilog_simulation_info_writer.h} (94%)

diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp
index d02ced128..940d78953 100644
--- a/openfpga/src/fpga_verilog/verilog_api.cpp
+++ b/openfpga/src/fpga_verilog/verilog_api.cpp
@@ -24,7 +24,7 @@
 #include "verilog_preconfig_top_module.h"
 #include "verilog_formal_random_top_testbench.h"
 #include "verilog_top_testbench.h"
-#include "simulation_info_writer.h"
+#include "verilog_simulation_info_writer.h"
 
 /* Header file for this source file */
 #include "verilog_api.h"
@@ -128,9 +128,9 @@ void fpga_fabric_verilog(ModuleManager &module_manager,
                            options.explicit_port_mapping());
 
   /* Generate an netlist including all the fabric-related netlists */
-  print_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
-                               src_dir_path,
-                               circuit_lib);
+  print_verilog_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
+                                       src_dir_path,
+                                       circuit_lib);
 
   /* Given a brief stats on how many Verilog modules have been written to files */
   VTR_LOGV(options.verbose_output(),
@@ -233,9 +233,9 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
   }
 
   /* Generate a Verilog file including all the netlists that have been generated */
-  print_include_netlists(src_dir_path,
-                         netlist_name,
-                         options.reference_benchmark_file_path());
+  print_verilog_testbench_include_netlists(src_dir_path,
+                                           netlist_name,
+                                           options.reference_benchmark_file_path());
 }
 
 } /* end namespace openfpga */
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
index 65e0d1ca2..93fdb2161 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
@@ -30,10 +30,10 @@ namespace openfpga {
  * This does NOT include any testbenches!
  * Some netlists are open to compile under specific preprocessing flags
  *******************************************************************/
-void print_fabric_include_netlist(const NetlistManager& netlist_manager,
-                                  const std::string& src_dir,
-                                  const CircuitLibrary& circuit_lib) {
-  std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME);
+void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                          const std::string& src_dir,
+                                          const CircuitLibrary& circuit_lib) {
+  std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME);
 
   /* Create the file stream */
   std::fstream fp;
@@ -94,10 +94,10 @@ void print_fabric_include_netlist(const NetlistManager& netlist_manager,
  * that have been generated and user-defined.
  * Some netlists are open to compile under specific preprocessing flags
  *******************************************************************/
-void print_include_netlists(const std::string& src_dir,
-                            const std::string& circuit_name,
-                            const std::string& reference_benchmark_file) {
-  std::string verilog_fname = src_dir + circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
+void print_verilog_testbench_include_netlists(const std::string& src_dir,
+                                              const std::string& circuit_name,
+                                              const std::string& reference_benchmark_file) {
+  std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
 
   /* Create the file stream */
   std::fstream fp;
@@ -116,7 +116,7 @@ void print_include_netlists(const std::string& src_dir,
 
   /* Include FPGA top module */
   print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
-  print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_NETLIST_FILE_NAME));
+  print_verilog_include_netlist(fp, src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME));
   fp << std::endl;
 
   /* Include reference benchmark netlist only when auto-check flag is enabled */
diff --git a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
index 57f04032f..c3952af85 100644
--- a/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
+++ b/openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
@@ -17,13 +17,13 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
-void print_fabric_include_netlist(const NetlistManager& netlist_manager,
-                                  const std::string& src_dir,
-                                  const CircuitLibrary& circuit_lib);
+void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
+                                          const std::string& src_dir,
+                                          const CircuitLibrary& circuit_lib);
 
-void print_include_netlists(const std::string& src_dir,
-                            const std::string& circuit_name,
-                            const std::string& reference_benchmark_file);
+void print_verilog_testbench_include_netlists(const std::string& src_dir,
+                                              const std::string& circuit_name,
+                                              const std::string& reference_benchmark_file);
 
 void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
                                                const FabricVerilogOption& fabric_verilog_opts);
diff --git a/openfpga/src/fpga_verilog/verilog_constants.h b/openfpga/src/fpga_verilog/verilog_constants.h
index a09425d4f..66ff018ff 100644
--- a/openfpga/src/fpga_verilog/verilog_constants.h
+++ b/openfpga/src/fpga_verilog/verilog_constants.h
@@ -19,8 +19,8 @@ constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
 constexpr char* ICARUS_SIMULATOR_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
 // End of Icarus variables and flag
 
-constexpr char* FABRIC_INCLUDE_NETLIST_FILE_NAME = "fabric_netlists.v";
-constexpr char* TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
+constexpr char* FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME = "fabric_netlists.v";
+constexpr char* TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX = "_include_netlists.v";
 constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
 constexpr char* FORMAL_VERIFICATION_VERILOG_FILE_POSTFIX = "_top_formal_verification.v"; 
 constexpr char* TOP_TESTBENCH_VERILOG_FILE_POSTFIX = "_top_tb.v"; /* !!! must be consist with the modelsim_testbench_module_postfix */ 
diff --git a/openfpga/src/fpga_verilog/simulation_info_writer.cpp b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
similarity index 98%
rename from openfpga/src/fpga_verilog/simulation_info_writer.cpp
rename to openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
index 134b34f0a..d4a64fcd0 100644
--- a/openfpga/src/fpga_verilog/simulation_info_writer.cpp
+++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.cpp
@@ -21,7 +21,7 @@
 #include "simulation_utils.h"
 
 #include "verilog_constants.h"
-#include "simulation_info_writer.h"
+#include "verilog_simulation_info_writer.h"
 
 /* begin namespace openfpga */
 namespace openfpga {
@@ -77,7 +77,7 @@ void print_verilog_simulation_info(const std::string& ini_fname,
   ini["SIMULATION_DECK"]["UNIT "] = "ms";
   ini["SIMULATION_DECK"]["VERILOG_PATH "] = std::string(src_dir);
   ini["SIMULATION_DECK"]["VERILOG_FILE1"] = std::string(DEFINES_VERILOG_FILE_NAME);
-  ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
+  ini["SIMULATION_DECK"]["VERILOG_FILE2"] = std::string(circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX));
   ini["SIMULATION_DECK"]["CONFIG_PROTOCOL"] = std::string(CONFIG_PROTOCOL_TYPE_STRING[config_protocol_type]);
 
   /* Information required by UVM */
diff --git a/openfpga/src/fpga_verilog/simulation_info_writer.h b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.h
similarity index 94%
rename from openfpga/src/fpga_verilog/simulation_info_writer.h
rename to openfpga/src/fpga_verilog/verilog_simulation_info_writer.h
index ff421fadc..8806a71ac 100644
--- a/openfpga/src/fpga_verilog/simulation_info_writer.h
+++ b/openfpga/src/fpga_verilog/verilog_simulation_info_writer.h
@@ -1,5 +1,5 @@
-#ifndef SIMULATION_INFO_WRITER_H
-#define SIMULATION_INFO_WRITER_H
+#ifndef VERILOG_SIMULATION_INFO_WRITER_H
+#define VERILOG_SIMULATION_INFO_WRITER_H
 
 /********************************************************************
  * Include header files that are required by function declaration

From 615a24999aad52f4a4d22380178afe591ca2d311 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 14:45:33 -0600
Subject: [PATCH 105/148] [Documentation] Remove out-of-date description

---
 README_Benchmarks.md | 9 ---------
 1 file changed, 9 deletions(-)
 delete mode 100644 README_Benchmarks.md

diff --git a/README_Benchmarks.md b/README_Benchmarks.md
deleted file mode 100644
index b9797186e..000000000
--- a/README_Benchmarks.md
+++ /dev/null
@@ -1,9 +0,0 @@
-[TODO]: # (This document might be incomplete. It is important to keep it updated with the right names)
-
-### Benchmarks README ###
-#########
-
-fpga_flow is a folder which contains benchmarks testing the performances of the tool on a known variety of benchmarks. In order to launch them, a script called run_fpga_spice_testbench_study.sh is called. This script is based on different other scripts which can be found in the script folder.
-
-The different benchmarks can be found in the fpga_spice_bench.txt found in the benchmarks folder. By commenting them, the script will not read them and not run through them. This can be useful if you want to focus on one benchmark in particular for example.
-

From 544c44fe4618fdfaa1e346cfc93544618f1fc9b7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 14:58:15 -0600
Subject: [PATCH 106/148] [FPGA-SPICE] Add VDD and VSS port to module
 definition

---
 .../src/fpga_spice/spice_writer_utils.cpp     | 28 ++++++++++++++++++-
 openfpga/src/fpga_spice/spice_writer_utils.h  |  4 ++-
 2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/fpga_spice/spice_writer_utils.cpp b/openfpga/src/fpga_spice/spice_writer_utils.cpp
index 889ee8c19..75f22196c 100644
--- a/openfpga/src/fpga_spice/spice_writer_utils.cpp
+++ b/openfpga/src/fpga_spice/spice_writer_utils.cpp
@@ -18,6 +18,7 @@
 /* Headers from openfpgautil library */
 #include "openfpga_digest.h"
 
+#include "spice_constants.h"
 #include "spice_writer_utils.h"
 
 /* begin namespace openfpga */
@@ -98,7 +99,9 @@ std::string generate_spice_port(const BasicPort& port,
  * module <module_name> (<ports without directions>);
  ***********************************************/
 void print_spice_subckt_definition(std::fstream& fp, 
-                                   const ModuleManager& module_manager, const ModuleId& module_id) {
+                                   const ModuleManager& module_manager,
+                                   const ModuleId& module_id,
+                                   const bool& include_supply_ports) {
   VTR_ASSERT(true == valid_file_stream(fp));
 
   print_spice_comment(fp, std::string("SPICE module for " + module_manager.module_name(module_id)));
@@ -153,6 +156,29 @@ void print_spice_subckt_definition(std::fstream& fp,
       }
     }
   }
+  
+  /* Add supply ports if specified */
+  if (true == include_supply_ports) {
+    /* Check if we need a new line */
+    new_line = false;
+    if (10 == pin_cnt) {
+      pin_cnt = 0;
+      fp << std::endl;
+      new_line = true;
+    }
+    /* Print VDD and VSS ports
+     * TODO: the supply ports should be derived from module manager
+     */
+    if (true == new_line) {
+      std::string port_whitespace(module_head_line.length() - 2, ' ');
+      fp << "+ " << port_whitespace;
+    }
+    write_space_to_file(fp, 1);
+    fp << SPICE_SUBCKT_VDD_PORT_NAME;
+    write_space_to_file(fp, 1);
+    fp << SPICE_SUBCKT_GND_PORT_NAME;
+  }
+
   fp << std::endl;
 }
 
diff --git a/openfpga/src/fpga_spice/spice_writer_utils.h b/openfpga/src/fpga_spice/spice_writer_utils.h
index b01d5a35c..a3617a43a 100644
--- a/openfpga/src/fpga_spice/spice_writer_utils.h
+++ b/openfpga/src/fpga_spice/spice_writer_utils.h
@@ -43,7 +43,9 @@ std::string generate_spice_port(const BasicPort& port,
                                 const bool& omit_pin_zero = false);
 
 void print_spice_subckt_definition(std::fstream& fp, 
-                                   const ModuleManager& module_manager, const ModuleId& module_id);
+                                   const ModuleManager& module_manager,
+                                   const ModuleId& module_id,
+                                   const bool& include_supply_ports = true);
 
 void print_spice_subckt_end(std::fstream& fp, 
                             const std::string& module_name);

From e867e203f44561fae5ceb0a862ce20e4fc63bff9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 15:00:56 -0600
Subject: [PATCH 107/148] [Documentation] Use release mode in Docker settings

---
 Dockerfile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Dockerfile b/Dockerfile
index 771ab425c..94f753737 100755
--- a/Dockerfile
+++ b/Dockerfile
@@ -17,7 +17,7 @@ RUN mkdir -p /release /dev
 
 RUN cd release && git clone --single-branch --branch master https://github.com/LNIS-Projects/OpenFPGA.git OpenFPGA
 
-RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -DCMAKE_BUILD_TYPE=debug -DCMAKE_NO_GRAPHICS=on && make
+RUN cd /release/OpenFPGA && mkdir build && cd build && cmake .. -DCMAKE_NO_GRAPHICS=on && make
 
 RUN rm -rf /var/lib/apt/lists/*
 

From c6ac02d210466fb0d31aa77520e7e0a7c39733b8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 15:21:33 -0600
Subject: [PATCH 108/148] [FPGA-SPICE] Add VDD/VSS ports to SPICE subckt
 instanciation

---
 openfpga/src/fpga_spice/spice_constants.h     |  1 +
 .../src/fpga_spice/spice_subckt_writer.cpp    | 28 ++++++++++++++-
 .../src/fpga_spice/spice_writer_utils.cpp     | 34 ++++++++++++++-----
 3 files changed, 53 insertions(+), 10 deletions(-)

diff --git a/openfpga/src/fpga_spice/spice_constants.h b/openfpga/src/fpga_spice/spice_constants.h
index 68026a0be..3e045b40c 100644
--- a/openfpga/src/fpga_spice/spice_constants.h
+++ b/openfpga/src/fpga_spice/spice_constants.h
@@ -2,6 +2,7 @@
 #define SPICE_CONSTANTS_H
 
 /* global parameters for dumping spice netlists */
+constexpr size_t SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE = 10;
 
 constexpr char* SPICE_NETLIST_FILE_POSTFIX = ".sp";
 
diff --git a/openfpga/src/fpga_spice/spice_subckt_writer.cpp b/openfpga/src/fpga_spice/spice_subckt_writer.cpp
index c90c0b5ac..291404ec6 100644
--- a/openfpga/src/fpga_spice/spice_subckt_writer.cpp
+++ b/openfpga/src/fpga_spice/spice_subckt_writer.cpp
@@ -19,6 +19,9 @@
 #include "openfpga_naming.h"
 
 #include "module_manager_utils.h"
+
+
+#include "spice_constants.h"
 #include "spice_writer_utils.h"
 #include "spice_subckt_writer.h"
 
@@ -370,7 +373,7 @@ void write_spice_instance_to_file(std::fstream& fp,
 
         /* Currently we limit 10 ports per line to keep a clean netlist */
         new_line = false;
-        if (10 == pin_cnt) {
+        if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
           pin_cnt = 0;
           fp << std::endl;
           new_line = true;
@@ -380,6 +383,29 @@ void write_spice_instance_to_file(std::fstream& fp,
     }
   }
 
+  /* Print VDD and VSS ports
+   * TODO: the supply ports should be derived from module manager
+   */
+  if (true == new_line) {
+    std::string port_whitespace(instance_head_line.length() - 2, ' ');
+    fp << "+ " << port_whitespace;
+  }
+  write_space_to_file(fp, 1);
+  fp << SPICE_SUBCKT_VDD_PORT_NAME;
+  write_space_to_file(fp, 1);
+  fp << SPICE_SUBCKT_GND_PORT_NAME;
+
+  pin_cnt += 2;
+
+  /* Check if we need a new line */
+  new_line = false;
+  if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
+    pin_cnt = 0;
+    fp << std::endl;
+    new_line = true;
+    fit_one_line = false;
+  }
+
   /* Print module name: 
    * if port print cannot fit one line, we create a new line for the module for a clean format
    */
diff --git a/openfpga/src/fpga_spice/spice_writer_utils.cpp b/openfpga/src/fpga_spice/spice_writer_utils.cpp
index 75f22196c..68d3360b1 100644
--- a/openfpga/src/fpga_spice/spice_writer_utils.cpp
+++ b/openfpga/src/fpga_spice/spice_writer_utils.cpp
@@ -148,7 +148,7 @@ void print_spice_subckt_definition(std::fstream& fp,
 
         /* Currently we limit 10 ports per line to keep a clean netlist */
         new_line = false;
-        if (10 == pin_cnt) {
+        if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
           pin_cnt = 0;
           fp << std::endl;
           new_line = true;
@@ -159,13 +159,6 @@ void print_spice_subckt_definition(std::fstream& fp,
   
   /* Add supply ports if specified */
   if (true == include_supply_ports) {
-    /* Check if we need a new line */
-    new_line = false;
-    if (10 == pin_cnt) {
-      pin_cnt = 0;
-      fp << std::endl;
-      new_line = true;
-    }
     /* Print VDD and VSS ports
      * TODO: the supply ports should be derived from module manager
      */
@@ -325,7 +318,7 @@ void print_spice_subckt_instance(std::fstream& fp,
 
         /* Currently we limit 10 ports per line to keep a clean netlist */
         new_line = false;
-        if (10 == pin_cnt) {
+        if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
           pin_cnt = 0;
           fp << std::endl;
           new_line = true;
@@ -335,6 +328,29 @@ void print_spice_subckt_instance(std::fstream& fp,
     }
   }
 
+  /* Print VDD and VSS ports
+   * TODO: the supply ports should be derived from module manager
+   */
+  if (true == new_line) {
+    std::string port_whitespace(instance_head_line.length() - 2, ' ');
+    fp << "+ " << port_whitespace;
+  }
+  write_space_to_file(fp, 1);
+  fp << SPICE_SUBCKT_VDD_PORT_NAME;
+  write_space_to_file(fp, 1);
+  fp << SPICE_SUBCKT_GND_PORT_NAME;
+
+  pin_cnt += 2;
+
+  /* Check if we need a new line */
+  new_line = false;
+  if (SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE == pin_cnt) {
+    pin_cnt = 0;
+    fp << std::endl;
+    new_line = true;
+    fit_one_line = false;
+  }
+
   /* Print module name: 
    * if port print cannot fit one line, we create a new line for the module for a clean format
    */

From defb5dea4b1b5c7bd0f4dbf7514d4ae61c44d8a3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 17:08:07 -0600
Subject: [PATCH 109/148] Update issue templates

---
 .github/ISSUE_TEMPLATE/bug_report.md      | 38 +++++++++++++++++++++++
 .github/ISSUE_TEMPLATE/feature_request.md | 20 ++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 .github/ISSUE_TEMPLATE/bug_report.md
 create mode 100644 .github/ISSUE_TEMPLATE/feature_request.md

diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
new file mode 100644
index 000000000..dd84ea782
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -0,0 +1,38 @@
+---
+name: Bug report
+about: Create a report to help us improve
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Describe the bug**
+A clear and concise description of what the bug is.
+
+**To Reproduce**
+Steps to reproduce the behavior:
+1. Go to '...'
+2. Click on '....'
+3. Scroll down to '....'
+4. See error
+
+**Expected behavior**
+A clear and concise description of what you expected to happen.
+
+**Screenshots**
+If applicable, add screenshots to help explain your problem.
+
+**Desktop (please complete the following information):**
+ - OS: [e.g. iOS]
+ - Browser [e.g. chrome, safari]
+ - Version [e.g. 22]
+
+**Smartphone (please complete the following information):**
+ - Device: [e.g. iPhone6]
+ - OS: [e.g. iOS8.1]
+ - Browser [e.g. stock browser, safari]
+ - Version [e.g. 22]
+
+**Additional context**
+Add any other context about the problem here.
diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md
new file mode 100644
index 000000000..bbcbbe7d6
--- /dev/null
+++ b/.github/ISSUE_TEMPLATE/feature_request.md
@@ -0,0 +1,20 @@
+---
+name: Feature request
+about: Suggest an idea for this project
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+**Is your feature request related to a problem? Please describe.**
+A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
+
+**Describe the solution you'd like**
+A clear and concise description of what you want to happen.
+
+**Describe alternatives you've considered**
+A clear and concise description of any alternative solutions or features you've considered.
+
+**Additional context**
+Add any other context or screenshots about the feature request here.

From 5d9228eb2e68f4fedc16271b53ee4d4879e5d1ba Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 20 Sep 2020 17:24:29 -0600
Subject: [PATCH 110/148] Update bug_report.md

---
 .github/ISSUE_TEMPLATE/bug_report.md | 14 ++++----------
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md
index dd84ea782..b465fdee4 100644
--- a/.github/ISSUE_TEMPLATE/bug_report.md
+++ b/.github/ISSUE_TEMPLATE/bug_report.md
@@ -23,16 +23,10 @@ A clear and concise description of what you expected to happen.
 **Screenshots**
 If applicable, add screenshots to help explain your problem.
 
-**Desktop (please complete the following information):**
- - OS: [e.g. iOS]
- - Browser [e.g. chrome, safari]
- - Version [e.g. 22]
-
-**Smartphone (please complete the following information):**
- - Device: [e.g. iPhone6]
- - OS: [e.g. iOS8.1]
- - Browser [e.g. stock browser, safari]
- - Version [e.g. 22]
+**Enviornment (please complete the following information):**
+ - OS: [e.g. CentOs, Ubuntu]
+ - Compiler [e.g. gcc, clang]
+ - Version [e.g. Github commit id]
 
 **Additional context**
 Add any other context about the problem here.

From 60f328a2ab9aee6e69e370deda087564c2e9a1cd Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 17:36:57 -0600
Subject: [PATCH 111/148] [Architecture] Add openfpga architecture for a small
 k4 fracturable FPGA

---
 .../k4_frac_N4_40nm_cc_openfpga.xml           | 231 ++++++++++++++++++
 1 file changed, 231 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
new file mode 100644
index 000000000..ee5c4df5f
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
@@ -0,0 +1,231 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="16"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

From e9c0e90544b4c62c1a8ad5731d599296ed741673 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 17:37:26 -0600
Subject: [PATCH 112/148] [Architecture] Add a VPR architectue using
 fracturable LUT4

---
 .../vpr_arch/k4_frac_N4_tileable_40nm.xml     | 437 ++++++++++++++++++
 1 file changed, 437 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
new file mode 100644
index 000000000..ad69a6808
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
@@ -0,0 +1,437 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="12" equivalent="full"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <output name="out" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fabric.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From a83bc3f75c5c06589f26d9aa78711a472eabaef2 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 17:38:16 -0600
Subject: [PATCH 113/148] [Regression tests] Add test cases for the fracturable
 LUT4 architecture and deploy it to CI

---
 .travis/fpga_verilog_reg_test.sh              |  5 +-
 .../lut_design/frac_lut4/config/task.conf     | 49 +++++++++++++++++++
 .../{frac_lut => frac_lut6}/config/task.conf  |  0
 3 files changed, 53 insertions(+), 1 deletion(-)
 create mode 100644 openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf
 rename openfpga_flow/tasks/fpga_verilog/lut_design/{frac_lut => frac_lut6}/config/task.conf (100%)

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index a8d1e8eb7..f08ebed0e 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -13,8 +13,11 @@ echo -e "FPGA-Verilog Feature Tests";
 echo -e "Testing Verilog generation for LUTs: a single mode LUT6 FPGA using micro benchmarks";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/single_mode --debug --show_thread_logs
 
+echo -e "Testing Verilog generation for LUTs: simple fracturable LUT4 ";
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut4 --debug --show_thread_logs
+
 echo -e "Testing Verilog generation for LUTs: simple fracturable LUT6 ";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/frac_lut6 --debug --show_thread_logs
 
 echo -e "Testing Verilog generation for LUTs: LUT6 with intermediate buffers";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/lut_design/intermediate_buffer --debug --show_thread_logs
diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf
new file mode 100644
index 000000000..805502d33
--- /dev/null
+++ b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut4/config/task.conf
@@ -0,0 +1,49 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+#
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
+# Modelsim is ok with this but icarus fails due to poor support on timing and looping
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+bench1_top = routing_test
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
+
+bench2_top = and2_or2
+bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
+bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf b/openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf
similarity index 100%
rename from openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut/config/task.conf
rename to openfpga_flow/tasks/fpga_verilog/lut_design/frac_lut6/config/task.conf

From d7f8b3abadc751327cf4c1040e59a17b5f858fc5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 17:44:37 -0600
Subject: [PATCH 114/148] [Architecture] Add k4 N4 untilable architecture

---
 openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml | 437 +++++++++++++++++++++
 1 file changed, 437 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
new file mode 100644
index 000000000..872c92a0e
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
@@ -0,0 +1,437 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="12" equivalent="full"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="false">
+    <!--auto_layout aspect_ratio="1.0"-->
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <!-- /auto_layout -->
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <output name="out" num_pins="2"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
+              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fabric.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 6-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From 936a164eee5d25f2510cf731da87b6a7bbe92b0b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 17:48:28 -0600
Subject: [PATCH 115/148] [OpenFPGA flow] Add a new template script to use a
 fixed device layout

---
 .../fix_device_example_script.openfpga        | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)
 create mode 100644 openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga

diff --git a/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
new file mode 100644
index 000000000..3d5418466
--- /dev/null
+++ b/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
@@ -0,0 +1,74 @@
+# Run VPR for the 'and' design
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
+
+# Read OpenFPGA architecture definition
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
+
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
+
+# Annotate the OpenFPGA architecture to VPR data base
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
+
+# Check and correct any naming conflicts in the BLIF netlist
+check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
+
+# Apply fix-up to clustering nets based on routing results
+pb_pin_fixup --verbose
+
+# Apply fix-up to Look-Up Table truth tables based on packing results
+lut_truth_table_fixup
+
+# Build the module graph
+#  - Enabled compression on routing architecture modules
+#  - Enable pin duplication on grid modules
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
+
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack #--verbose
+
+# Build the bitstream
+#  - Output the fabric-independent bitstream to a file
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
+
+# Build fabric-dependent bitstream
+build_fabric_bitstream --verbose
+
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
+
+# Write the Verilog netlist for FPGA fabric
+#  - Enable the use of explicit port mapping in Verilog netlist
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+
+# Write the Verilog testbench for FPGA fabric
+#  - We suggest the use of same output directory as fabric Verilog netlists
+#  - Must specify the reference benchmark file if you want to output any testbenches
+#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
+#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
+#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
+
+# Write the SDC files for PnR backend
+#  - Turn on every options here
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
+
+# Write the SDC to run timing analysis for a mapped FPGA fabric
+write_analysis_sdc --file ./SDC_analysis
+
+# Finish and exit OpenFPGA
+exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

From e1c5947143bb30df5e1dc03b12b983b80fb0517f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 18:01:51 -0600
Subject: [PATCH 116/148] [Architecture] Add auto layout and fixed layout to
 architectures

---
 openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml    |  9 +++++++--
 .../k4_N4_tileable_full_output_crossbar_40nm.xml  |  9 +++++++--
 .../k4_N4_tileable_no_local_routing_40nm.xml      |  9 +++++++--
 openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml        |  9 +++++++--
 .../vpr_arch/k4_frac_N4_tileable_40nm.xml         |  9 +++++++--
 openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml       |  9 +++++++--
 .../vpr_arch/k6_frac_N10_adder_chain_40nm.xml     |  9 +++++++--
 .../k6_frac_N10_adder_chain_mem16K_40nm.xml       | 12 ++++++++++--
 .../vpr_arch/k6_frac_N10_tileable_40nm.xml        |  9 +++++++--
 .../k6_frac_N10_tileable_adder_chain_40nm.xml     |  9 +++++++--
 ..._frac_N10_tileable_adder_chain_mem16K_40nm.xml | 12 ++++++++++--
 ...c_N10_tileable_adder_chain_mem16K_aib_40nm.xml | 14 ++++++++++++--
 ..._adder_chain_mem16K_multi_io_capacity_40nm.xml | 15 +++++++++++++--
 ...ileable_adder_chain_mem16K_reduced_io_40nm.xml | 15 ++++++++++++---
 ..._N10_tileable_adder_chain_wide_mem16K_40nm.xml | 12 ++++++++++--
 ...rac_N10_tileable_adder_register_chain_40nm.xml |  9 +++++++--
 ...10_tileable_adder_register_scan_chain_40nm.xml |  9 +++++++--
 ...er_register_scan_chain_depop50_spypad_40nm.xml | 11 +++++++++--
 ...er_register_scan_chain_mem16K_depop50_12nm.xml | 12 ++++++++++--
 ...eable_thru_channel_adder_chain_mem16K_40nm.xml | 12 ++++++++++--
 ..._thru_channel_adder_chain_wide_mem16K_40nm.xml | 12 ++++++++++--
 .../vpr_arch/k6_frac_N8_tileable_40nm.xml         |  9 +++++++--
 22 files changed, 190 insertions(+), 45 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
index 533704db8..90a484880 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
@@ -63,7 +63,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -71,7 +77,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!--/auto_layout-->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
index 16ceb2be2..00dc13362 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
@@ -64,7 +64,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -72,7 +78,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!--/auto_layout-->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
index 06499b328..f82ea7ffc 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
@@ -67,7 +67,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -75,7 +81,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!--/auto_layout-->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
index 872c92a0e..9544fe0ea 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
@@ -77,7 +77,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -85,7 +91,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
index ad69a6808..fa21da38f 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
@@ -77,7 +77,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -85,7 +91,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
index aa9ca9d98..929809782 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
@@ -77,7 +77,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -85,7 +91,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index bbe041562..8db8eadc2 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -160,7 +160,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="4x4" width="6" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -168,7 +174,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
index 850eb5450..9ec50599a 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml
@@ -194,7 +194,16 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
     <fixed_layout name="4x4" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -205,7 +214,6 @@
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
index 2c528c13c..4eef5f3ac 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
@@ -77,7 +77,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -85,7 +91,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
index c3598bd2b..9afc53b66 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
@@ -160,7 +160,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -168,7 +174,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
index 49656c706..b9bae7853 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
@@ -194,7 +194,16 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
     <fixed_layout name="3x2" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -205,7 +214,6 @@
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
index 2147d392d..fc16bac51 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml
@@ -224,7 +224,18 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="10"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="1"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      <!-- Single instance of an AIB interface -->
+      <single type="aib" x="4" y="1" priority="20"/>
+    </auto_layout>
     <fixed_layout name="3x4" width="5" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="10"/>
@@ -237,7 +248,6 @@
       <!-- Single instance of an AIB interface -->
       <single type="aib" x="4" y="1" priority="20"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
index a3233edb3..b8d4b731d 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
@@ -225,7 +225,19 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <row type="io_top" starty="H-1" priority="100"/>
+      <row type="io_bottom" starty="0" priority="100"/>
+      <col type="io_left" startx="0" priority="100"/>
+      <col type="io_right" startx="W-1" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
     <fixed_layout name="3x2" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <row type="io_top" starty="H-1" priority="100"/>
@@ -239,7 +251,6 @@
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
index 2ed58d2f7..3f29db0e9 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
@@ -194,7 +194,18 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="10"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="1"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+      <row type="EMPTY" starty="H-1" priority="11"/>
+      <row type="EMPTY" starty="0" priority="11"/>
+    </auto_layout>
     <fixed_layout name="3x2" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="10"/>
@@ -206,9 +217,7 @@
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
       <row type="EMPTY" starty="H-1" priority="11"/>
       <row type="EMPTY" starty="0" priority="11"/>
-      <!-- Single instance of an AIB interface -->
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
index 46b23c83e..ab91d62c2 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
@@ -194,7 +194,16 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
     <fixed_layout name="4x4" width="6" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -205,7 +214,6 @@
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
index 9d2f8aee9..f98de28e6 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
@@ -164,7 +164,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -172,7 +178,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index ea1144264..2fb64bf21 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -179,7 +179,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -187,7 +193,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
index d4a4104af..e6e3c11ce 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
@@ -187,7 +187,15 @@
        This is strongly recommended if you want to PnR large FPGA fabric
     -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!-- Use the clb with spypad at [1,1] by setting a higher priority -->
+      <single type="clb_spypad" x="1" y="1" priority="11"/>
+    </auto_layout>
     <!-- Apply a fixed layout of 2x2 core array.
          VPR8 considers the I/O ring in the array size
          Therefore the height and width are both 4
@@ -201,7 +209,6 @@
       <!-- Use the clb with spypad at [1,1] by setting a higher priority -->
       <single type="clb_spypad" x="1" y="1" priority="11"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
index 15281812f..2ee4db855 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
@@ -184,7 +184,16 @@
        This is strongly recommended if you want to PnR large FPGA fabric
     -->
   <layout tileable="true">
-    <!-- auto_layout aspect_ratio="1.0" -->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="16" starty="1" repeatx="16" priority="20"/>
+      <col type="EMPTY" startx="16" repeatx="16" starty="1" priority="19"/>
+    </auto_layout-->
     <!-- Apply a fixed layout of 2x2 core array.
          VPR8 considers the I/O ring in the array size
          Therefore the height and width are both 4
@@ -199,7 +208,6 @@
       <col type="memory" startx="16" starty="1" repeatx="16" priority="20"/>
       <col type="EMPTY" startx="16" repeatx="16" starty="1" priority="19"/>
     </fixed_layout>
-    <!--/auto_layout-->
   </layout>
   <device>
     <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
index ffefc9146..aaf06d70c 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
@@ -201,7 +201,16 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
     <fixed_layout name="4x4" width="5" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -212,7 +221,6 @@
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
index bc5c762b3..802d32ca4 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
@@ -194,7 +194,16 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true" through_channel="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
     <fixed_layout name="4x4" width="6" height="6">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -205,7 +214,6 @@
       <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
       <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
diff --git a/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
index a31984e8b..f642014f7 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N8_tileable_40nm.xml
@@ -77,7 +77,13 @@
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
   <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
     <fixed_layout name="2x2" width="4" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
       <perimeter type="io" priority="100"/>
@@ -85,7 +91,6 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
-    <!-- /auto_layout -->
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 

From 2bbfcb5753681b93cf5404fc7fa3265fbf6600f8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 18:34:31 -0600
Subject: [PATCH 117/148] [Architecture] Add a new device layout to k4n4 for
 testing tileable routing

---
 openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
index fa21da38f..25193bb0f 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
@@ -91,6 +91,13 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 

From 7a57cc9cf457641ab29b64183fef26c60005202d Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 18:36:50 -0600
Subject: [PATCH 118/148] [Architecture] A new device layout to k4n4 to test
 untileable architecture

---
 openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
index 9544fe0ea..5582a8b7b 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
@@ -91,6 +91,13 @@
       <!--Fill with 'clb'-->
       <fill type="clb" priority="10"/>
     </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
   </layout>
   <device>
     <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 

From e4291eb27e28d286b8663864e87b75ae8b6fdee4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 18:44:13 -0600
Subject: [PATCH 119/148] [Regression Tests] Now use fixed device layout in
 test cases for best coverage

---
 .../flatten_routing_example_script.openfpga                | 2 +-
 ...generate_secure_fabric_from_key_example_script.openfpga | 2 +-
 .../load_external_arch_bitstream_example_script.openfpga   | 2 +-
 .../load_external_architecture_bitstream/config/task.conf  | 1 +
 .../tasks/fpga_verilog/bram/dpram16k/config/task.conf      | 3 ++-
 .../tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf | 3 ++-
 .../fpga_verilog/fabric_chain/adder_chain/config/task.conf | 3 ++-
 .../fabric_chain/register_chain/config/task.conf           | 3 ++-
 .../fpga_verilog/fabric_chain/scan_chain/config/task.conf  | 3 ++-
 .../fabric_key/load_external_key/config/task.conf          | 1 +
 .../fabric_key/load_external_key_cc_fpga/config/task.conf  | 1 +
 .../tasks/fpga_verilog/flatten_routing/config/task.conf    | 5 +++--
 openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf   | 3 ++-
 .../fpga_verilog/io/multi_io_capacity/config/task.conf     | 3 ++-
 .../tasks/fpga_verilog/io/reduced_io/config/task.conf      | 3 ++-
 openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf   | 2 +-
 .../thru_channel/thru_narrow_tile/config/task.conf         | 3 ++-
 .../thru_channel/thru_wide_tile/config/task.conf           | 3 ++-
 .../tasks/fpga_verilog/untileable/config/task.conf         | 7 ++++---
 19 files changed, 34 insertions(+), 19 deletions(-)

diff --git a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
index d1c20fb9d..4889f8414 100644
--- a/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga
index 15098c124..9d9b0aa7d 100644
--- a/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/generate_secure_fabric_from_key_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga
index f53e6b187..8276a9119 100644
--- a/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga
+++ b/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
index d36f074ae..89ba177b6 100644
--- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf
@@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf
index a001231df..b693eab56 100644
--- a/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/bram/dpram16k/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf
index 048f5e236..bf748e819 100644
--- a/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/bram/wide_dpram16k/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
index f465fe4fb..c4ca19820 100644
--- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_layout_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf
index 08b46bef5..aa92c76ae 100644
--- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/register_chain/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf
index a4737dbfe..d042a6923 100644
--- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/scan_chain/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf
index b6658090b..d15e02442 100644
--- a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key/config/task.conf
@@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf
index 5931a4a13..41768fc75 100644
--- a/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_key/load_external_key_cc_fpga/config/task.conf
@@ -20,6 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_sample_key.xml
+openfpga_vpr_device_layout=2x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf
index 7fdd7f456..6a4c3aad5 100644
--- a/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/flatten_routing/config/task.conf
@@ -17,11 +17,12 @@ fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/flatten_routing_example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
diff --git a/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf
index 68741ad1c..3dc99925d 100644
--- a/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/io/aib/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x4
 
 #####################################
 # Debugging status 
diff --git a/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf
index fb326c021..645339aee 100644
--- a/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/io/multi_io_capacity/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf
index 88b7b74c8..04d01af53 100644
--- a/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/io/reduced_io/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x2
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
index 0d0bbb547..63d24e471 100644
--- a/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/spypad/config/task.conf
@@ -16,7 +16,7 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 
diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf
index 1e2941de1..7099ff2bc 100644
--- a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_narrow_tile/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf
index 5f6de1078..711c7c7c5 100644
--- a/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/thru_channel/thru_wide_tile/config/task.conf
@@ -16,9 +16,10 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 
 [ARCHITECTURES]
 arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_wide_mem16K_40nm.xml
diff --git a/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf
index 13c0cdf62..44182f645 100644
--- a/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/untileable/config/task.conf
@@ -16,12 +16,13 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif

From acf318f184429088ba6d6403635bce1fc9f22538 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 18:58:35 -0600
Subject: [PATCH 120/148] [Regression test] Bug fix in test case fabric_chain

---
 .../fpga_verilog/fabric_chain/adder_chain/config/task.conf      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
index c4ca19820..71813d734 100644
--- a/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
+++ b/openfpga_flow/tasks/fpga_verilog/fabric_chain/adder_chain/config/task.conf
@@ -16,7 +16,7 @@ timeout_each_job = 20*60
 fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_layout_example_script.openfpga
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
 openfpga_vpr_device_layout=2x2

From a8a269aa82d3f41eb34176229a4bc89e915173c7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 19:51:23 -0600
Subject: [PATCH 121/148] [Architecture] Temporary patch for the no local
 routing architecture

---
 .../k4_N4_tileable_no_local_routing_40nm.xml  | 20 +++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
index f82ea7ffc..4c44908a3 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
@@ -54,10 +54,10 @@
       <equivalent_sites>
         <site pb_type="clb"/>
       </equivalent_sites>
-      <input name="I0" num_pins="4" equivalent="full"/>
-      <input name="I1" num_pins="4" equivalent="full"/>
-      <input name="I2" num_pins="4" equivalent="full"/>
-      <input name="I3" num_pins="4" equivalent="full"/>
+      <input name="I0" num_pins="4" equivalent="none"/>
+      <input name="I1" num_pins="4" equivalent="none"/>
+      <input name="I2" num_pins="4" equivalent="none"/>
+      <input name="I3" num_pins="4" equivalent="none"/>
       <output name="O" num_pins="4" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
@@ -207,10 +207,14 @@
 	   routing area up significantly, we estimate into the ~70% range. 
 	   -->
     <pb_type name="clb">
-      <input name="I0" num_pins="4" equivalent="full"/>
-      <input name="I1" num_pins="4" equivalent="full"/>
-      <input name="I2" num_pins="4" equivalent="full"/>
-      <input name="I3" num_pins="4" equivalent="full"/>
+      <!-- FIXME These inputs should be logic equivalent
+           However, current annotation engine does not support this
+           The feature should be enabled after patching
+        -->
+      <input name="I0" num_pins="4" equivalent="none"/>
+      <input name="I1" num_pins="4" equivalent="none"/>
+      <input name="I2" num_pins="4" equivalent="none"/>
+      <input name="I3" num_pins="4" equivalent="none"/>
       <output name="O" num_pins="4" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <!-- Describe basic logic element.  

From 26f1a5d9ec98d300b9ddbd54a6269d6d0755aa1e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 22:22:03 -0600
Subject: [PATCH 122/148] [OpenFPGA Tool] Bug fix for repacking no local
 routing architecture

---
 openfpga/src/repack/repack.cpp | 92 ++++++++++++++++++++++++++++++++--
 1 file changed, 89 insertions(+), 3 deletions(-)

diff --git a/openfpga/src/repack/repack.cpp b/openfpga/src/repack/repack.cpp
index c3ab88f1c..83956dfc9 100644
--- a/openfpga/src/repack/repack.cpp
+++ b/openfpga/src/repack/repack.cpp
@@ -20,6 +20,73 @@
 /* begin namespace openfpga */
 namespace openfpga {
 
+/***************************************************************************************
+ * Try to find sink pb graph pins through walking through the fan-out edges from
+ * the source pb graph pin
+ * Only the sink meeting the following requirements can be considered:
+ * - All the fan-out edges between the source and sink are from direct interconnection
+ * - sink is an input of a primitive pb_type
+ * 
+ * Note: 
+ *  - If there is a fan-out of the current source pb graph pin is not a direct interconnection
+ *    the direct search should stop. 
+ *  - This function is designed for pb graph without local routing
+ *    For example: direct connection between root pb graph node to the LUT pb graph node
+ *              
+ *              root pb_graph_node
+ *              +-----------------------------------------
+ *              |         Intermediate pb_graph_node
+ *              |       +----------------------------------
+ *              |       |         primitive pb_graph_node
+ *              |       |        +-------------------------
+ *    I[0] ---->+------>+------->|I[0]   LUT
+ *
+ *  - This function is designed for passing wires inside pb graph
+ *
+ *              root pb_graph_node
+ *              +------------------------------+
+ *              | Intermediate pb_graph_node   |
+ *              |       +-------------+        |
+ *              |       |             |        |
+ *              |       |             |        |
+ *    I[0]----->+------>+--- ... ---->+------->+------>O[0]
+ *
+ ***************************************************************************************/
+static 
+bool rec_direct_search_sink_pb_graph_pins(const t_pb_graph_pin* source_pb_pin,
+                                          std::vector<t_pb_graph_pin*>& sink_pb_pins) {
+
+  std::vector<t_pb_graph_pin*> sink_pb_pins_to_search;
+
+  for (int iedge = 0; iedge < source_pb_pin->num_output_edges; ++iedge) {
+    if (DIRECT_INTERC != source_pb_pin->output_edges[iedge]->interconnect->type) {
+      return false;
+    }
+    for (int ipin = 0; ipin < source_pb_pin->output_edges[iedge]->num_output_pins; ++ipin) {
+      t_pb_graph_pin* cand_sink_pb_pin = source_pb_pin->output_edges[iedge]->output_pins[ipin];
+      if ( (true == is_primitive_pb_type(cand_sink_pb_pin->parent_node->pb_type))
+        && (IN_PORT == cand_sink_pb_pin->port->type)) {
+        sink_pb_pins.push_back(cand_sink_pb_pin);
+      } else if ( (true == cand_sink_pb_pin->parent_node->is_root())
+                && (OUT_PORT == cand_sink_pb_pin->port->type)) {
+        sink_pb_pins.push_back(cand_sink_pb_pin);
+      } else {
+        sink_pb_pins_to_search.push_back(cand_sink_pb_pin);
+      }
+    }
+  }
+
+  for (t_pb_graph_pin* sink_pb_pin : sink_pb_pins_to_search) {
+    bool direct_search_status = rec_direct_search_sink_pb_graph_pins(sink_pb_pin, sink_pb_pins);
+    if (false == direct_search_status) {
+      return false;
+    }
+  }
+
+  /* Reach here, we succeed. */
+  return true;
+}
+
 /***************************************************************************************
  * Try find all the sink pins which is mapped to a routing trace in the context of pb route
  * This function uses a recursive walk-through over the pb_route
@@ -133,13 +200,32 @@ void rec_find_routed_sink_pb_graph_pins(const t_pb* pb,
 static 
 std::vector<t_pb_graph_pin*> find_routed_pb_graph_pins_atom_net(const t_pb* pb,
                                                                 const t_pb_graph_pin* source_pb_pin,
+                                                                const t_pb_graph_pin* packing_source_pb_pin,
                                                                 const AtomNetId& atom_net_id,
                                                                 const VprDeviceAnnotation& device_annotation,
                                                                 const std::map<const t_pb_graph_pin*, AtomNetId>& pb_pin_mapped_nets,
                                                                 t_pb_graph_pin** pb_graph_pin_lookup_from_index) {
   std::vector<t_pb_graph_pin*> sink_pb_pins;  
 
-  rec_find_routed_sink_pb_graph_pins(pb, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index, sink_pb_pins);
+  /* Try to directly search for sink pb_pins from the source_pb_pin,
+   * which is the actual source pin to be routed from
+   * Note that the packing source_pb_pin is the source pin considered by 
+   * VPR packer, but may not be the actual source!!! 
+   */
+  if (true == source_pb_pin->parent_node->is_root()) {
+    bool direct_search_status = rec_direct_search_sink_pb_graph_pins(source_pb_pin, sink_pb_pins);
+    if (true == direct_search_status) {
+      VTR_ASSERT(!sink_pb_pins.empty());
+      /* We have find through direct searching, return now */
+      return sink_pb_pins;
+    }
+
+    /* Cannot find through direct searching, reset results */
+    VTR_ASSERT_SAFE(false == direct_search_status);
+    sink_pb_pins.clear();
+  }
+
+  rec_find_routed_sink_pb_graph_pins(pb, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index, sink_pb_pins);
 
   return sink_pb_pins; 
 }
@@ -339,7 +425,7 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(nullptr != packing_source_pb_pin);
 
     /* Find all the sink pins in the pb_route, we walk through the input pins and find the pin  */
-    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index);
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, packing_source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index);
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());
 
@@ -404,7 +490,7 @@ void add_lb_router_nets(LbRouter& lb_router,
     VTR_ASSERT(AtomNetId::INVALID() != atom_net_id);
 
     /* Find all the sink pins in the pb_route */
-    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index);
+    std::vector<t_pb_graph_pin*> sink_pb_graph_pins = find_routed_pb_graph_pins_atom_net(pb, physical_source_pb_pin, source_pb_pin, atom_net_id, device_annotation, pb_pin_mapped_nets, pb_graph_pin_lookup_from_index);
 
     std::vector<LbRRNodeId> sink_lb_rr_nodes = find_lb_net_physical_sink_lb_rr_nodes(lb_rr_graph, sink_pb_graph_pins, device_annotation);
     VTR_ASSERT(sink_lb_rr_nodes.size() == sink_pb_graph_pins.size());

From aa5f5fc7e0d2e29bf97577b44ad73ad4d5bf4598 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 21 Sep 2020 22:22:39 -0600
Subject: [PATCH 123/148] [Architecture] Bring back pin equivalence for no
 local routing architecture

---
 .../k4_N4_tileable_no_local_routing_40nm.xml     | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
index 4c44908a3..b4ebcc711 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
@@ -54,10 +54,10 @@
       <equivalent_sites>
         <site pb_type="clb"/>
       </equivalent_sites>
-      <input name="I0" num_pins="4" equivalent="none"/>
-      <input name="I1" num_pins="4" equivalent="none"/>
-      <input name="I2" num_pins="4" equivalent="none"/>
-      <input name="I3" num_pins="4" equivalent="none"/>
+      <input name="I0" num_pins="4" equivalent="full"/>
+      <input name="I1" num_pins="4" equivalent="full"/>
+      <input name="I2" num_pins="4" equivalent="full"/>
+      <input name="I3" num_pins="4" equivalent="full"/>
       <output name="O" num_pins="4" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
@@ -211,10 +211,10 @@
            However, current annotation engine does not support this
            The feature should be enabled after patching
         -->
-      <input name="I0" num_pins="4" equivalent="none"/>
-      <input name="I1" num_pins="4" equivalent="none"/>
-      <input name="I2" num_pins="4" equivalent="none"/>
-      <input name="I3" num_pins="4" equivalent="none"/>
+      <input name="I0" num_pins="4" equivalent="full"/>
+      <input name="I1" num_pins="4" equivalent="full"/>
+      <input name="I2" num_pins="4" equivalent="full"/>
+      <input name="I3" num_pins="4" equivalent="full"/>
       <output name="O" num_pins="4" equivalent="none"/>
       <clock name="clk" num_pins="1"/>
       <!-- Describe basic logic element.  

From 7a6f5a06f75d163a1a17e41bb02947eb5a5b13e6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:33:56 -0600
Subject: [PATCH 124/148] [Architecture] Add a k4n4 architecture with carry
 chain to quick test

---
 .../k4_frac_N4_tileable_adder_chain_40nm.xml  | 601 ++++++++++++++++++
 1 file changed, 601 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
new file mode 100644
index 000000000..1d0a769ed
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
@@ -0,0 +1,601 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[3:0] clb.I[5:0]</loc>
+        <loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
+      </pinlocations>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </auto_layout>
+    <fixed_layout name="2x2" width="4" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+    </fixed_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="fabric.cout"/>
+              <direct name="direct4" input="frac_logic.out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct5" input="frac_logic.out[1:1]" output="adder[0:0].b"/>
+              <complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="frac_logic.out[0:0] adder[0].cout" output="ff[0:0].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].cout" out_port="ff[0:0].D"/>
+              </mux>
+              <mux name="mux2" input="frac_logic.out[1:1] adder[0].sumout" output="ff[1:1].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].sumout" out_port="ff[1:1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].cout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].cout frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[0].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- BEGIN arithmetic mode of dual lut3 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut3" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="3" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <complete name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[2:0]" output="lut3[0:0].in[2:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[2:0]" output="lut3[1:1].in[2:0]"/>
+              <direct name="lut_to_add1" input="lut3[0:0].out" output="adder.a">
+              </direct>
+              <direct name="lut_to_add2" input="lut3[1:1].out" output="adder.b">
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="cout" input="ff[0:0].Q adder.cout" output="arithmetic.out[0:0]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[0:0]"/>
+                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="arithmetic.out[0:0]"/>
+              </mux>
+              <mux name="sumout" input="ff[1:1].Q adder.sumout" output="arithmetic.out[1:1]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[1:1]"/>
+                <delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="arithmetic.out[1:1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="arithmetic[0:0].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[0:0].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[3:3].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[3:3].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[2:0].cout" output="fle[3:1].cin">
+          <pack_pattern name="chain" in_port="fle[2:0].cout" out_port="fle[3:1].cin"/>
+        </direct>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+  </complexblocklist>
+</architecture>

From dd192a2f5407382ef693d168210a617b05c033a3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:34:23 -0600
Subject: [PATCH 125/148] [Architecture] Add a k4k4 openfpga architecture with
 carry chain for quick test

---
 ...4_frac_N4_adder_chain_40nm_cc_openfpga.xml | 254 ++++++++++++++++++
 1 file changed, 254 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
new file mode 100644
index 000000000..7033f1eda
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
@@ -0,0 +1,254 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="16"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble4' -->
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

From dad19cac9a2791e1be1bedae657cb3f67275f9d8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:39:18 -0600
Subject: [PATCH 126/148] [Regression test] Add k4 series architecture:
 fracturable adder

---
 .../k4_series/k4n4_adder/config/task.conf     | 39 +++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf
new file mode 100644
index 000000000..e1beaf610
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_adder/config/task.conf
@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+external_fabric_key_file=
+openfpga_vpr_device_layout=2x2
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From ea4dd410b71ee1db53adf8b78377ac4084b9f19a Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:41:36 -0600
Subject: [PATCH 127/148] [Regression Test] Add k4n4 fracturable lut test case
 to basic test

---
 .../k4_series/k4n4_frac_lut/config/task.conf  | 49 +++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf
new file mode 100644
index 000000000..805502d33
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf
@@ -0,0 +1,49 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
+
+[BENCHMARKS]
+#
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
+bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
+# Modelsim is ok with this but icarus fails due to poor support on timing and looping
+#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+
+bench1_top = routing_test
+bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
+bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
+
+bench2_top = and2_or2
+bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
+bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 28813126378b137070278e2ed987d84982e19676 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:43:34 -0600
Subject: [PATCH 128/148] [Regression test] deploy k4 series test cases to CI

---
 .travis/basic_reg_test.sh | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index ff29f7b71..3865c66e9 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -38,4 +38,10 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_testbench --
 echo -e "Testing user-defined simulation settings: clock frequency and number of cycles";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_simulation_settings --debug --show_thread_logs
 
+echo -e "Testing K4 series FPGA";
+echo -e "Testing K4N4 with facturable LUTs";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
+echo -e "Testing K4N4 with hard adders";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
+
 end_section "OpenFPGA.TaskTun"

From 2dea97afb65b9185251a4ad093bfd1bb8d04bd85 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:45:29 -0600
Subject: [PATCH 129/148] [Regression test] reduce runtime for k4n4 test in
 basic testing

---
 .../k4_series/k4n4_frac_lut/config/task.conf  | 20 ++++---------------
 1 file changed, 4 insertions(+), 16 deletions(-)

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf
index 805502d33..fa6394642 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_lut/config/task.conf
@@ -25,24 +25,12 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 #
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
-bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
-bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
-# Modelsim is ok with this but icarus fails due to poor support on timing and looping
-#bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
 
 [SYNTHESIS_PARAM]
-bench0_top = and2
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
-
-bench1_top = routing_test
-bench1_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
-bench1_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
-
-bench2_top = and2_or2
-bench2_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
-bench2_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
+bench0_top = and2_or2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
 end_flow_with_test=

From 7ed9f76b069ecfbd828c4277a33533f56621bb0b Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:47:03 -0600
Subject: [PATCH 130/148] [Regression test] Move k4n4 no local routing to basic
 test

---
 .../k4n4_no_local_routing/config/task.conf    | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf
new file mode 100644
index 000000000..c076b156c
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_no_local_routing/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+external_fabric_key_file=
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 3bf94b8e3462003abcdcc4f82bebf7d6fd123e2e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:48:19 -0600
Subject: [PATCH 131/148] [Regression test] Remove no local routing from fpga
 verilog tests

---
 .travis/fpga_verilog_reg_test.sh              |  3 --
 .../no_local_routing/config/task.conf         | 38 -------------------
 2 files changed, 41 deletions(-)
 delete mode 100644 openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf

diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh
index f08ebed0e..ce8c57b92 100755
--- a/.travis/fpga_verilog_reg_test.sh
+++ b/.travis/fpga_verilog_reg_test.sh
@@ -96,9 +96,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar
 echo -e "Testing Fully connected output crossbar in local routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs
 
-echo -e "Testing no local routing architecture";
-python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/no_local_routing --debug --show_thread_logs
-
 echo -e "Testing through channels in tileable routing";
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs
diff --git a/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf
deleted file mode 100644
index c076b156c..000000000
--- a/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf
+++ /dev/null
@@ -1,38 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 20*60
-fpga_flow=vpr_blif
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-external_fabric_key_file=
-
-[ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
-
-[BENCHMARKS]
-bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
-
-[SYNTHESIS_PARAM]
-bench0_top = and2
-bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
-bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
-bench0_chan_width = 300
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
-end_flow_with_test=
-vpr_fpga_verilog_formal_verification_top_netlist=

From 237fc2e63607f2a0c6dfbe7b9da0d5f6703e6f45 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 11:49:16 -0600
Subject: [PATCH 132/148] [Regression test] Deploy no local routing in basic
 tests to CI

---
 .travis/basic_reg_test.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index 3865c66e9..84543bf8d 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -43,5 +43,7 @@ echo -e "Testing K4N4 with facturable LUTs";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_lut --debug --show_thread_logs
 echo -e "Testing K4N4 with hard adders";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
+echo -e "Testing K4N4 without local routing architecture";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"

From daf776b7b1ce9a3293cc5419dafa51c2995653a4 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:22:32 -0600
Subject: [PATCH 133/148] [Architecture] Add k4n4 architecture with bram block
 for basic tests

---
 ...rac_N4_tileable_adder_chain_mem1K_40nm.xml | 702 ++++++++++++++++++
 1 file changed, 702 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
new file mode 100644
index 000000000..68f4bdcb6
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
@@ -0,0 +1,702 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[3:0] clb.I[5:0]</loc>
+        <loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
+    <fixed_layout name="3x2" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="fabric.cout"/>
+              <direct name="direct4" input="frac_logic.out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct5" input="frac_logic.out[1:1]" output="adder[0:0].b"/>
+              <complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="frac_logic.out[0:0] adder[0].cout" output="ff[0:0].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].cout" out_port="ff[0:0].D"/>
+              </mux>
+              <mux name="mux2" input="frac_logic.out[1:1] adder[0].sumout" output="ff[1:1].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].sumout" out_port="ff[1:1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].cout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].cout frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[0].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- BEGIN arithmetic mode of dual lut3 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut3" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="3" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <complete name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[2:0]" output="lut3[0:0].in[2:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[2:0]" output="lut3[1:1].in[2:0]"/>
+              <direct name="lut_to_add1" input="lut3[0:0].out" output="adder.a">
+              </direct>
+              <direct name="lut_to_add2" input="lut3[1:1].out" output="adder.b">
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="cout" input="ff[0:0].Q adder.cout" output="arithmetic.out[0:0]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[0:0]"/>
+                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="arithmetic.out[0:0]"/>
+              </mux>
+              <mux name="sumout" input="ff[1:1].Q adder.sumout" output="arithmetic.out[1:1]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[1:1]"/>
+                <delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="arithmetic.out[1:1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="arithmetic[0:0].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[0:0].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[3:3].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[3:3].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[2:0].cout" output="fle[3:1].cin">
+          <pack_pattern name="chain" in_port="fle[2:0].cout" out_port="fle[3:1].cin"/>
+        </direct>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 128x8=1Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 1K dual-port RAM
+        -->
+      <mode name="mem_128x8_dp">
+        <pb_type name="mem_128x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="7" port_class="address"/>
+          <input name="raddr" num_pins="7" port_class="address"/>
+          <input name="d_in" num_pins="8" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="8" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_128x8_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_128x8_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_128x8_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_128x8_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_128x8_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_128x8_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_128x8_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_128x8_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_128x8_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_128x8_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_128x8_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_128x8_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_128x8_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_128x8_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From 26fba4a94be3b7ac6900463a8010cd7da4564a98 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:22:59 -0600
Subject: [PATCH 134/148] [Architecture] Add openfpga architectue for k4n4 with
 bram blocks

---
 ..._adder_chain_mem1K_40nm_frame_openfpga.xml | 271 ++++++++++++++++++
 1 file changed, 271 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
new file mode 100644
index 000000000..508ceab90
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
@@ -0,0 +1,271 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="16"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" size="1"/>
+       <port type="wl" prefix="wl" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="waddr" size="7"/>
+      <port type="input" prefix="raddr" size="7"/>
+      <port type="input" prefix="d_in" size="8"/>
+      <port type="input" prefix="wen" size="1"/>
+      <port type="input" prefix="ren" size="1"/>
+      <port type="output" prefix="d_out" size="8"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="config_latch"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble4' -->
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
+    <!-- END physical pb_type binding in complex block memory -->
+
+  </pb_type_annotations>
+</openfpga_architecture>

From ddf999b6b901fb94e6cc39f7d0d6e5cdc654512e Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:23:28 -0600
Subject: [PATCH 135/148] [Architecture] Add verilog HDL for dual-port BRAM 1k

---
 openfpga_flow/VerilogNetlists/dpram1k.v | 56 +++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 openfpga_flow/VerilogNetlists/dpram1k.v

diff --git a/openfpga_flow/VerilogNetlists/dpram1k.v b/openfpga_flow/VerilogNetlists/dpram1k.v
new file mode 100644
index 000000000..427d6d199
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/dpram1k.v
@@ -0,0 +1,56 @@
+//-----------------------------------------------------
+// Design Name : dual_port_ram
+// File Name   : dpram.v
+// Function    : Dual port RAM 8x128 
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module dpram_128x8 (
+	input clk,
+	input wen,
+	input ren,
+	input[0:6] waddr,
+	input[0:6] raddr,
+	input[0:7] d_in,
+	output[0:7] d_out );
+
+		dual_port_sram memory_0 (
+			.wclk		(clk),
+			.wen		(wen),
+			.waddr		(waddr),
+			.data_in	(d_in),
+			.rclk		(clk),
+			.ren		(ren),
+			.raddr		(raddr),
+			.d_out		(d_out) );
+
+endmodule
+
+module dual_port_sram (
+	input wclk,
+	input wen,
+	input[0:6] waddr,
+	input[0:7] data_in,
+	input rclk,
+	input ren,
+	input[0:6] raddr,
+	output[0:7] d_out );
+
+	reg[0:7] ram[0:127];
+	reg[0:7] internal;
+
+	assign d_out = internal;
+
+	always @(posedge wclk) begin
+		if(wen) begin
+			ram[waddr] <= data_in;
+		end
+	end
+
+	always @(posedge rclk) begin
+		if(ren) begin
+			internal <= ram[raddr];
+		end
+	end
+
+endmodule

From 5741664580a7b677125f103af00eb633e134d10c Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:23:56 -0600
Subject: [PATCH 136/148] [Regression Test] Add test case for k4n4 bram
 architecture

---
 .../k4_series/k4n4_bram/config/task.conf      | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf
new file mode 100644
index 000000000..6ed4e217e
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_bram/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=3x2
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 8fff2b77eb8a546107be5fbf048554568eb60374 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:24:54 -0600
Subject: [PATCH 137/148] [Regression Test] Deploy k4n4 BRAM test case to CI

---
 .travis/basic_reg_test.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index 84543bf8d..873e0c875 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -45,5 +45,7 @@ echo -e "Testing K4N4 with hard adders";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_adder --debug --show_thread_logs
 echo -e "Testing K4N4 without local routing architecture";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
+echo -e "Testing K4N4 with block RAM";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"

From 8a3934b749c82aebb0045b2d47e99a6664fb89ae Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:35:39 -0600
Subject: [PATCH 138/148] [Architecture Add vpr architecture for k4n4 using
 multiple wire segments

---
 ...4_tileable_adder_chain_mem1K_L124_40nm.xml | 717 ++++++++++++++++++
 1 file changed, 717 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
new file mode 100644
index 000000000..a5172d3f9
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
@@ -0,0 +1,717 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture:
+    25% L = 1, fc_in = 0.25, Fc_out = 0.2
+    25% L = 2, fc_in = 0.25, Fc_out = 0.2
+    50% L = 4, fc_in = 0.25, Fc_out = 0.2
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.25" out_type="frac" out_val="0.20"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.25" out_type="frac" out_val="0.20">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[3:0] clb.I[5:0]</loc>
+        <loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.25" out_type="frac" out_val="0.20"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
+    <fixed_layout name="3x2" width="5" height="4">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="L1" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L2" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <switch type="mux" name="L4" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L1" freq="1.000000" length="1" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="L1"/>
+      <sb type="pattern">1 1</sb>
+      <cb type="pattern">1</cb>
+    </segment>
+    <segment name="L2" freq="1.000000" length="2" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="L2"/>
+      <sb type="pattern">1 1 1</sb>
+      <cb type="pattern">1 1</cb>
+    </segment>
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="L4"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="fabric.cout"/>
+              <direct name="direct4" input="frac_logic.out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct5" input="frac_logic.out[1:1]" output="adder[0:0].b"/>
+              <complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="frac_logic.out[0:0] adder[0].cout" output="ff[0:0].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].cout" out_port="ff[0:0].D"/>
+              </mux>
+              <mux name="mux2" input="frac_logic.out[1:1] adder[0].sumout" output="ff[1:1].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].sumout" out_port="ff[1:1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].cout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].cout frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[0].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- BEGIN arithmetic mode of dual lut3 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut3" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="3" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <complete name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[2:0]" output="lut3[0:0].in[2:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[2:0]" output="lut3[1:1].in[2:0]"/>
+              <direct name="lut_to_add1" input="lut3[0:0].out" output="adder.a">
+              </direct>
+              <direct name="lut_to_add2" input="lut3[1:1].out" output="adder.b">
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="cout" input="ff[0:0].Q adder.cout" output="arithmetic.out[0:0]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[0:0]"/>
+                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="arithmetic.out[0:0]"/>
+              </mux>
+              <mux name="sumout" input="ff[1:1].Q adder.sumout" output="arithmetic.out[1:1]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[1:1]"/>
+                <delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="arithmetic.out[1:1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="arithmetic[0:0].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[0:0].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[3:3].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[3:3].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[2:0].cout" output="fle[3:1].cin">
+          <pack_pattern name="chain" in_port="fle[2:0].cout" out_port="fle[3:1].cin"/>
+        </direct>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 128x8=1Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 1K dual-port RAM
+        -->
+      <mode name="mem_128x8_dp">
+        <pb_type name="mem_128x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="7" port_class="address"/>
+          <input name="raddr" num_pins="7" port_class="address"/>
+          <input name="d_in" num_pins="8" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="8" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_128x8_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_128x8_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_128x8_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_128x8_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_128x8_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_128x8_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_128x8_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_128x8_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_128x8_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_128x8_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_128x8_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_128x8_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_128x8_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_128x8_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+  </complexblocklist>
+</architecture>

From 13df6c1c21fe17d7a1b51699cad4fe6b94ad0756 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:36:11 -0600
Subject: [PATCH 139/148] [Architecture] Add openfpga architecture for k4n4
 using multiple segments

---
 ...r_chain_mem1K_L124_40nm_frame_openfpga.xml | 275 ++++++++++++++++++
 1 file changed, 275 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
new file mode 100644
index 000000000..8bba60744
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
@@ -0,0 +1,275 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="16"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" size="1"/>
+       <port type="wl" prefix="wl" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="waddr" size="7"/>
+      <port type="input" prefix="raddr" size="7"/>
+      <port type="input" prefix="d_in" size="8"/>
+      <port type="input" prefix="wen" size="1"/>
+      <port type="input" prefix="ren" size="1"/>
+      <port type="output" prefix="d_out" size="8"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="config_latch"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="L1" circuit_model_name="mux_2level_tapbuf"/>
+    <switch name="L2" circuit_model_name="mux_2level_tapbuf"/>
+    <switch name="L4" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L1" circuit_model_name="chan_segment"/>
+    <segment name="L2" circuit_model_name="chan_segment"/>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble4' -->
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
+    <!-- END physical pb_type binding in complex block memory -->
+
+  </pb_type_annotations>
+</openfpga_architecture>

From 801055b007eab71d9113eaf4e5654e75ab74f375 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:47:02 -0600
Subject: [PATCH 140/148] [OpenFPGA Tool] Bug Fix on the tileable RRG for multi
 segment

---
 vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index ad4944bb4..2cef83e5c 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -1211,7 +1211,7 @@ t_track2pin_map build_gsb_track_to_ipin_map(const RRGraph& rr_graph,
         ipin_Fc_out.push_back(ipin_Fc);
         if (0 != ipin_Fc) { 
           skip_conn2track = false;
-          break;
+          continue;
         }
       }
 
@@ -1290,7 +1290,7 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraph& rr_graph,
         opin_Fc_out.push_back(opin_Fc);
         if (0 != opin_Fc) { 
           skip_conn2track = false;
-          break;
+          continue;
         }
       }
 

From 3d1f49fb2f7300ed19a0e72fced5d4e3f14d748f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:47:41 -0600
Subject: [PATCH 141/148] [Regression Test] Add testcase for k4n4 with multiple
 segments

---
 .../k4_series/k4n4_L124/config/task.conf      | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf
new file mode 100644
index 000000000..c59ceb467
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_L124/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From a61d161cbed864e6f6fffbf88b8d128b79c206f5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 12:48:53 -0600
Subject: [PATCH 142/148] [Regression Test] Deploy k4n4 with multiple segments
 to CI

---
 .travis/basic_reg_test.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index 873e0c875..2a0ae6bb2 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -47,5 +47,7 @@ echo -e "Testing K4N4 without local routing architecture";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_no_local_routing --debug --show_thread_logs
 echo -e "Testing K4N4 with block RAM";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
+echo -e "Testing K4N4 with multiple lengths of routing segments";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"

From 61bcbaafd81f87bb2294aeea744cbe160921e5d7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 15:15:19 -0600
Subject: [PATCH 143/148] [Architecture] Add Verilog HDL for fracturable 32-bit
 multiplier

---
 openfpga_flow/VerilogNetlists/mult_32x32.v | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 openfpga_flow/VerilogNetlists/mult_32x32.v

diff --git a/openfpga_flow/VerilogNetlists/mult_32x32.v b/openfpga_flow/VerilogNetlists/mult_32x32.v
new file mode 100644
index 000000000..f2e0bea9b
--- /dev/null
+++ b/openfpga_flow/VerilogNetlists/mult_32x32.v
@@ -0,0 +1,35 @@
+//-----------------------------------------------------
+// Design Name : mult_32x32
+// File Name   : mult_32x32.v
+// Function    : A 32-bit multiplier which can operate in fracturable modes:
+//               1. four 8-bit multipliers
+//               2. two 16-bit multipliers
+//               3. one 32-bit multipliers
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module mult_32x32 (
+	input [0:31] a,
+	input [0:31] b,
+	output [0:63] out,
+    input [0:1] mode);
+
+    reg [0:63] out_reg;
+
+    always @(mode, a, b) begin 
+       if (2'b01 == mode) begin
+         out_reg[0:15] <= a[0:7] * b[0:7];
+         out_reg[16:31] <= a[8:15] * b[8:15];
+         out_reg[32:47] <= a[16:23] * b[16:23];
+         out_reg[48:63] <= a[24:31] * b[24:31];
+       end else if (2'b10 == mode) begin
+         out_reg[0:31] <= a[0:15] * b[0:15];
+         out_reg[32:63] <= a[16:31] * b[16:31];
+       end else begin
+         out_reg <= a * b;
+       end
+    end
+
+    assign out = out_reg;
+
+endmodule

From 72749be4bd3153f34965648fae8bb82c616704a7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 15:31:34 -0600
Subject: [PATCH 144/148] [Architecture] Add OpenFPGA architecture for k4n4
 with fracturable 32-bit multiplier

---
 ...n_mem1K_frac_dsp32_40nm_frame_openfpga.xml | 304 ++++++++++++++++++
 1 file changed, 304 insertions(+)
 create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml

diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
new file mode 100644
index 000000000..eb5e3c659
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
@@ -0,0 +1,304 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
+      <design_technology type="cmos" topology="OR"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="a b" out_port="out">
+        10e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
+      <design_technology type="cmos" fracturable_lut="true"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4" tri_state_map="---1" circuit_model_name="OR2"/>
+      <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
+      <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
+      <port type="sram" prefix="sram" size="16"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" size="1"/>
+       <port type="wl" prefix="wl" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="Qb" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="input" prefix="outpad" size="1"/>
+      <port type="output" prefix="inpad" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="1"/>
+      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="cin" size="1"/>
+      <port type="output" prefix="sumout" size="1"/>
+      <port type="output" prefix="cout" size="1"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="waddr" size="7"/>
+      <port type="input" prefix="raddr" size="7"/>
+      <port type="input" prefix="d_in" size="8"/>
+      <port type="input" prefix="wen" size="1"/>
+      <port type="input" prefix="ren" size="1"/>
+      <port type="output" prefix="d_out" size="8"/>
+      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+    <circuit_model type="hard_logic" name="mult_32x32" prefix="mult_32x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/mult_32x32.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/mult_32x32.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="input" prefix="a" size="32"/>
+      <port type="input" prefix="b" size="32"/>
+      <port type="output" prefix="out" size="64"/>
+      <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="config_latch"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <direct_connection>
+    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
+  </direct_connection>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle" physical_mode_name="physical"/>
+    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <!-- Binding operating pb_type to physical pb_type -->
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].arithmetic.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
+      <!-- Binding the lut4 to the first 3 inputs of fracturable lut6 -->
+      <port name="in" physical_mode_port="in[0:2]"/>
+      <port name="out" physical_mode_port="lut3_out[0:0]" physical_mode_pin_rotate_offset="1"/>
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
+    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <!-- Binding operating pb_types in mode 'ble4' -->
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="0">
+      <!-- Binding the lut4 to the first 4 inputs of fracturable lut4 -->
+      <port name="in" physical_mode_port="in[0:3]"/>
+      <port name="out" physical_mode_port="lut4_out"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <!-- End physical pb_type binding in complex block IO -->
+    <!-- physical pb_type binding in complex block memory -->
+    <pb_type name="memory[mem_128x8_dp].mem_128x8_dp" circuit_model_name="dpram_128x8"/>
+    <!-- END physical pb_type binding in complex block memory -->
+
+    <!-- physical pb_type binding in complex block dsp -->
+    <pb_type name="mult_32" physical_mode_name="mult_32x32" idle_mode_name="mult_32x32"/>
+    <!-- Bind the primitive pb_type in the physical mode to a circuit model --> 
+    <pb_type name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" circuit_model_name="mult_32x32" mode_bits="00"/>
+    <!-- Bind the 8x8 multiplier to the physical 32x32 multiplier
+         There are four 8x8 multipliers, each of which occupies part
+         of the input/output of the 32x32 multiplier
+      -->
+    <pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[two_mult_8x8].mult_8x8_slice.mult_8x8" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="01" physical_pb_type_index_factor="0">
+      <port name="a" physical_mode_port="a[0:7]" physical_mode_pin_rotate_offset="8"/>
+      <port name="b" physical_mode_port="b[0:7]" physical_mode_pin_rotate_offset="8"/>
+      <port name="out" physical_mode_port="out[0:15]" physical_mode_pin_rotate_offset="16"/>
+    </pb_type>
+    <!-- Bind the 16x16 multiplier to the physical 32x32 multiplier
+         There are two 16x16 multipliers, each of which occupies part
+         of the input/output of the 32x32 multiplier
+      -->
+    <pb_type name="mult_32[two_divisible_mult_16x16].divisible_mult_16x16[mult_16x16].mult_16x16_slice.mult_16x16" physical_pb_type_name="mult_32[mult_32x32].mult_32x32_slice.mult_32x32" mode_bits="10" physical_pb_type_index_factor="0">
+      <port name="a" physical_mode_port="a[0:15]" physical_mode_pin_rotate_offset="16"/>
+      <port name="b" physical_mode_port="b[0:15]" physical_mode_pin_rotate_offset="16"/>
+      <port name="out" physical_mode_port="out[0:31]" physical_mode_pin_rotate_offset="32"/>
+    </pb_type>
+    <!-- END physical pb_type binding in complex block dsp -->
+  </pb_type_annotations>
+</openfpga_architecture>

From 70b8b02f74ad3e38dd2b1536f73d26fb8c5039b6 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 15:32:11 -0600
Subject: [PATCH 145/148] [Architecture] Add vpr architecture for k4n4 with
 fracturable 32-bit multiplier

---
 ...able_adder_chain_mem1K_frac_dsp32_40nm.xml | 902 ++++++++++++++++++
 1 file changed, 902 insertions(+)
 create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml

diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
new file mode 100644
index 000000000..eff6cc604
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+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
@@ -0,0 +1,902 @@
+<!-- 
+  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
+
+  - 40 nm technology
+  - General purpose logic block: 
+    K = 4, N = 4, fracturable 4 LUTs (can operate as one 4-LUT or two 3-LUTs with all 3 inputs shared) 
+    with optionally registered outputs
+  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
+  - Memory size 1 Kbits, memory aspect ratios vary from a data width of 1 to data width of 8.  
+    Height = 2, found on every (8n+2)th column
+  - Multiplier modes: one 32x32, two 16x16, each 16x16 can also operate as two 8x8.  
+    Height = 4, found on every (8n+4)th column
+
+
+  Details on Modelling:
+
+  Based on flagship k4_frac_N4_mem32K_40nm.xml architecture.
+
+  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
+-->
+<architecture>
+  <!-- 
+       ODIN II specific config begins 
+       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
+       ".model [type_of_block]") that this architecture supports.
+
+       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
+       already special structures in blif (.names, .input, .output, and .latch) 
+       that describe them.
+  -->
+  <models>
+    <model name="adder">
+      <input_ports>
+        <port name="a" combinational_sink_ports="sumout cout"/>
+        <port name="b" combinational_sink_ports="sumout cout"/>
+        <port name="cin" combinational_sink_ports="sumout cout"/>
+      </input_ports>
+      <output_ports>
+        <port name="cout"/>
+        <port name="sumout"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="io">
+      <input_ports>
+        <port name="outpad"/>
+      </input_ports>
+      <output_ports>
+        <port name="inpad"/>
+      </output_ports>
+    </model>
+    <!-- A virtual model for I/O to be used in the physical mode of io block -->
+    <model name="frac_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut3_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
+    <model name="dual_port_ram">
+      <input_ports>
+        <!-- write address lines -->
+        <port name="waddr" clock="clk"/>
+        <!-- read address lines -->
+        <port name="raddr" clock="clk"/>
+        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_in" clock="clk"/>
+        <!-- write enable -->
+        <port name="wen" clock="clk"/>
+        <!-- read enable -->
+        <port name="ren" clock="clk"/>
+        <!-- memories are often clocked -->
+        <port name="clk" is_clock="1"/>
+      </input_ports>
+      <output_ports>
+        <!-- output can be broken down into smaller bit widths minimum size 1 -->
+        <port name="d_out" clock="clk"/>
+      </output_ports>
+    </model>
+    <model name="multiply">
+      <input_ports>
+        <port name="a" combinational_sink_ports="out"/>
+        <port name="b" combinational_sink_ports="out"/>
+      </input_ports>
+      <output_ports>
+        <port name="out"/>
+      </output_ports>
+    </model>
+  </models>
+  <tiles>
+    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+         If you need to register the I/O, define clocks in the circuit models
+         These clocks can be handled in back-end
+     -->
+    <tile name="io" capacity="8" area="0">
+      <equivalent_sites>
+        <site pb_type="io"/>
+      </equivalent_sites>
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="custom">
+        <loc side="left">io.outpad io.inpad</loc>
+        <loc side="top">io.outpad io.inpad</loc>
+        <loc side="right">io.outpad io.inpad</loc>
+        <loc side="bottom">io.outpad io.inpad</loc>
+      </pinlocations>
+    </tile>
+    <tile name="clb" area="53894">
+      <equivalent_sites>
+        <site pb_type="clb"/>
+      </equivalent_sites>
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
+        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
+        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
+      </fc>
+      <!--pinlocations pattern="spread"/-->
+      <pinlocations pattern="custom">
+        <loc side="left">clb.clk</loc>
+        <loc side="top">clb.cin</loc>
+        <loc side="right">clb.O[3:0] clb.I[5:0]</loc>
+        <loc side="bottom">clb.cout clb.O[7:4] clb.I[11:6]</loc>
+      </pinlocations>
+    </tile>
+    <tile name="memory" height="2" area="548000">
+      <equivalent_sites>
+        <site pb_type="memory"/>
+      </equivalent_sites>
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <pinlocations pattern="spread"/>
+    </tile>
+    <tile name="mult_32" height="4" area="396000">
+      <equivalent_sites>
+        <site pb_type="mult_32" pin_mapping="direct"/>
+      </equivalent_sites>
+      <input name="a" num_pins="32"/>
+      <input name="b" num_pins="32"/>
+      <output name="out" num_pins="64"/>
+      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
+      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
+      <pinlocations pattern="spread"/>
+      <!--pinlocations pattern="custom">
+        <loc side="left"></loc>
+        <loc side="top"></loc>
+        <loc side="right">mult_32.a[0:15] mult_32.b[0:15] mult_32.out[0:31]</loc>
+        <loc side="bottom">mult_32.a[16:31] mult_32.b[16:31] mult_32.out[32:63]</loc>
+      </pinlocations-->
+    </tile>
+  </tiles>
+  <!-- ODIN II specific config ends -->
+  <!-- Physical descriptions begin -->
+  <layout tileable="true">
+    <auto_layout aspect_ratio="1.0">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'mult_32' with 'EMPTY' blocks wherever a 'mult_32' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="mult_32" startx="4" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="4" repeatx="8" starty="1" priority="19"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </auto_layout>
+    <fixed_layout name="4x4" width="6" height="6">
+      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
+      <perimeter type="io" priority="100"/>
+      <corners type="EMPTY" priority="101"/>
+      <!--Fill with 'clb'-->
+      <fill type="clb" priority="10"/>
+      <!--Column of 'mult_32' with 'EMPTY' blocks wherever a 'mult_32' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="mult_32" startx="4" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="4" repeatx="8" starty="1" priority="19"/>
+      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
+      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
+      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
+    </fixed_layout>
+  </layout>
+  <device>
+    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
+			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
+			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
+			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
+			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
+			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
+			     lined up with Stratix IV. 
+			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
+			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
+			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
+	                     by 2.5x when looking up in Jeff's tables.
+			     The delay values are lined up with Stratix IV, which has an architecture similar to this
+			     proposed FPGA, and which is also 40 nm 
+			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
+			     4x minimum drive strength buffer. -->
+    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
+    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
+     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
+	  -->
+    <area grid_logic_tile_area="0"/>
+    <chan_width_distr>
+      <x distr="uniform" peak="1.000000"/>
+      <y distr="uniform" peak="1.000000"/>
+    </chan_width_distr>
+    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
+    <connection_block input_switch_name="ipin_cblock"/>
+  </device>
+  <switchlist>
+    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
+	       book area formula. This means the mux transistors are about 5x minimum drive strength.
+	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
+	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
+	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
+	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
+	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
+	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
+	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
+	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
+	       2.5x when looking up in Jeff's tables.
+	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
+	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
+    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
+    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
+    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
+  </switchlist>
+  <segmentlist>
+    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
+			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
+			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
+    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
+    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
+      <mux name="0"/>
+      <sb type="pattern">1 1 1 1 1</sb>
+      <cb type="pattern">1 1 1 1</cb>
+    </segment>
+  </segmentlist>
+  <directlist>
+    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
+  </directlist>
+  <complexblocklist>
+    <!-- Define I/O pads begin -->
+    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
+    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
+    <pb_type name="io">
+      <input name="outpad" num_pins="1"/>
+      <output name="inpad" num_pins="1"/>
+      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
+           If you need to register the I/O, define clocks in the circuit models
+           These clocks can be handled in back-end
+       -->
+      <!-- A mode denotes the physical implementation of an I/O 
+           This mode will be not packable but is mainly used for fabric verilog generation   
+        -->
+      <mode name="physical" disabled_in_pack="true">
+        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="iopad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
+          </direct>
+          <direct name="inpad" input="iopad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+
+      <!-- IOs can operate as either inputs or outputs.
+	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
+	     the delays to and from registers in the I/O (and generally I/Os are registered 
+	     today and that is when you timing analyze them.
+	     -->
+      <mode name="inpad">
+        <pb_type name="inpad" blif_model=".input" num_pb="1">
+          <output name="inpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="inpad" input="inpad.inpad" output="io.inpad">
+            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="outpad">
+        <pb_type name="outpad" blif_model=".output" num_pb="1">
+          <input name="outpad" num_pins="1"/>
+        </pb_type>
+        <interconnect>
+          <direct name="outpad" input="io.outpad" output="outpad.outpad">
+            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- IOs go on the periphery of the FPGA, for consistency, 
+          make it physically equivalent on all sides so that only one definition of I/Os is needed.
+          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
+        -->
+      <!-- Place I/Os on the sides of the FPGA -->
+      <power method="ignore"/>
+    </pb_type>
+    <!-- Define I/O pads ends -->
+    <!-- Define general purpose logic block (CLB) begin -->
+    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
+	   area is 60 L^2 yields a tile area of 84375 MWTAs.
+	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
+	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
+	   block. Note that the crossbar / local interconnect is considered part of the logic block
+	   area in this analysis. That is a lower proportion of of routing area than most academics
+	   assume, but note that the total routing area really includes the crossbar, which would push
+	   routing area up significantly, we estimate into the ~70% range. 
+	   -->
+    <pb_type name="clb">
+      <input name="I" num_pins="12" equivalent="full"/>
+      <input name="cin" num_pins="1"/>
+      <output name="O" num_pins="8" equivalent="none"/>
+      <output name="cout" num_pins="1"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Describe fracturable logic element.  
+             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
+             The outputs of the fracturable logic element can be optionally registered
+        -->
+      <pb_type name="fle" num_pb="4">
+        <input name="in" num_pins="4"/>
+        <input name="cin" num_pins="1"/>
+        <output name="out" num_pins="2"/>
+        <output name="cout" num_pins="1"/>
+        <clock name="clk" num_pins="1"/>
+        <!-- Physical mode definition begin (physical implementation of the fle) -->
+        <mode name="physical" disabled_in_pack="true">
+          <pb_type name="fabric" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="frac_logic" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="out" num_pins="2"/>
+              <!-- Define LUT -->
+              <pb_type name="frac_lut4" blif_model=".subckt frac_lut4" num_pb="1">
+                <input name="in" num_pins="4"/>
+                <output name="lut3_out" num_pins="2"/>
+                <output name="lut4_out" num_pins="1"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="frac_logic.in" output="frac_lut4.in"/>
+                <direct name="direct2" input="frac_lut4.lut3_out[1]" output="frac_logic.out[1]"/>
+                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
+                <mux name="mux1" input="frac_lut4.lut4_out frac_lut4.lut3_out[0]" output="frac_logic.out[0]"/>
+              </interconnect>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <!-- Define adders -->
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
+              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
+              <direct name="direct3" input="adder[0:0].cout" output="fabric.cout"/>
+              <direct name="direct4" input="frac_logic.out[0:0]" output="adder[0:0].a"/>
+              <direct name="direct5" input="frac_logic.out[1:1]" output="adder[0:0].b"/>
+              <complete name="direct6" input="fabric.clk" output="ff[1:0].clk"/>
+              <mux name="mux1" input="frac_logic.out[0:0] adder[0].cout" output="ff[0:0].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[0:0]" out_port="ff[0:0].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].cout" out_port="ff[0:0].D"/>
+              </mux>
+              <mux name="mux2" input="frac_logic.out[1:1] adder[0].sumout" output="ff[1:1].D">
+                <delay_constant max="25e-12" in_port="frac_logic.out[1:1]" out_port="ff[1:1].D"/>
+                <delay_constant max="45e-12" in_port="adder[0].sumout" out_port="ff[1:1].D"/>
+              </mux>
+              <mux name="mux3" input="adder[0].cout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].cout frac_logic.out[0]" out_port="fabric.out[0]"/>
+                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
+              </mux>
+              <mux name="mux4" input="adder[0].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[1]" out_port="fabric.out[1]"/>
+                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="fabric.in"/>
+            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
+            <direct name="direct3" input="fabric.out" output="fle.out"/>
+            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Dual 3-LUT mode definition begin -->
+        <mode name="n2_lut3">
+          <pb_type name="lut3inter" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <output name="out" num_pins="2"/>
+            <clock name="clk" num_pins="1"/>
+            <pb_type name="ble3" num_pb="2">
+              <input name="in" num_pins="3"/>
+              <output name="out" num_pins="1"/>
+              <clock name="clk" num_pins="1"/>
+              <!-- Define the LUT -->
+              <pb_type name="lut3" blif_model=".names" num_pb="1" class="lut">
+                <input name="in" num_pins="3" port_class="lut_in"/>
+                <output name="out" num_pins="1" port_class="lut_out"/>
+                <!-- LUT timing using delay matrix -->
+                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                           we instead take the average of these numbers to get more stable results
+                      82e-12
+                      173e-12
+                      261e-12
+                      263e-12
+                      398e-12
+                      -->
+                <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  235e-12
+                  235e-12
+                  235e-12
+                </delay_matrix>
+              </pb_type>
+              <!-- Define the flip-flop -->
+              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+                <input name="D" num_pins="1" port_class="D"/>
+                <output name="Q" num_pins="1" port_class="Q"/>
+                <clock name="clk" num_pins="1" port_class="clock"/>
+                <T_setup value="66e-12" port="ff.D" clock="clk"/>
+                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+              </pb_type>
+              <interconnect>
+                <direct name="direct1" input="ble3.in[2:0]" output="lut3[0:0].in[2:0]"/>
+                <direct name="direct2" input="lut3[0:0].out" output="ff[0:0].D">
+                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                  <pack_pattern name="ble3" in_port="lut3[0:0].out" out_port="ff[0:0].D"/>
+                </direct>
+                <direct name="direct3" input="ble3.clk" output="ff[0:0].clk"/>
+                <mux name="mux1" input="ff[0:0].Q lut3.out[0:0]" output="ble3.out[0:0]">
+                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                  <delay_constant max="25e-12" in_port="lut3.out[0:0]" out_port="ble3.out[0:0]"/>
+                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble3.out[0:0]"/>
+                </mux>
+              </interconnect>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="lut3inter.in" output="ble3[0:0].in"/>
+              <direct name="direct2" input="lut3inter.in" output="ble3[1:1].in"/>
+              <direct name="direct3" input="ble3[1:0].out" output="lut3inter.out"/>
+              <complete name="complete1" input="lut3inter.clk" output="ble3[1:0].clk"/>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="lut3inter.in"/>
+            <direct name="direct2" input="lut3inter.out" output="fle.out"/>
+            <direct name="direct3" input="fle.clk" output="lut3inter.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Dual 3-LUT mode definition end -->
+        <!-- BEGIN arithmetic mode of dual lut3 + adders -->
+        <mode name="arithmetic">
+          <pb_type name="arithmetic" num_pb="1">
+            <input name="in" num_pins="3"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="2"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Special dual-LUT mode that drives adder only -->
+            <pb_type name="lut3" blif_model=".names" num_pb="2" class="lut">
+              <input name="in" num_pins="3" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  -->
+              <delay_matrix type="max" in_port="lut3.in" out_port="lut3.out">
+                  195e-12
+                  195e-12
+                  195e-12
+                </delay_matrix>
+            </pb_type>
+            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+              <output name="sumout" num_pins="1"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
+              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
+              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
+              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
+            </pb_type>
+            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <complete name="clock" input="arithmetic.clk" output="ff.clk"/>
+              <direct name="lut_in1" input="arithmetic.in[2:0]" output="lut3[0:0].in[2:0]"/>
+              <direct name="lut_in2" input="arithmetic.in[2:0]" output="lut3[1:1].in[2:0]"/>
+              <direct name="lut_to_add1" input="lut3[0:0].out" output="adder.a">
+              </direct>
+              <direct name="lut_to_add2" input="lut3[1:1].out" output="adder.b">
+              </direct>
+              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
+                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
+              </direct>
+              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
+                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
+              </direct>
+              <mux name="cout" input="ff[0:0].Q adder.cout" output="arithmetic.out[0:0]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[0:0]"/>
+                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="arithmetic.out[0:0]"/>
+              </mux>
+              <mux name="sumout" input="ff[1:1].Q adder.sumout" output="arithmetic.out[1:1]">
+                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out[1:1]"/>
+                <delay_constant max="45e-12" in_port="ff[1:1].Q" out_port="arithmetic.out[1:1]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in[2:0]" output="arithmetic[0:0].in"/>
+            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
+              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
+            </direct>
+            <direct name="carry_out" input="arithmetic[0:0].cout" output="fle.cout">
+              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
+            </direct>
+            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
+            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition begin -->
+        <mode name="n1_lut4">
+          <!-- Define 4-LUT mode -->
+          <pb_type name="ble4" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <output name="out" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define LUT -->
+            <pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
+              <input name="in" num_pins="4" port_class="lut_in"/>
+              <output name="out" num_pins="1" port_class="lut_out"/>
+              <!-- LUT timing using delay matrix -->
+              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
+                       we instead take the average of these numbers to get more stable results
+                  82e-12
+                  173e-12
+                  261e-12
+                  263e-12
+                  398e-12
+                  397e-12
+                  -->
+              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
+                261e-12
+                261e-12
+                261e-12
+                261e-12
+              </delay_matrix>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
+              <direct name="direct2" input="lut4.out" output="ff.D">
+                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
+                <pack_pattern name="ble4" in_port="lut4.out" out_port="ff.D"/>
+              </direct>
+              <direct name="direct3" input="ble4.clk" output="ff.clk"/>
+              <mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
+                <!-- LUT to output is faster than FF to output on a Stratix IV -->
+                <delay_constant max="25e-12" in_port="lut4.out" out_port="ble4.out"/>
+                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble4.out"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="ble4.in"/>
+            <direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
+            <direct name="direct3" input="fle.clk" output="ble4.clk"/>
+          </interconnect>
+        </mode>
+        <!-- 4-LUT mode definition end -->
+      </pb_type>
+      <interconnect>
+        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
+		     The delays below come from Stratix IV. the delay through a connection block
+		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
+		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
+		     delay within the crossbar is 95 ps. 
+		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
+		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
+		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
+		     to get the part that should be marked on the crossbar.	 -->
+        <complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
+          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[3:0].in"/>
+          <delay_constant max="75e-12" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
+        </complete>
+        <complete name="clks" input="clb.clk" output="fle[3:0].clk">
+        </complete>
+        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
+               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
+               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
+               naive specification).
+          -->
+        <direct name="clbouts1" input="fle[3:0].out[0:0]" output="clb.O[3:0]"/>
+        <direct name="clbouts2" input="fle[3:0].out[1:1]" output="clb.O[7:4]"/>
+        <!-- Carry chain links -->
+        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
+          <!-- Put all inter-block carry chain delay on this one edge -->
+          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
+          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
+        </direct>
+        <direct name="carry_out" input="fle[3:3].cout" output="clb.cout">
+          <pack_pattern name="chain" in_port="fle[3:3].cout" out_port="clb.cout"/>
+        </direct>
+        <direct name="carry_link" input="fle[2:0].cout" output="fle[3:1].cin">
+          <pack_pattern name="chain" in_port="fle[2:0].cout" out_port="fle[3:1].cin"/>
+        </direct>
+      </interconnect>
+      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
+      <!-- Place this general purpose logic block in any unspecified column -->
+    </pb_type>
+    <!-- Define general purpose logic block (CLB) ends -->
+    <!-- Define single-mode dual-port memory begin -->
+    <pb_type name="memory">
+      <input name="waddr" num_pins="7"/>
+      <input name="raddr" num_pins="7"/>
+      <input name="d_in" num_pins="8"/>
+      <input name="wen" num_pins="1"/>
+      <input name="ren" num_pins="1"/>
+      <output name="d_out" num_pins="8"/>
+      <clock name="clk" num_pins="1"/>
+      <!-- Specify the 128x8=1Kbit memory block
+           Note: the delay numbers are extracted from VPR flagship XML without modification
+                 Should align to the process technology we using to create the 1K dual-port RAM
+        -->
+      <mode name="mem_128x8_dp">
+        <pb_type name="mem_128x8_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
+          <input name="waddr" num_pins="7" port_class="address"/>
+          <input name="raddr" num_pins="7" port_class="address"/>
+          <input name="d_in" num_pins="8" port_class="data_in"/>
+          <input name="wen" num_pins="1" port_class="write_en"/>
+          <input name="ren" num_pins="1" port_class="write_en"/>
+          <output name="d_out" num_pins="8" port_class="data_out"/>
+          <clock name="clk" num_pins="1" port_class="clock"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.waddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.raddr" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.d_in" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.wen" clock="clk"/>
+          <T_setup value="509e-12" port="mem_128x8_dp.ren" clock="clk"/>
+          <T_clock_to_Q max="1.234e-9" port="mem_128x8_dp.d_out" clock="clk"/>
+          <power method="pin-toggle">
+            <port name="clk" energy_per_toggle="17.9e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <direct name="waddress" input="memory.waddr" output="mem_128x8_dp.waddr">
+            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_128x8_dp.waddr"/>
+          </direct>
+          <direct name="raddress" input="memory.raddr" output="mem_128x8_dp.raddr">
+            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_128x8_dp.raddr"/>
+          </direct>
+          <direct name="data_input" input="memory.d_in" output="mem_128x8_dp.d_in">
+            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_128x8_dp.d_in"/>
+          </direct>
+          <direct name="writeen" input="memory.wen" output="mem_128x8_dp.wen">
+            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_128x8_dp.wen"/>
+          </direct>
+          <direct name="readen" input="memory.ren" output="mem_128x8_dp.ren">
+            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_128x8_dp.ren"/>
+          </direct>
+          <direct name="dataout" input="mem_128x8_dp.d_out" output="memory.d_out">
+            <delay_constant max="40e-12" in_port="mem_128x8_dp.d_out" out_port="memory.d_out"/>
+          </direct>
+          <direct name="clk" input="memory.clk" output="mem_128x8_dp.clk">
+          </direct>
+        </interconnect>
+      </mode>
+    </pb_type>
+    <!-- Define single-mode dual-port memory end -->
+    <!-- Define fracturable multiplier begin -->
+    <!-- This multiplier can operate as a 32x32 multiplier that can fracture to two 16x16 multipliers each of which can further fracture to two 8x8 multipliers 
+	   For delay modelling, the 32x32 DSP multiplier in Stratix IV has a maximum delay of 1.523 ns + 1.93 ns
+	    = 3.45 ns. The average difference between the maximum and minimum values of a dsp mac out in 36 bit multiply
+		mode is 0.51. Hence, the minimum delay is modeled as 0.776 ns + 0.984 ns = 1.760 ns.
+ 		The 16x16 mode doesn't need to sum four 16x16 multipliers, so it is a bit
+	   faster: 1.523 ns for the multiplier, and 1.09 ns for the multiplier output block.
+	    For the input and output interconnect delays, unlike Stratix IV, we don't
+	   have any routing/logic flexibility (crossbars) at the inputs.  There is some output muxing
+	   in Stratix IV and this architecture to select which multiplier outputs should go out (e.g.
+	   8x8 outputs, 16x16 or 32x32) so those are very close between the two architectures. 
+	   We take the conservative (slightly pessimistic)
+           approach modelling the input as the same as the Stratix IV input delay and the output delay the same as the Stratix IV DSP out delay.
+		   
+	   We estimate block area by using the published Stratix III data (which is architecturally identical to Stratix IV)
+	      (H. Wong, V. Betz and J. Rose, "Comparing FPGA vs. Custom CMOS and the Impact on Processor Microarchitecture", FPGA 2011) of 0.2623 
+		  mm^2 and scaling from 65 to 40 nm to obtain 0.0993 mm^2. That area is for a DSP block with approximately 2x the functionality of 
+		  the block we use (can implement two 32x32 multiplies instead of our 1, eight 16x16 multiplies instead of our 4, etc.). Hence we 
+		  divide the area by 2 to obtain 0.0497 mm^2. One minimum-width transistor units = 60 L^2 (where L = 40 nm), so is 518,000 MWTUS. 
+		  That area includes routing and the connection block input muxes.  Our DSP block is four 
+		  rows high, and hence includes four horizontal routing channel segments and four vertical ones, which is 4x the routing of a logic 
+		  block (single tile). It also includes 3.6x the outputs of a logic block, and 1.8x the inputs. Hence a slight overestimate of the routing
+		  area associated with our DSP block is four times that of a logic tile, where the routing area of a logic tile was calculated above (at W = 300)
+		  as 30481 MWTAs. Hence the (core, non-routing) area our DSP block is approximately 518,000 - 4 * 30,481 = 396,000 MWTUs.
+      -->
+    <pb_type name="mult_32">
+      <input name="a" num_pins="32"/>
+      <input name="b" num_pins="32"/>
+      <output name="out" num_pins="64"/>
+      <mode name="two_divisible_mult_16x16">
+        <pb_type name="divisible_mult_16x16" num_pb="2">
+          <input name="a" num_pins="16"/>
+          <input name="b" num_pins="16"/>
+          <output name="out" num_pins="32"/>
+          <!-- Model 8x8 delay and 16x16 delay as the same.  8x8 could be faster, but in Stratix IV
+	          isn't, presumably because the multiplier layout is really optimized for 16x16.
+		        -->
+          <mode name="two_mult_8x8">
+            <pb_type name="mult_8x8_slice" num_pb="2">
+              <input name="A_cfg" num_pins="8"/>
+              <input name="B_cfg" num_pins="8"/>
+              <output name="OUT_cfg" num_pins="16"/>
+              <pb_type name="mult_8x8" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="8"/>
+                <input name="b" num_pins="8"/>
+                <output name="out" num_pins="16"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.a" out_port="mult_8x8.out"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_8x8.b" out_port="mult_8x8.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_8x8_slice.A_cfg" output="mult_8x8.a">
+                </direct>
+                <direct name="b2b" input="mult_8x8_slice.B_cfg" output="mult_8x8.b">
+                </direct>
+                <direct name="out2out" input="mult_8x8.out" output="mult_8x8_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.45e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.45e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_16x16.a" output="mult_8x8_slice[1:0].A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_16x16.b" output="mult_8x8_slice[1:0].B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_8x8_slice[1:0].OUT_cfg" output="divisible_mult_16x16.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <mode name="mult_16x16">
+            <pb_type name="mult_16x16_slice" num_pb="1">
+              <input name="A_cfg" num_pins="16"/>
+              <input name="B_cfg" num_pins="16"/>
+              <output name="OUT_cfg" num_pins="32"/>
+              <pb_type name="mult_16x16" blif_model=".subckt multiply" num_pb="1">
+                <input name="a" num_pins="16"/>
+                <input name="b" num_pins="16"/>
+                <output name="out" num_pins="32"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_16x16.a" out_port="mult_16x16.out"/>
+                <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_16x16.b" out_port="mult_16x16.out"/>
+              </pb_type>
+              <interconnect>
+                <direct name="a2a" input="mult_16x16_slice.A_cfg" output="mult_16x16.a">
+                </direct>
+                <direct name="b2b" input="mult_16x16_slice.B_cfg" output="mult_16x16.b">
+                </direct>
+                <direct name="out2out" input="mult_16x16.out" output="mult_16x16_slice.OUT_cfg">
+                </direct>
+              </interconnect>
+              <power method="pin-toggle">
+                <port name="A_cfg" energy_per_toggle="1.09e-12"/>
+                <port name="B_cfg" energy_per_toggle="1.09e-12"/>
+                <static_power power_per_instance="0.0"/>
+              </power>
+            </pb_type>
+            <interconnect>
+              <direct name="a2a" input="divisible_mult_16x16.a" output="mult_16x16_slice.A_cfg">
+              </direct>
+              <direct name="b2b" input="divisible_mult_16x16.b" output="mult_16x16_slice.B_cfg">
+              </direct>
+              <direct name="out2out" input="mult_16x16_slice.OUT_cfg" output="divisible_mult_16x16.out">
+              </direct>
+            </interconnect>
+          </mode>
+          <power method="sum-of-children"/>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading 134 ps
+				The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps
+              -->
+          <direct name="a2a" input="mult_32.a" output="divisible_mult_16x16[1:0].a">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_32.a" out_port="divisible_mult_16x16[1:0].a"/>
+          </direct>
+          <direct name="b2b" input="mult_32.b" output="divisible_mult_16x16[1:0].b">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_32.b" out_port="divisible_mult_16x16[1:0].b"/>
+          </direct>
+          <direct name="out2out" input="divisible_mult_16x16[1:0].out" output="mult_32.out">
+            <delay_constant max="1.09e-9" min="74e-12" in_port="divisible_mult_16x16[1:0].out" out_port="mult_32.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <mode name="mult_32x32">
+        <pb_type name="mult_32x32_slice" num_pb="1">
+          <input name="A_cfg" num_pins="32"/>
+          <input name="B_cfg" num_pins="32"/>
+          <output name="OUT_cfg" num_pins="64"/>
+          <pb_type name="mult_32x32" blif_model=".subckt multiply" num_pb="1">
+            <input name="a" num_pins="32"/>
+            <input name="b" num_pins="32"/>
+            <output name="out" num_pins="64"/>
+            <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_32x32.a" out_port="mult_32x32.out"/>
+            <delay_constant max="1.523e-9" min="0.776e-9" in_port="mult_32x32.b" out_port="mult_32x32.out"/>
+          </pb_type>
+          <interconnect>
+            <direct name="a2a" input="mult_32x32_slice.A_cfg" output="mult_32x32.a">
+            </direct>
+            <direct name="b2b" input="mult_32x32_slice.B_cfg" output="mult_32x32.b">
+            </direct>
+            <direct name="out2out" input="mult_32x32.out" output="mult_32x32_slice.OUT_cfg">
+            </direct>
+          </interconnect>
+          <power method="pin-toggle">
+            <port name="A_cfg" energy_per_toggle="2.13e-12"/>
+            <port name="B_cfg" energy_per_toggle="2.13e-12"/>
+            <static_power power_per_instance="0.0"/>
+          </power>
+        </pb_type>
+        <interconnect>
+          <!-- Stratix IV input delay of 207ps is conservative for this architecture because this architecture does not have an input crossbar in the multiplier. 
+		   Subtract 72.5 ps delay, which is already in the connection block input mux, leading
+		   to a 134 ps delay.
+				The interconnect difference for DSP blocks is 0.5523, which leads to a minimum delay of 74 ps
+              -->
+          <direct name="a2a" input="mult_32.a" output="mult_32x32_slice.A_cfg">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_32.a" out_port="mult_32x32_slice.A_cfg"/>
+          </direct>
+          <direct name="b2b" input="mult_32.b" output="mult_32x32_slice.B_cfg">
+            <delay_constant max="134e-12" min="74e-12" in_port="mult_32.b" out_port="mult_32x32_slice.B_cfg"/>
+          </direct>
+          <direct name="out2out" input="mult_32x32_slice.OUT_cfg" output="mult_32.out">
+            <delay_constant max="1.93e-9" min="74e-12" in_port="mult_32x32_slice.OUT_cfg" out_port="mult_32.out"/>
+          </direct>
+        </interconnect>
+      </mode>
+      <!-- Place this multiplier block every 8 columns from (and including) the sixth column -->
+      <power method="sum-of-children"/>
+    </pb_type>
+    <!-- Define fracturable multiplier end -->
+
+  </complexblocklist>
+</architecture>

From 51c03196575fc77e2effdcbbf99a7d1f940d4ebe Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 15:32:54 -0600
Subject: [PATCH 146/148] [Regression tests] Add test case for the k4n4 with
 fracturable 32-bit multiplier

---
 .../k4_series/k4n4_frac_mult/config/task.conf | 38 +++++++++++++++++++
 1 file changed, 38 insertions(+)
 create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf

diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf
new file mode 100644
index 000000000..d338a3409
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_frac_mult/config/task.conf
@@ -0,0 +1,38 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+openfpga_vpr_device_layout=4x4
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_frac_dsp32_40nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench0_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=

From 8f4cca789a3201c7fea6936241ff769dd08160a9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 15:34:44 -0600
Subject: [PATCH 147/148] [Regression Test] Add k4n4 with fracturable
 multiplier test case to CI

---
 .travis/basic_reg_test.sh | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh
index 2a0ae6bb2..85cb514e4 100755
--- a/.travis/basic_reg_test.sh
+++ b/.travis/basic_reg_test.sh
@@ -49,5 +49,7 @@ echo -e "Testing K4N4 with block RAM";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_bram --debug --show_thread_logs
 echo -e "Testing K4N4 with multiple lengths of routing segments";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
+echo -e "Testing K4N4 with 32-bit fracturable multiplier";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"

From 7729f671ab6123fa3193a71ff1d172000e39afd9 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 22 Sep 2020 18:35:41 -0600
Subject: [PATCH 148/148] [Regression Tests] Remove deadlink

---
 openfpga_flow/tasks/generate_testbenches | 1 -
 1 file changed, 1 deletion(-)
 delete mode 120000 openfpga_flow/tasks/generate_testbenches

diff --git a/openfpga_flow/tasks/generate_testbenches b/openfpga_flow/tasks/generate_testbenches
deleted file mode 120000
index 67a0f73fe..000000000
--- a/openfpga_flow/tasks/generate_testbenches
+++ /dev/null
@@ -1 +0,0 @@
-/research/ece/lnis/USERS/DARPA_ERI/Tapeout/May2020/release/FROG_v1.0/SCRIPTS/generate_testbenches
\ No newline at end of file