diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c index a797d2bdf..00fc479ae 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c @@ -286,7 +286,8 @@ void vpr_fpga_verilog(t_vpr_setup vpr_setup, verilog_generate_sdc_pnr(sram_verilog_orgz_info, sdc_dir_path, Arch, &vpr_setup.RoutingArch, num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data, - nx, ny); + nx, ny, + vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy); } /* dump_verilog_sdc_file(); */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c index fe6f87ef8..bc95473f6 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c @@ -1052,6 +1052,7 @@ void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp) { return; } +static void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp, int LL_nx, int LL_ny) { int ix, iy, side, itrack, imux; @@ -1156,8 +1157,7 @@ void verilog_generate_sdc_disable_unused_cbs_muxs(FILE* fp, int LL_nx, int LL_ny return; } - - +static void verilog_generate_sdc_disable_unused_cbs_muxs(FILE* fp, int LL_nx, int LL_ny) { @@ -1844,6 +1844,7 @@ void verilog_generate_sdc_disable_unused_grids(FILE* fp, return; } +static void verilog_generate_sdc_disable_unused_grids_muxs(FILE* fp, int LL_nx, int LL_ny, t_grid_tile** LL_grid, @@ -1915,9 +1916,9 @@ void dump_sdc_one_clb_muxes(FILE* fp, * of the rr_graph to comment the active path and the fan_in and name * inside of the pb_graph to dump the name of the port we need to disable*/ void dump_sdc_rec_one_pb_muxes(FILE* fp, - char* grid_instance_name, - t_rr_graph* rr_graph, - t_pb_graph_node* cur_pb_graph_node) { + char* grid_instance_name, + t_rr_graph* rr_graph, + t_pb_graph_node* cur_pb_graph_node) { int mode_index; int ipb, jpb; @@ -1941,10 +1942,10 @@ void dump_sdc_rec_one_pb_muxes(FILE* fp, return; } -void dump_sdc_pb_graph_node_muxes (FILE* fp, - char* grid_instance_name, - t_rr_graph* rr_graph, - t_pb_graph_node* pb_graph_node) { +void dump_sdc_pb_graph_node_muxes(FILE* fp, + char* grid_instance_name, + t_rr_graph* rr_graph, + t_pb_graph_node* pb_graph_node) { int i_pin, i_port; // Input pins for (i_port = 0; i_port< pb_graph_node->num_input_ports; i_port++) { @@ -1967,10 +1968,10 @@ void dump_sdc_pb_graph_node_muxes (FILE* fp, return; } -void dump_sdc_pb_graph_pin_muxes (FILE* fp, - char* grid_instance_name, - t_rr_graph* rr_graph, - t_pb_graph_pin pb_graph_pin) { +void dump_sdc_pb_graph_pin_muxes(FILE* fp, + char* grid_instance_name, + t_rr_graph* rr_graph, + t_pb_graph_pin pb_graph_pin) { int i_fan_in, datapath_id, fan_in; int level_changing = 0; t_spice_model* mux_spice_model; @@ -1983,7 +1984,7 @@ void dump_sdc_pb_graph_pin_muxes (FILE* fp, /* There are three types of interconnection: same level, going down a level, going up a level * Since we check the fan_in, we need to get the right input edge mode */ if (0 == pb_graph_pin.num_input_edges || 0 == pb_graph_pin.num_output_edges) { - return; + return; } if (pb_graph_pin.input_edges[cur_mode_index]->interconnect->parent_mode != pb_graph_pin.output_edges[cur_mode_index]->interconnect->parent_mode) { if (pb_graph_pin.input_edges[cur_mode_index]->interconnect->parent_mode != cur_mode) { @@ -2174,7 +2175,8 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - int LL_nx, int LL_ny) { + int LL_nx, int LL_ny, + boolean compact_routing_hierarchy) { t_sdc_opts sdc_opts; /* Initialize */ diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.h b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.h index 8e6225ac0..c08d74031 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.h +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.h @@ -8,7 +8,8 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info, int LL_num_rr_nodes, t_rr_node* LL_rr_node, t_ivec*** LL_rr_node_indices, t_rr_indexed_data* LL_rr_indexed_data, - int LL_nx, int LL_ny); + int LL_nx, int LL_ny, + boolean compact_routing_hierarchy); void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info, char* sdc_dir, @@ -19,15 +20,6 @@ void verilog_generate_sdc_analysis(t_sram_orgz_info* cur_sram_orgz_info, t_block* LL_block, boolean compact_routing_hierarchy); -void verilog_generate_sdc_disable_unused_sbs_muxs(FILE* fp, int LL_nx, int LL_ny); - -void verilog_generate_sdc_disable_unused_cbs_muxs(FILE* fp, int LL_nx, int LL_ny); - -void verilog_generate_sdc_disable_unused_grids_muxs(FILE* fp, - int LL_nx, int LL_ny, - t_grid_tile** LL_grid, - t_block* LL_block); - void dump_sdc_one_clb_muxes(FILE* fp, char* grid_instance_name, t_rr_graph* rr_graph,