[lib] remove out-of-date files
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tangxifan
parent
14726e9317
commit
e2e212cec4
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@ -1,165 +0,0 @@
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/* (C) 2018 - genBTC, All Rights Reserved */
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/* November 17, 2018 */
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#include <iostream>
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#include <fstream>
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#include <string>
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#include <sstream>
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#include <vector>
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#include <algorithm>
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#include <map>
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#include <climits>
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struct PCFlayout {
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std::string pinName; //with the [7:0] bitfield(maybe)
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int pinNameBit = 0;
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std::string pinNameBase; //without the bitfield
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std::string pinNum;
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int pinNumInt;
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std::string comment;
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};
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struct Veriloglayout {
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std::string inpout;
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std::string bitfield;
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int bits = 1;
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int hibit = INT_MAX;
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int lobit = 0;
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std::string pinName;
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std::string comment;
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};
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#define TEST_PRINT_VERILOG_CHECK 0
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#define TEST_PCFMAP_PIN_COUNT 0
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std::vector<Veriloglayout> parseVerilog(const char* verilogfile) {
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std::vector<Veriloglayout> v;
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std::ifstream input(verilogfile); // open the file
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std::string line; // iterate each line
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while (std::getline(input, line)) { // getline returns the stream by reference, so this handles EOF
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std::stringstream ss(line); // create a stringstream out of each line
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Veriloglayout VLog_node; // start a new node
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while (ss) { // while the stream is good
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std::string word; // get first word
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if (ss >> word) { // if first word is set_io
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if (word.find("input") == 0 || word.find("output") == 0 || word.find("inout") == 0) {
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VLog_node.inpout = word;
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if (ss >> word) {
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if (word.find('[') == 0) {
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VLog_node.bitfield = word;
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VLog_node.hibit = std::stoi(word.substr(1, word.find(':')));
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VLog_node.lobit = std::stoi(word.substr(word.find(':') + 1, word.size()));
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VLog_node.bits = VLog_node.hibit - VLog_node.lobit + 1;
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ss >> VLog_node.pinName;
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}
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else
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VLog_node.pinName = word;
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//remove the ending comma
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auto l = VLog_node.pinName.size() - 1;
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if (l == VLog_node.pinName.find(','))
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VLog_node.pinName.erase(l);
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}
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break;
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}
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else if (word.find("wire") == 0) //marks a wire block.
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break;
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else if (word[0] == '#') { // if it's a comment
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int commentpos = line.find("#");
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//if its not at the beginning of the line, store it
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if (commentpos != 0)
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VLog_node.comment = line.substr(commentpos);
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break; //or ignore the full line comment and move on
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}
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else if (word.find("verilog") == 0) //marks the start of the file
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break;
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else if (word.find("module") == 0) { //marks the start of the module definition
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ss >> word; //this is the title of the module
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break;
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}
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else if (word.find(");") == 0) //marks the end of the file
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break;
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else {
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//noisy parser errors
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std::cerr << "Error @ line: " << line << "\n";
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std::cerr << "Unresolved Symbol: '" << word << "'\n";
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break; //and move onto next line. without this, it will accept more following values on this line
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}
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}
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}
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if (VLog_node.pinName == "") continue;
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v.push_back(VLog_node);
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}
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return v;
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}
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void printParsedVerilogCheck(std::vector<Veriloglayout> &vlognodes)
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{
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//visually prints Verilog data we just read into the vector - to check validity, as a Unit Test
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if (TEST_PRINT_VERILOG_CHECK) {
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std::cout << "Printing parsed Verilog:\n";
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for (auto node : vlognodes) {
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if (node.pinName.length() != 0) {
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std::cout << node.inpout << ": " << node.pinName;
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if (node.bits > 1)
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std::cout << " bits: [" << node.bits << "]";
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std::cout << " " << node.comment << std::endl;
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}
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}
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std::cout << "\n";
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}
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}
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bool comparePCFtoVerilog(std::vector<PCFlayout> &v1, std::vector<Veriloglayout> &v2){
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std::map<std::string, int> pinBitNumsMap;
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//Count up the number of PCF pins with the same name;
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for (auto &pNode : v1) {
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//make a map of the PCF to find by BaseName and count up the bits
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pinBitNumsMap[pNode.pinNameBase]++; //increment seen pin bit count
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}
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//check output:
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if (TEST_PCFMAP_PIN_COUNT) {
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std::cout << "\nCount up the number of PCF pins with the same name:\n";
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for (auto pin : pinBitNumsMap) {
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//map will be: PIN_NAME , TOTAL_BITS_ACCOUNTED_FOR
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std::cout << pin.first << " " << pin.second << "\n";
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}
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std::cout << "\n";
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}
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std::cout << "Comparing parsed_Verilog with parsed_PCF:\n";
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bool hasMismatches{ false }; int mismatches_found = 0;
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//O(n^2)? = meh
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for (auto pin : pinBitNumsMap) {
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for (auto vNode : v2) {
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if (pin.first.find(vNode.pinName) == 0) {
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if (pin.second != vNode.bits) {
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std::cout << "Verilog @ " << vNode.pinName << " [" << vNode.bits << "]\n";
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std::cout << " NOT EQUAL: \n";
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std::cout << "PCFfile @ " << pin.first << " [" << pin.second << "]\n";
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hasMismatches = true; ++mismatches_found;
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break;
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}
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}
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}
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}
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if (hasMismatches || mismatches_found)
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std::cout << "\n" << mismatches_found << " Mis-Matches Found!\n";
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std::cout << "\nComparing parsed_PCF pin name bit number with parsed_Verilog bit field:\n";
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std::cout << "Finds errors where pin bit name is less than or greater than than the Verilog.v bit-field\n";
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//Finds Bit-Range errors between .PCF and .V
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for (auto pNode : v1) {
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for (auto vNode : v2) {
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if (pNode.pinName.find(vNode.pinName) == 0) {
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if (pNode.pinNameBit < vNode.lobit) {
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std::cout << "Error: " << pNode.pinName << " @ .PCF = " << pNode.pinNameBit << " < " << vNode.lobit << " @ .V \n";
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}
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else if (pNode.pinNameBit > vNode.hibit) {
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std::cout << "Error: " << pNode.pinName << " @ .PCF = " << pNode.pinNameBit << " > " << vNode.hibit << " @ .V \n";
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}
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}
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}
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}
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return hasMismatches;
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}
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