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Typo fixing

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AurelienUoU 2019-09-30 10:38:02 -06:00
parent 74f7a3cfb2
commit e2867019e1
1 changed files with 19 additions and 19 deletions
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docs/source/arch_lang/interconnect.rst
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@ -1,12 +1,12 @@
Interconnection extensions
==========================
This section will introduce extensions on the architecture description file about existing interconnection description.
This section introduces extensions on the architecture description file about existing interconnection description.
Directlist
----------
The original direct connections in the directlist section is doccumented here_. Its description is given below:
The original direct connections in the directlist section are documented here_. Its description is given below:
.. _here: http://docs.verilogtorouting.org/en/latest/arch/reference/?highlight=directlist#direct-inter-block-connections
@ -78,12 +78,12 @@ For this example, we will study a scan-chain implementation.The description coul
An example of scan-chain implementation
In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB together.
In this figure, the red arrows represent the initial direct connection. The green arrows represent the point to point connection to connect all the columns of CLB.
Truth table
-----------
A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his own point to point connection, a truth table with our new parameters id provided below.
A point to point connection can be applied in different ways than showed in the example section. To help the designer implement his point to point connection, a truth table with our new parameters id provided below.
:numref:`fig_p2p_trtable` provides all possible variable combination and the connection it will generate.