From e17a5cbbf2944fbe8288752f91d8f0a8bb3171f5 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 19 Jan 2021 15:52:51 -0700
Subject: [PATCH] [Test] Rename to pin constraint to comply with libpcf
 requirement

---
 .../config/{fpga_port_nets.xml => pin_constraints.xml}    | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
 rename openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/{fpga_port_nets.xml => pin_constraints.xml} (62%)

diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml
similarity index 62%
rename from openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml
rename to openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml
index 5b8ec18d3..90523a274 100644
--- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/fpga_port_nets.xml
+++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_4clock/config/pin_constraints.xml
@@ -1,9 +1,9 @@
-<fpga_port_nets>
+<pin_constraints>
   <!-- For a given .blif file, we want to assign 
        - the clk0 signal to the clk[0] port of the FPGA fabric
        - the clk1 signal to the clk[1] port of the FPGA fabric
     -->
-  <port net="clk0" fpga="clk[0]"/>
-  <port net="clk1" fpga="clk[1]"/>
-</fpga_port_nets>
+  <set_io pin="clk[0]" net="clk0"/>
+  <set_io pin="clk[1]" net="clk1"/>
+</pin_constraints>