From e0f9547f5b9e5c23238eb294047c3b16b9e99552 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 24 Sep 2020 19:53:54 -0600 Subject: [PATCH] [Architecture] Rework the i/o cell Verilog HDL --- openfpga_flow/VerilogNetlists/gpio.v | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 openfpga_flow/VerilogNetlists/gpio.v diff --git a/openfpga_flow/VerilogNetlists/gpio.v b/openfpga_flow/VerilogNetlists/gpio.v new file mode 100644 index 000000000..5fb318f3d --- /dev/null +++ b/openfpga_flow/VerilogNetlists/gpio.v @@ -0,0 +1,20 @@ +//----------------------------------------------------- +// Design Name : General Purpose I/Os +// File Name : gpio.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A minimum general purpose I/O +//----------------------------------------------------- +module GPIO ( + input A, // Data output + output Y, // Data input + inout PAD, // bi-directional pad + input DIR // direction control +); + //----- when direction enabled, the signal is propagated from PAD to data input + assign Y = DIR ? PAD : 1'bz; + //----- when direction is disabled, the signal is propagated from data out to pad + assign PAD = DIR ? 1'bz : A; +endmodule