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[HDL] Remove redundant comments

This commit is contained in:
tangxifan 2021-02-01 10:33:08 -07:00
parent 39543f7945
commit e0e2506e32
1 changed files with 0 additions and 2 deletions
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openfpga_flow/openfpga_cell_library/verilog/mux2.v
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@ -63,8 +63,6 @@ endmodule
//----------------------------------------------------- //-----------------------------------------------------
module CARRY_MUX2( module CARRY_MUX2(
// iVerilog is buggy on the 'input A' declaration when deposit initial
// values
input [0:0] A, // Data input 0 input [0:0] A, // Data input 0
input [0:0] B, // Data input 1 input [0:0] B, // Data input 1
input [0:0] S0, // Select port input [0:0] S0, // Select port