riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[test] typo

This commit is contained in:
tangxifan 2024-07-01 20:34:37 -07:00
parent 1bfcf7574c
commit e00312d29e
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
openfpga_flow/tasks/basic_tests/clock_network/homo_1clock_1reset_2layer_syntax/config/clk_arch_1clk_1rst_2layer.xml
View File

@ -11,7 +11,7 @@
<spine name="clk_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="clk_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<region from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]" start_x="1" start_y="1" end_x="2" endy="1" repeat_x="1" repeat_y="1"/>
<region from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]" start_x="1" start_y="1" end_x="2" end_y="1" repeat_x="1" repeat_y="1"/>
<single from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]" x="1" y="2"/>
<single from_pin="op_clk[0:0]" to_pin="clb[0:0].clk[0:0]" x="2" y="2"/>
</taps>
@ -28,7 +28,7 @@
<spine name="rst_rib_lvl1_sw1_upper" start_x="2" start_y="2" end_x="2" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rst_rib_lvl1_sw1_lower" start_x="2" start_y="1" end_x="2" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<region from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]" start_x="1" start_y="1" end_x="2" endy="1" repeat_x="1" repeat_y="1"/>
<region from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]" start_x="1" start_y="1" end_x="2" end_y="1" repeat_x="1" repeat_y="1"/>
<single from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]" x="1" y="2"/>
<single from_pin="op_reset[0:0]" to_pin="clb[0:0].reset[0:0]" x="2" y="2"/>
</taps>