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[engine] resolve compilation warnings

This commit is contained in:
tangxifan 2022-08-17 16:32:21 -07:00
parent fef7991952
commit dfe30df462
3 changed files with 29 additions and 29 deletions
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32
openfpga/src/fpga_spice/spice_constants.h
View File

@ -4,26 +4,26 @@
/* global parameters for dumping spice netlists */
constexpr size_t SPICE_NETLIST_MAX_NUM_PORTS_PER_LINE = 10;
constexpr char* SPICE_NETLIST_FILE_POSTFIX = ".sp";
constexpr const char* SPICE_NETLIST_FILE_POSTFIX = ".sp";
constexpr char* TRANSISTOR_WRAPPER_POSTFIX = "_wrapper";
constexpr const char* TRANSISTOR_WRAPPER_POSTFIX = "_wrapper";
constexpr char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
constexpr char* SUPPLY_WRAPPER_SPICE_FILE_NAME = "supply_wrapper.sp";
constexpr char* MUX_PRIMITIVES_SPICE_FILE_NAME = "mux_primitives.sp";
constexpr char* MUXES_SPICE_FILE_NAME = "muxes.sp";
constexpr char* LUTS_SPICE_FILE_NAME = "luts.sp";
constexpr char* MEMORIES_SPICE_FILE_NAME = "memories.sp";
constexpr char* FABRIC_INCLUDE_SPICE_NETLIST_FILE_NAME = "fabric_netlists.sp";
constexpr const char* TRANSISTORS_SPICE_FILE_NAME = "transistor.sp";
constexpr const char* SUPPLY_WRAPPER_SPICE_FILE_NAME = "supply_wrapper.sp";
constexpr const char* MUX_PRIMITIVES_SPICE_FILE_NAME = "mux_primitives.sp";
constexpr const char* MUXES_SPICE_FILE_NAME = "muxes.sp";
constexpr const char* LUTS_SPICE_FILE_NAME = "luts.sp";
constexpr const char* MEMORIES_SPICE_FILE_NAME = "memories.sp";
constexpr const char* FABRIC_INCLUDE_SPICE_NETLIST_FILE_NAME = "fabric_netlists.sp";
constexpr char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
constexpr char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
constexpr const char* SPICE_SUBCKT_VDD_PORT_NAME = "VDD";
constexpr const char* SPICE_SUBCKT_GND_PORT_NAME = "VSS";
constexpr char* SPICE_MUX_BASIS_POSTFIX = "_basis";
constexpr char* SPICE_MEM_POSTFIX = "_mem";
constexpr const char* SPICE_MUX_BASIS_POSTFIX = "_basis";
constexpr const char* SPICE_MEM_POSTFIX = "_mem";
constexpr char* SB_SPICE_FILE_NAME_PREFIX = "sb_";
constexpr char* LOGICAL_MODULE_SPICE_FILE_NAME_PREFIX = "logical_tile_";
constexpr char* GRID_SPICE_FILE_NAME_PREFIX = "grid_";
constexpr const char* SB_SPICE_FILE_NAME_PREFIX = "sb_";
constexpr const char* LOGICAL_MODULE_SPICE_FILE_NAME_PREFIX = "logical_tile_";
constexpr const char* GRID_SPICE_FILE_NAME_PREFIX = "grid_";
#endif

24
openfpga/src/fpga_verilog/verilog_top_testbench_memory_bank.cpp
View File

@ -40,18 +40,18 @@
/* begin namespace openfpga */
namespace openfpga {
constexpr char* TOP_TB_BL_SHIFT_REGISTER_CLOCK_PORT_NAME = "bl_sr_clock";
constexpr char* TOP_TB_WL_SHIFT_REGISTER_CLOCK_PORT_NAME = "wl_sr_clock";
constexpr char* TOP_TB_VIRTUAL_BL_SHIFT_REGISTER_CLOCK_PORT_NAME = "virtual_bl_sr_clock";
constexpr char* TOP_TB_VIRTUAL_WL_SHIFT_REGISTER_CLOCK_PORT_NAME = "virtual_wl_sr_clock";
constexpr char* TOP_TB_START_BL_SHIFT_REGISTER_PORT_NAME = "start_bl_sr";
constexpr char* TOP_TB_START_WL_SHIFT_REGISTER_PORT_NAME = "start_wl_sr";
constexpr char* TOP_TB_BL_SHIFT_REGISTER_COUNT_PORT_NAME = "bl_sr_count";
constexpr char* TOP_TB_WL_SHIFT_REGISTER_COUNT_PORT_NAME = "wl_sr_count";
constexpr char* TOP_TB_BITSTREAM_BL_HEAD_WIDTH_VARIABLE = "BITSTREAM_BL_HEAD_WIDTH";
constexpr char* TOP_TB_BITSTREAM_WL_HEAD_WIDTH_VARIABLE = "BITSTREAM_WL_HEAD_WIDTH";
constexpr char* TOP_TB_BITSTREAM_BL_WORD_SIZE_VARIABLE = "BITSTREAM_BL_WORD_SIZE";
constexpr char* TOP_TB_BITSTREAM_WL_WORD_SIZE_VARIABLE = "BITSTREAM_WL_WORD_SIZE";
constexpr const char* TOP_TB_BL_SHIFT_REGISTER_CLOCK_PORT_NAME = "bl_sr_clock";
constexpr const char* TOP_TB_WL_SHIFT_REGISTER_CLOCK_PORT_NAME = "wl_sr_clock";
constexpr const char* TOP_TB_VIRTUAL_BL_SHIFT_REGISTER_CLOCK_PORT_NAME = "virtual_bl_sr_clock";
constexpr const char* TOP_TB_VIRTUAL_WL_SHIFT_REGISTER_CLOCK_PORT_NAME = "virtual_wl_sr_clock";
constexpr const char* TOP_TB_START_BL_SHIFT_REGISTER_PORT_NAME = "start_bl_sr";
constexpr const char* TOP_TB_START_WL_SHIFT_REGISTER_PORT_NAME = "start_wl_sr";
constexpr const char* TOP_TB_BL_SHIFT_REGISTER_COUNT_PORT_NAME = "bl_sr_count";
constexpr const char* TOP_TB_WL_SHIFT_REGISTER_COUNT_PORT_NAME = "wl_sr_count";
constexpr const char* TOP_TB_BITSTREAM_BL_HEAD_WIDTH_VARIABLE = "BITSTREAM_BL_HEAD_WIDTH";
constexpr const char* TOP_TB_BITSTREAM_WL_HEAD_WIDTH_VARIABLE = "BITSTREAM_WL_HEAD_WIDTH";
constexpr const char* TOP_TB_BITSTREAM_BL_WORD_SIZE_VARIABLE = "BITSTREAM_BL_WORD_SIZE";
constexpr const char* TOP_TB_BITSTREAM_WL_WORD_SIZE_VARIABLE = "BITSTREAM_WL_WORD_SIZE";
void print_verilog_top_testbench_ql_memory_bank_port(std::fstream& fp,
const ModuleManager& module_manager,

2
vtr-verilog-to-routing

@ -1 +1 @@
Subproject commit 674a569688455eccbd620e0612afaf50763c7652
Subproject commit 090322cd55f02e6f2d359e58afd91c3e486bfba9