riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[Tool] Patch repacker to support duplicated nets due to adder nets

This commit is contained in:
tangxifan 2021-02-23 19:01:18 -07:00
parent ad25944e59
commit df7b436ac7
1 changed files with 15 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
openfpga/src/repack/repack.cpp
View File

@ -259,13 +259,25 @@ std::vector<int> find_pb_route_remapped_source_pb_pin(const t_pb* pb,
/* Only care the pin has the same parent port as source_pb_pin
* Due to that the source_pb_pin may be swapped during routing
* the pb_route is out-of-date
*
* For those parent port is defined as non-equivalent,
* the source pin and the pin recorded in the routing trace must match!
*
* TODO: should update pb_route by post routing results
* On the other side, the swapping can only happen between equivalent pins
* in a port. So the port must match here!
*/
if (PortEquivalence::FULL == source_pb_pin->port->equivalent) {
if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) {
pb_route_indices.push_back(pin);
}
} else {
/* NOTE: INSTANCE is NOT supported! We support only NONE equivalent */
VTR_ASSERT (PortEquivalence::NONE == source_pb_pin->port->equivalent);
if (source_pb_pin == pb->pb_route.at(pin).pb_graph_pin) {
pb_route_indices.push_back(pin);
}
}
}
return pb_route_indices;