From df53f6da2c6c1ec41fae328caa5b9142de779a3b Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Fri, 5 Jul 2019 13:41:34 -0600 Subject: [PATCH] Updates FPGA-Verilog command lines --- docs/source/fpga_verilog/command_line_usage.rst | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/docs/source/fpga_verilog/command_line_usage.rst b/docs/source/fpga_verilog/command_line_usage.rst index aa5b8f702..dfe34eaea 100644 --- a/docs/source/fpga_verilog/command_line_usage.rst +++ b/docs/source/fpga_verilog/command_line_usage.rst @@ -40,6 +40,13 @@ FPGA-Verilog Supported Options:: ", "Prints a testbench stimulating the generated FPGA and the initial benchmark to compare stimuli responses, which includes programming phase and operationg phase (random patterns)" "--fpga_verilog_print_formal_verification_top_netlist", "Prints a Verilog top file compliant with formal verification tools. With this top file the FPGA is initialy programmed. It also prints a testbench with random patterns, which can be manually or automatically check regarding previous options." "--fpga_verilog_include_icarus_simulator", "Activates waveforms .vcd file generation and simulation timeout, which are required for Icarus Verilog simulator" + "--fpga_verilog_print_input_blif_testbench", "Generates a Verilog test-bench to use with input blif file" + "--fpga_verilog_print_report_timing_tcl", "Generates tcl commands to run STA analysis with TO COMPLETE TOOL" + "--fpga_verilog_report_timing_rpt_path ", "Specifies path where report timing are written" + "--fpga_verilog_print_sdc_pnr", "Generates SDC constraints to PNR" + "--fpga_verilog_print_sdc_analysis", "Generates SDC to run timing analysis in PNR tool" + "--fpga_verilog_print_user_defined_template", "Generates a template of hierarchy modules and their port mapping" + "", "" >>>>>>> f56adc681567b73c7826228641e089482dffc009 .. note:: The selected directory will contain the *Verilog top file* and three other folders. The folders are: