From df23daf0265eb318494da155e1a8b3dfb8bbef61 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 1 Jul 2024 17:37:16 -0700
Subject: [PATCH] [lib] sanity check on global port name and from pin name of
 tap points

---
 .../src/base/clock_network.cpp                | 19 ++++++++++++++++++-
 .../src/base/clock_network.h                  |  1 +
 2 files changed, 19 insertions(+), 1 deletion(-)

diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp
index e95df9f68..440870f29 100644
--- a/libs/libclkarchopenfpga/src/base/clock_network.cpp
+++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp
@@ -859,6 +859,23 @@ bool ClockNetwork::link() {
   return true;
 }
 
+bool ClockNetwork::validate_tree_taps() const {
+  for (ClockTreeId tree_id : trees()) {
+    for (ClockTapId tap_id : tree_taps(tree_id)) {
+      /* The from pin name should match the global port */
+      if (!tree_global_port(tree_id).mergeable(tap_from_port(tap_id)) || !tree_global_port(tree_id).contained(tap_from_port(tap_id))) {
+        VTR_LOG_ERROR(
+          "Tap point from_port '%s' is not part of the global port '%s' of tree '%s'\n",
+          tap_from_port(tap_id).to_verilog_string().c_str(),
+          tree_global_port(tree_id).to_verilog_string().c_str(),
+          tree_name(tree_id).c_str());
+        return false;
+      }
+    }
+  }
+  return true;
+}
+
 bool ClockNetwork::validate_tree() const {
   for (ClockTreeId tree_id : trees()) {
     for (ClockSpineId spine_id : spines(tree_id)) {
@@ -920,7 +937,7 @@ bool ClockNetwork::validate_tree() const {
 bool ClockNetwork::validate() const {
   is_dirty_ = true;
   if (default_segment_id_ && default_tap_switch_id_ &&
-      default_driver_switch_id_ && validate_tree()) {
+      default_driver_switch_id_ && validate_tree() && validate_tree_taps()) {
     is_dirty_ = false;
   }
   return true;
diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h
index ebfcbf038..ffec611df 100644
--- a/libs/libclkarchopenfpga/src/base/clock_network.h
+++ b/libs/libclkarchopenfpga/src/base/clock_network.h
@@ -266,6 +266,7 @@ class ClockNetwork {
  private: /* Public invalidators/validators */
   /* Ensure tree data is clean. All the spines are valid, and switch points are
    * valid */
+  bool validate_tree_taps() const;
   bool validate_tree() const;
   /* Show if the internal driver id is a valid for data queries */
   bool valid_internal_driver_id(