diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif
new file mode 100644
index 000000000..6ee9c8583
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.blif
@@ -0,0 +1,18 @@
+# Use a FF with constant input to connect a clock signal (frequency divided by 2) from a global network to datapath
+# Use an external signal to enable the clock signal
+.model clk_gate
+.inputs clk_i data_i
+.outputs data_o
+
+.names $true
+1
+
+.names $true ff_i
+1 1
+
+.names ff_o data_i data_o
+11 1
+
+.latch ff_i ff_o re clk_o 0 
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v
new file mode 100644
index 000000000..382fc03a5
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/clk_gate/clk_gate.v
@@ -0,0 +1,23 @@
+/////////////////////////////////////////
+//  Functionality: Use clock to gate the output of an AND2 gate
+//                 This is to test if LUTs can be mapped as wires
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module clk_gate(
+  clk_i,
+  data_i,
+  data_o);
+
+input wire clk_i;
+input wire data_i;
+output wire data_o;
+reg q;
+
+always @(posedge clk_i) begin
+  q <= 1;
+end
+assign data_o = data_i & q;
+
+endmodule