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reserve all the input/output net storage in bitstream manager

This commit is contained in:
tangxifan 2020-07-02 19:17:34 -06:00
parent f97e3bfba6
commit dee4be96af
5 changed files with 42 additions and 7 deletions
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28
libopenfpga/libfpgabitstream/src/bitstream_manager.cpp
View File

@ -15,6 +15,8 @@ namespace openfpga {
BitstreamManager::BitstreamManager() {
num_blocks_ = 0;
num_bits_ = 0;
invalid_block_ids_.clear();
invalid_bit_ids_.clear();
}
/**************************************************
@ -39,7 +41,7 @@ bool BitstreamManager::bit_value(const ConfigBitId& bit_id) const {
/* Ensure a valid id */
VTR_ASSERT(true == valid_bit_id(bit_id));
return bit_values_[bit_id];
return '1' == bit_values_[bit_id];
}
std::string BitstreamManager::block_name(const ConfigBlockId& block_id) const {
@ -146,7 +148,11 @@ ConfigBitId BitstreamManager::add_bit(const bool& bit_value) {
ConfigBitId bit = ConfigBitId(num_bits_);
/* Add a new bit, and allocate associated data structures */
num_bits_++;
bit_values_.push_back(bit_value);
if (true == bit_value) {
bit_values_.push_back('1');
} else {
bit_values_.push_back('0');
}
shared_config_bit_values_.emplace_back();
bit_parent_block_ids_.push_back(ConfigBlockId::INVALID());
@ -238,6 +244,14 @@ void BitstreamManager::add_path_id_to_block(const ConfigBlockId& block, const in
block_path_ids_[block] = path_id;
}
void BitstreamManager::reserve_block_input_net_ids(const ConfigBlockId& block,
const size_t& num_input_net_ids) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
block_input_net_ids_[block].reserve(num_input_net_ids);
}
void BitstreamManager::add_input_net_id_to_block(const ConfigBlockId& block,
const std::string& input_net_id) {
/* Ensure the input ids are valid */
@ -247,6 +261,14 @@ void BitstreamManager::add_input_net_id_to_block(const ConfigBlockId& block,
block_input_net_ids_[block].push_back(input_net_id);
}
void BitstreamManager::reserve_block_output_net_ids(const ConfigBlockId& block,
const size_t& num_output_net_ids) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_block_id(block));
block_output_net_ids_[block].reserve(num_output_net_ids);
}
void BitstreamManager::add_output_net_id_to_block(const ConfigBlockId& block,
const std::string& output_net_id) {
/* Ensure the input ids are valid */
@ -256,7 +278,7 @@ void BitstreamManager::add_output_net_id_to_block(const ConfigBlockId& block,
block_output_net_ids_[block].push_back(output_net_id);
}
void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits) {
void BitstreamManager::add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<char>& shared_config_bits) {
/* Ensure the input ids are valid */
VTR_ASSERT(true == valid_bit_id(bit));

14
libopenfpga/libfpgabitstream/src/bitstream_manager.h
View File

@ -176,14 +176,20 @@ class BitstreamManager {
/* Add a path id to a block */
void add_path_id_to_block(const ConfigBlockId& block, const int& path_id);
/* Reserve input net ids for a block */
void reserve_block_input_net_ids(const ConfigBlockId& block, const size_t& num_input_net_ids);
/* Add an input net id to a block */
void add_input_net_id_to_block(const ConfigBlockId& block, const std::string& input_net_id);
/* Reserve output net ids for a block */
void reserve_block_output_net_ids(const ConfigBlockId& block, const size_t& num_output_net_ids);
/* Add an output net id to a block */
void add_output_net_id_to_block(const ConfigBlockId& block, const std::string& output_net_id);
/* Add share configuration bits to a configuration bit */
void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<bool>& shared_config_bits);
void add_shared_config_bit_values(const ConfigBitId& bit, const std::vector<char>& shared_config_bits);
public: /* Public Validators */
bool valid_bit_id(const ConfigBitId& bit_id) const;
@ -220,7 +226,7 @@ class BitstreamManager {
* -Bitstream manager will NOT check if the id is good for bitstream builders
* It just store the results
*/
vtr::vector<ConfigBlockId, int> block_path_ids_;
vtr::vector<ConfigBlockId, uint8_t> block_path_ids_;
/* Net ids that are mapped to inputs and outputs of this block
*
@ -236,9 +242,9 @@ class BitstreamManager {
std::unordered_set<ConfigBitId> invalid_bit_ids_;
vtr::vector<ConfigBitId, ConfigBlockId> bit_parent_block_ids_;
/* value of a bit in the Bitstream */
vtr::vector<ConfigBitId, bool> bit_values_;
vtr::vector<ConfigBitId, char> bit_values_;
/* value of a shared configuration bits in the Bitstream */
vtr::vector<ConfigBitId, std::vector<bool>> shared_config_bit_values_;
vtr::vector<ConfigBitId, std::vector<char>> shared_config_bit_values_;
};
} /* end namespace openfpga */

2
openfpga/src/fpga_bitstream/build_grid_bitstream.cpp
View File

@ -221,6 +221,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
}
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, mux_input_pin_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
for (const AtomNetId& input_net : input_nets) {
if (true == atom_ctx.nlist.valid_net_id(input_net)) {
bitstream_manager.add_input_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(input_net));
@ -229,6 +230,7 @@ void build_physical_block_pin_interc_bitstream(BitstreamManager& bitstream_manag
}
}
if (true == atom_ctx.nlist.valid_net_id(output_net)) {
bitstream_manager.reserve_block_output_net_ids(mux_mem_block, 1);
bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_net));
} else {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, std::string("unmapped"));

4
openfpga/src/fpga_bitstream/build_routing_bitstream.cpp
View File

@ -105,6 +105,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
}
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
for (const ClusterNetId& input_net : input_nets) {
AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net);
if (true == atom_ctx.nlist.valid_net_id(input_atom_net)) {
@ -114,6 +115,7 @@ void build_switch_block_mux_bitstream(BitstreamManager& bitstream_manager,
}
}
AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net);
bitstream_manager.reserve_block_output_net_ids(mux_mem_block, 1);
if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_atom_net));
} else {
@ -296,6 +298,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
}
/* Record path ids, input and output nets */
bitstream_manager.add_path_id_to_block(mux_mem_block, path_id);
bitstream_manager.reserve_block_input_net_ids(mux_mem_block, input_nets.size());
for (const ClusterNetId& input_net : input_nets) {
AtomNetId input_atom_net = atom_ctx.lookup.atom_net(input_net);
if (true == atom_ctx.nlist.valid_net_id(input_atom_net)) {
@ -305,6 +308,7 @@ void build_connection_block_mux_bitstream(BitstreamManager& bitstream_manager,
}
}
AtomNetId output_atom_net = atom_ctx.lookup.atom_net(output_net);
bitstream_manager.reserve_block_output_net_ids(mux_mem_block, 1);
if (true == atom_ctx.nlist.valid_net_id(output_atom_net)) {
bitstream_manager.add_output_net_id_to_block(mux_mem_block, atom_ctx.nlist.net_name(output_atom_net));
} else {

1
openfpga/src/fpga_bitstream/fabric_bitstream.cpp
View File

@ -14,6 +14,7 @@ namespace openfpga {
*************************************************/
FabricBitstream::FabricBitstream() {
num_bits_ = 0;
invalid_bit_ids_.clear();
}
/**************************************************