From decc1dc4b25fa88a0bc69a88d9b9e32a61f8abcf Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 5 Apr 2020 17:39:30 -0600
Subject: [PATCH] debugged global gp input/output port support

---
 openfpga/src/fpga_sdc/analysis_sdc_writer.cpp   | 11 +++++++++++
 .../src/fpga_verilog/verilog_top_testbench.cpp  | 17 ++++++++++++++++-
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
index aec9fc2e7..c188dedd8 100644
--- a/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
+++ b/openfpga/src/fpga_sdc/analysis_sdc_writer.cpp
@@ -192,6 +192,17 @@ void print_analysis_sdc_disable_global_ports(std::fstream& fp,
       continue;
     }
 
+    /* Skip any gpio port here! */
+    if ( (CIRCUIT_MODEL_PORT_INPUT == circuit_lib.port_type(global_port)) 
+      && (true == circuit_lib.port_is_io(global_port)) ) {
+      continue;
+    }
+
+    /* Skip any gpio port here! */
+    if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(global_port)) {
+      continue;
+    }
+
     ModulePortId module_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(global_port)); 
     BasicPort port_to_disable = module_manager.module_port(top_module, module_port);
 
diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
index 911c6defb..95f88bf92 100644
--- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
+++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp
@@ -18,6 +18,7 @@
 
 #include "bitstream_manager_utils.h"
 
+#include "openfpga_reserved_words.h"
 #include "openfpga_naming.h"
 #include "simulation_utils.h"
 #include "openfpga_atom_netlist_utils.h"
@@ -272,9 +273,23 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
       continue;
     }
 
+    /* Bypass gp output signals, they do not need any drivers */
+    if (CIRCUIT_MODEL_PORT_OUTPUT == circuit_lib.port_type(model_global_port)) {
+      continue;
+    }
+
+    /* Find the port name, gpio port has special names */
+    std::string port_name;
+    if (true == circuit_lib.port_is_io(model_global_port)) {
+      port_name = generate_fpga_global_io_port_name(std::string(GIO_INOUT_PREFIX), circuit_lib, circuit_lib.port_parent_model(model_global_port), model_global_port);
+    } else {
+      VTR_ASSERT_SAFE(false == circuit_lib.port_is_io(model_global_port));
+      port_name = circuit_lib.port_prefix(model_global_port);
+    }
+
     /* Reach here, it means we have a port to deal with */
     /* Find the module port and wire it to constant values */
-    ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
+    ModulePortId module_global_port = module_manager.find_module_port(top_module, port_name);
     VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
 
     BasicPort module_port = module_manager.module_port(top_module, module_global_port);