From de48b8c7b2f01ae9d81c6b2a81a9a3162796d0c1 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 17 Sep 2020 10:21:25 -0600
Subject: [PATCH] [Benchmark]  Add a new micro benchmark to test fracturable
 LUTs

---
 .../micro_benchmark/and2_or2/and2_or2.act     |  4 ++++
 .../micro_benchmark/and2_or2/and2_or2.blif    | 11 ++++++++++
 .../micro_benchmark/and2_or2/and2_or2.v       | 22 +++++++++++++++++++
 3 files changed, 37 insertions(+)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
new file mode 100644
index 000000000..33c156f30
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.act
@@ -0,0 +1,4 @@
+a 0.5 0.5
+b 0.5 0.5
+c 0.25 0.25
+d 0.25 0.25
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
new file mode 100644
index 000000000..88e7fcf9a
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.blif
@@ -0,0 +1,11 @@
+.model and2_or2
+.inputs a b
+.outputs c d
+
+.names a b c
+11 1
+
+.names a b d
+00 1
+
+.end
diff --git a/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
new file mode 100644
index 000000000..b57cdeffe
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/and2_or2/and2_or2.v
@@ -0,0 +1,22 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND + 2-input OR 
+//                 This benchmark is designed to test fracturable LUTs
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and2_or2(
+  a,
+  b,
+  c,
+  d);
+
+input wire a;
+input wire b;
+output wire c;
+output wire d;
+
+assign c = a & b;
+assign d = a | b;
+
+endmodule