diff --git a/docs/source/manual/arch_lang/annotate_vpr_arch.rst b/docs/source/manual/arch_lang/annotate_vpr_arch.rst index 69aed061e..39e02269c 100644 --- a/docs/source/manual/arch_lang/annotate_vpr_arch.rst +++ b/docs/source/manual/arch_lang/annotate_vpr_arch.rst @@ -4,86 +4,6 @@ Bind circuit modules to VPR architecture ---------------------------------------- Each defined circuit model should be linked to an FPGA module defined in the original part of architecture descriptions. It helps FPGA-circuit creating the circuit netlists for logic/routing blocks. Since the original part lacks such support, we create a few XML properties to link to Circuit models. -Configuration Protocol -~~~~~~~~~~~~~~~~~~~~~~ - -Configuration protocol is the circuitry designed to program an FPGA. -As an interface, configuration protocol could be really different in FPGAs, depending on the application context. - -Template -```````` - -.. code-block:: xml - - - - - -.. option:: type="scan_chain|memory_bank|standalone" - - Specify the type of configuration circuits. - - OpenFPGA supports different types of configuration protocols to program FPGA fabrics: - - ``scan_chain``: configurable memories are connected in a chain. Bitstream is loaded serially to program a FPGA - - ``memory_bank``: configurable memories are organized in an array, where each element can be accessed by an unique address to the BL/WL decoders - - ``standalone``: configurable memories are directly accessed through ports of FPGA fabrics. In other words, there are no protocol to control the memories. This allows full customization on the configuration protocol for hardware engineers. - - .. note:: Avoid to use ``standalone`` when designing an FPGA chip. It will causes a huge number of I/Os required, far beyond any package size. It is well applicable to eFPGAs, where designers do need customized protocols between FPGA and processors. - -.. warning:: Currently FPGA-SPICE only supports standalone memory organization. - -.. warning:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator. - -.. option:: circuit_model_name="" - - Specify the name of circuit model to be used as configurable memory. - - ``scan_chain`` requires a circuit model type of ``ccff`` - - ``memory_bank`` requires a circuit model type of ``sram`` - - ``standalone`` requires a circuit model type of ``sram`` - -Configuration Chain Example -``````````````````````````` -The following XML code describes a scan-chain circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_ccff_fpga`. -It will use the circuit model defined in :ref:`circuit_model_examples`. - -.. code-block:: xml - - - - - -.. _fig_ccff_fpga: - -.. figure:: figures/ccff_fpga.png - :scale: 60% - :alt: map to buried treasure - - Example of a configuration chain to program core logic of a FPGA - -Memory bank Example -``````````````````` -The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`. -It will use the circuit model defined in :ref:`circuit_model_examples`. - -.. code-block:: xml - - - - - -.. _fig_sram: - -.. figure:: figures/sram.png - :scale: 60% - :alt: map to buried treasure - - Example of a memory organization using memory decoders - -Standalone SRAM Example -``````````````````````` - -.. warning:: TO BE CONSTRUCTED - Switch Blocks ~~~~~~~~~~~~~ diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index 9b689d2f7..e93d18e6a 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -240,7 +240,62 @@ Template .. note:: The information of input and output buffer should be clearly specified according to the customized Verilog/SPICE netlist! The existence of input/output buffers will influence the decision in creating testbenches, which may leads to larger errors in power analysis. -.. note:: The support SRAM modules should have a BL and a WL when the memory-bank-style configuration circuit is declared. Note that the WL should be the write/read enable signal, while BL is the data input. +SRAM with BL/WL +``````````````` +.. _fig_sram_blwl: + +.. figure:: ./figures/sram_blwl.png + :scale: 100% + + An example of a SRAM with Bit-Line (BL) and Word-Line (WL) control signals + +The following XML codes describes the SRAM cell shown in :numref:`fig_sram_blwl`. + +.. code-block:: xml + + + + + + + + + + + + +.. note:: OpenFPGA always assume that a ``WL`` port should be the write/read enable signal, while a ``BL`` port is the data input. + +.. note:: When the ``memory_bank`` type of configuration procotol is specified, SRAM modules should have a BL and a WL. + +Configurable Latch +`````````````````` + +.. _fig_config_latch: + +.. figure:: ./figures/config_latch.png + :scale: 100% + + An example of a SRAM-based configurable latch with Bit-Line (BL) and Word-Line (WL) control signals + +The following XML codes describes the configurable latch shown in :numref:`fig_config_latch`. + +.. code-block:: xml + + + + + + + + + + + + +.. note:: OpenFPGA always assume that a ``WL`` port should be the write/read enable signal, while a ``BL`` port is the data input. + +.. note:: When the ``frame_based`` type of configuration procotol is specified, the configurable latch or a SRAM with ``BL`` and ``WL`` should be specified. Logic gates ~~~~~~~~~~~ diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst new file mode 100644 index 000000000..f37c7f18b --- /dev/null +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -0,0 +1,126 @@ +.. _config_protocol: + +Configuration Protocol +---------------------- + +Configuration protocol is the circuitry designed to program an FPGA. +As an interface, configuration protocol could be really different in FPGAs, depending on the application context. +OpenFPGA supports versatile configuration protocol, providing different trade-offs between speed and area. + +Template +~~~~~~~~ + +.. code-block:: xml + + + + + +.. option:: type="scan_chain|memory_bank|standalone" + + Specify the type of configuration circuits. + + OpenFPGA supports different types of configuration protocols to program FPGA fabrics: + - ``scan_chain``: configurable memories are connected in a chain. Bitstream is loaded serially to program a FPGA + - ``frame_based``: configurable memories are organized by frames. Each module of a FPGA fabric, e.g., Configurable Logic Block (CLB), Switch Block (SB) and Connection Block (CB), is considered as a frame of configurable memories. Inside each frame, all the memory banks are accessed through an address decoder. Users can write each memory cell with a specific address. Note that the frame-based memory organization is applid hierarchically. Each frame may consists of a number of sub frames, each of which follows the similar organization. + - ``memory_bank``: configurable memories are organized in an array, where each element can be accessed by an unique address to the BL/WL decoders + - ``standalone``: configurable memories are directly accessed through ports of FPGA fabrics. In other words, there are no protocol to control the memories. This allows full customization on the configuration protocol for hardware engineers. + + .. note:: Avoid to use ``standalone`` when designing an FPGA chip. It will causes a huge number of I/Os required, far beyond any package size. It is well applicable to eFPGAs, where designers do need customized protocols between FPGA and processors. + +.. warning:: Currently FPGA-SPICE only supports standalone memory organization. + +.. warning:: Currently RRAM-based FPGA only supports memory-bank organization for Verilog Generator. + +.. option:: circuit_model_name="" + + Specify the name of circuit model to be used as configurable memory. + - ``scan_chain`` requires a circuit model type of ``ccff`` + - ``frame_based`` requires a circuit model type of ``sram`` + - ``memory_bank`` requires a circuit model type of ``sram`` + - ``standalone`` requires a circuit model type of ``sram`` + +Configuration Chain Example +~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The following XML code describes a scan-chain circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_ccff_fpga`. +It will use the circuit model defined in :numref:`fig_ccff`. + +.. code-block:: xml + + + + + +.. _fig_ccff_fpga: + +.. figure:: figures/ccff_fpga.png + :scale: 60% + :alt: map to buried treasure + + Example of a configuration chain to program core logic of a FPGA + +Frame-based Example +~~~~~~~~~~~~~~~~~~~ +The following XML code describes frame-based memory banks to configure the core logic of FPGA. +It will use the circuit model defined in :numref:`fig_config_latch`. + +.. code-block:: xml + + + + + +Through frame-based configuration protocol, each memory cell can be accessed with an unique address given to decoders. +:numref:`fig_frame_config_protocol_example` illustrates an example about how the configurable memories are organizaed inside a Logic Element (LE) shown in :numref:`fig_k4n4_arch`. +The decoder inside the LE will enable the decoders of the Look-Up Table (LUT) and the routing multiplexer, based on the given address at ``address[2:2]``. +When the decoder of sub block, e.g., the LUT, is enabled, each memory cells can be accessed throught the ``address[1:0]`` and the data to write is provided at ``data_in``. + +.. _fig_frame_config_protocol_example: + +.. figure:: figures/frame_config_protocol_example.png + :scale: 25% + :alt: map to buried treasure + + Example of a frame-based memory organization inside a Logic Element + +:numref:`fig_frame_config_protocol` shows a hierarchical view on how the frame-based decoders across a FPGA fabric. + +.. _fig_frame_config_protocol: + +.. figure:: figures/frame_config_protocol.png + :scale: 60% + :alt: map to buried treasure + + Frame-based memory organization in a hierarchical view + +.. note:: Frame-based decoders does require a memory cell to have + + - two outputs (one regular and another inverted) + - a Bit-Line input to load the data + - a Word-Line input to enable data write + +Memory bank Example +~~~~~~~~~~~~~~~~~~~ +The following XML code describes a memory-bank circuitry to configure the core logic of FPGA, as illustrated in :numref:`fig_sram`. +It will use the circuit model defined in :numref:`fig_sram_blwl`. + +.. code-block:: xml + + + + + +.. _fig_sram: + +.. figure:: figures/sram.png + :scale: 60% + :alt: map to buried treasure + + Example of a memory organization using memory decoders + +.. warning:: THIS IS STILL UNDER CONSTRUCTION + +Standalone SRAM Example +~~~~~~~~~~~~~~~~~~~~~~~ + +.. warning:: TO BE CONSTRUCTED diff --git a/docs/source/manual/arch_lang/figures/config_latch.png b/docs/source/manual/arch_lang/figures/config_latch.png new file mode 100644 index 000000000..33506a49f Binary files /dev/null and b/docs/source/manual/arch_lang/figures/config_latch.png differ diff --git a/docs/source/manual/arch_lang/figures/frame_config_protocol.png b/docs/source/manual/arch_lang/figures/frame_config_protocol.png new file mode 100644 index 000000000..2786c2416 Binary files /dev/null and b/docs/source/manual/arch_lang/figures/frame_config_protocol.png differ diff --git a/docs/source/manual/arch_lang/figures/frame_config_protocol_example.png b/docs/source/manual/arch_lang/figures/frame_config_protocol_example.png new file mode 100644 index 000000000..9cc4e7e4d Binary files /dev/null and b/docs/source/manual/arch_lang/figures/frame_config_protocol_example.png differ diff --git a/docs/source/manual/arch_lang/figures/sram_blwl.png b/docs/source/manual/arch_lang/figures/sram_blwl.png new file mode 100644 index 000000000..243420fbc Binary files /dev/null and b/docs/source/manual/arch_lang/figures/sram_blwl.png differ diff --git a/docs/source/manual/arch_lang/index.rst b/docs/source/manual/arch_lang/index.rst index b7e33de15..f2fd146fb 100644 --- a/docs/source/manual/arch_lang/index.rst +++ b/docs/source/manual/arch_lang/index.rst @@ -11,6 +11,8 @@ OpenFPGA Architecture Description addon_vpr_syntax + config_protocol + direct_interconnect simulation_setting