[doc] format
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@ -92,12 +92,12 @@ set(WITH_PARMYS OFF CACHE BOOL "Enable Yosys as elaborator and parmys-plugin as
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# TCL file/lib required to link with SWIG generated wrapper
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if (OPENFPGA_WITH_SWIG)
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#Find Tcl
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#Find Tcl
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include(FindTCL)
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message(STATUS "tcl.h path is : ${TCL_INCLUDE_PATH}")
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message(STATUS "libtcl.so path is : ${TCL_LIBRARY}")
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#Find SWIG
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#Find SWIG
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find_package(SWIG 3.0 REQUIRED)
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if (SWIG_VERSION VERSION_GREATER_EQUAL "4.1.0")
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message(WARNING "Using SWIG >= ${SWIG_VERSION} -flatstaticmethod flag for python")
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@ -165,7 +165,7 @@ else ()
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"-Wcast-align" #Warn if a cast causes memory alignment changes
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"-Wshadow" #Warn if local variable shadows another variable
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"-Wformat=2" #Sanity checks for printf-like formatting
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"-Wno-format-nonliteral" # But don't worry about non-literal formtting (i.e. run-time printf format strings)
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"-Wno-format-nonliteral" # But don't worry about non-literal formatting (i.e. run-time printf format strings)
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"-Wlogical-op" #Checks for logical op when bit-wise expected
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"-Wmissing-declarations" #Warn if a global function is defined with no declaration
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"-Wmissing-include-dirs" #Warn if a user include directory is missing
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@ -183,10 +183,10 @@ else ()
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"-Wduplicated-cond" #Warn about identical conditions in if-else chains
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"-Wduplicated-branches" #Warn when different branches of an if-else chain are equivalent
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"-Wnull-dereference" #Warn about null pointer dereference execution paths
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"-Wuninitialized" #Warn about unitialized values
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"-Wuninitialized" #Warn about uninitialized values
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"-Winit-self" #Warn about self-initialization
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"-Wcatch-value=3" #Warn when catch statements don't catch by reference
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"-Wextra-semi" #Warn about redudnant semicolons
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"-Wextra-semi" #Warn about redundant semicolons
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"-Wimplicit-fallthrough=3" #Warn about case fallthroughs, but allow 'fallthrough' comments to suppress warnings
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#GCC-like optional
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#"-Wsuggest-final-types" #Suggest where 'final' would help if specified on a type methods
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@ -201,7 +201,7 @@ else ()
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#"-Wunsafe-loop-optimizations" #Warn when loops can't be optimized
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#"-Wswitch-enum" #Warn about uncovered enumeration values in a switch (even if there is a default)
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#"-Wsign-promo" #Warn when overload resolution converts an unsigned type to signed when an unsigned overload exists
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#"-Wdouble-promotion" #Warn when float is implicitly propted to double
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#"-Wdouble-promotion" #Warn when float is implicitly prompted to double
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#"-Wuseless-cast" #Warn about casts to the same type
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#"-Wzero-as-null-pointer-constant" #Warn about using '0' instead of nullptr
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)
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2
Makefile
2
Makefile
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@ -24,7 +24,7 @@ CMAKE_BUILD_TYPE := $(shell echo ${BUILD_TYPE} | sed 's/_\?pgo//' | sed 's/_\?st
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# e.g. make CMAKE_FLAGS="-DCMAKE_CXX_COMPILER=g++-9'
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override CMAKE_FLAGS := -DCMAKE_BUILD_TYPE=${BUILD_TYPE} -G 'Unix Makefiles' ${CMAKE_FLAGS}
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# -s : Suppresss makefile output (e.g. entering/leaving directories)
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# -s : Suppress makefile output (e.g. entering/leaving directories)
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# --output-sync target : For parallel compilation ensure output for each target is synchronized (make version >= 4.0)
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MAKEFLAGS := -s
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@ -42,6 +42,6 @@ Version updates are made in the following scenario
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- significant improvements on Quality-of-Results (QoR).
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- significant changes on user interface.
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- a techical feature is developed and validated by the community, which can impact the complete design flow.
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- a technical feature is developed and validated by the community, which can impact the complete design flow.
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@ -30,7 +30,7 @@ A summary of the architectural features is as follows:
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- K4N4 Configurable Logic Block (CLB), which consists of four Basic Logic Elements (BLEs) and a fully-connected crossbar. Each BLE contains a 4-input Look-Up Table (LUT), a Flip-Flop (FF) and a 2:1 routing multiplexer
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- Length-1 routing wires interconnected by Wilton-Style Switch Block (SB)
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The VPR architecture description is designed for EDA needs mainly, which lacks the details physical modelingrequired by OpenFPGA.
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The VPR architecture description is designed for EDA needs mainly, which lacks the details physical modeling required by OpenFPGA.
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Here, we show a step-by-step adaption on the architecture template.
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Physical I/O Modeling
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@ -46,7 +46,7 @@ Once the ``openfpga.sh`` script is sourced, you can run any following commands d
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.. option:: clear-task-run <task_name>
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Clears all run diretories of the given task
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Clears all run directories of the given task
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.. option:: run-modelsim <task_name>
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@ -132,7 +132,7 @@ goto-task () {
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done
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}
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# Clears enviroment variables and fucntions
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# Clears environment variables and functions
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unset-openfpga (){
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unset -v OPENFPGA_PATH
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unset -f list-tasks run-task run-flow goto-task goto-root >/dev/null 2>&1
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