[Test] Remove unused tests

openfpga_flow/tasks/ci_tests/config/task.conf

@@ -1,40 +0,0 @@
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# Configuration file for running experiments
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
-# Each job execute fpga_flow script on combination of architecture & benchmark
-# timeout_each_job is timeout for each job
-# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
-
-[GENERAL]
-run_engine=openfpga_shell
-power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
-power_analysis = true
-spice_output=false
-verilog_output=true
-timeout_each_job = 20*60
-fpga_flow=yosys_vpr
-arch_variable_file=${PATH:TASK_DIR}/design_variables.yml 
-
-[OpenFPGA_SHELL]
-openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_fabric_example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
-openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-# Use a absolute path for the Verilog netlists to be generated
-# This is designed to allow the test case 'basic_tests/generate_testbench'
-# to use the Verilog netlists along with testbenches in HDL simulation
-openfpga_verilog_output_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/generate_fabric/latest/k6_frac_N10_tileable_40nm/and2/MIN_ROUTE_CHAN_WIDTH
-
-[ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
-
-[BENCHMARKS]
-bench0=${PATH:DESIGN_PATH}
-
-[SYNTHESIS_PARAM]
-bench_read_verilog_options_common = -nolatches
-bench0_top =${PATH:DESIGN_TOP}
-#bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
-#bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
-
-[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]

openfpga_flow/tasks/ci_tests/design_variables.yml

@@ -1 +0,0 @@
-TEST_VARIABLE: 100