diff --git a/docs/source/manual/arch_lang/config_protocol.rst b/docs/source/manual/arch_lang/config_protocol.rst index d4d4d052e..f1a816eb3 100644 --- a/docs/source/manual/arch_lang/config_protocol.rst +++ b/docs/source/manual/arch_lang/config_protocol.rst @@ -7,6 +7,17 @@ Configuration protocol is the circuitry designed to program an FPGA. As an interface, configuration protocol could be really different in FPGAs, depending on the application context. OpenFPGA supports versatile configuration protocol, providing different trade-offs between speed and area. +Under configuration protocol, if the configuration is QL Memory Bank with flatten BL/WL protocol, there might be +optional configuration setting call . +In QL Memory Bank configuration protocol, configuration bits are organized as BitLine (BL) x WordLine (WL) +By default, OpenFPGA will keep BL and WL in square shape if possible where BL might be one bit longer than WL in some cases + For example: + - If the configuration bits of a PB is 9 bits, then BL=3 and WL=3 + - If the configuration bits of a PB is 11 bits, then BL=4 and WL=3 (where there is one extra bit as phantom bit) + - If the configuration bits of a PB is 14 bits, then BL=4 and WL=4 (where there is two extra bits as phantom bits) + +This QL Memory Bank configuration setting allow OpenFPGA to use a fixed WL size, instead of default approach + Template ~~~~~~~~ @@ -14,6 +25,9 @@ Template + + + .. option:: type="scan_chain|memory_bank|standalone|frame_based|ql_memory_bank" @@ -54,6 +68,29 @@ Template .. note:: For ``ql_memory_bank`` configuration protocol when BL/WL protocol ``shift_register`` is selected, different configuration regions **cannot** share any WLs on the same row! In such case, the default fabric key may not work. Strongly recommend to craft your own fabric key based on your configuration region plannning! +.. option:: name="" + + Specify the name of PB type, for example: clb, dsp, bram and etc + +.. option:: num_wl="" + + Fix the size of WL + + For example: + Considered that the configuration bits of a PB is 400 bits. + + If num_wl is not defined, then + - BL will be 20 [=ceiling(square_root(400))] + - WL will be 20 [=ceiling(400/20)] + + If num_wl is defined as 10, then + - WL will be fixed as 10 + - BL will be 40 [=ceiling(400/10)] + + If num_wl is defined as 32, then + - WL will be fixed as 32 + - BL will be 13 [=ceiling(400/32)] + - There will be 16 bits [=(32x13)-400] as phantom bits. Configuration Chain Example ~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/libs/libarchopenfpga/src/config_protocol.cpp b/libs/libarchopenfpga/src/config_protocol.cpp index 00de87a41..d4a40833c 100644 --- a/libs/libarchopenfpga/src/config_protocol.cpp +++ b/libs/libarchopenfpga/src/config_protocol.cpp @@ -116,6 +116,11 @@ CircuitModelId ConfigProtocol::wl_memory_model() const { size_t ConfigProtocol::wl_num_banks() const { return wl_num_banks_; } +const QLMemoryBankConfigSetting* ConfigProtocol::ql_memory_bank_config_setting() + const { + return &ql_memory_bank_config_setting_; +} + /************************************************************************ * Public Mutators ***********************************************************************/ @@ -256,6 +261,10 @@ void ConfigProtocol::set_wl_num_banks(const size_t& num_banks) { wl_num_banks_ = num_banks; } +QLMemoryBankConfigSetting* ConfigProtocol::get_ql_memory_bank_config_setting() { + return &ql_memory_bank_config_setting_; +} + /************************************************************************ * Private Validators ***********************************************************************/ diff --git a/libs/libarchopenfpga/src/config_protocol.h b/libs/libarchopenfpga/src/config_protocol.h index 42ca982c4..7805d3c36 100644 --- a/libs/libarchopenfpga/src/config_protocol.h +++ b/libs/libarchopenfpga/src/config_protocol.h @@ -7,6 +7,7 @@ #include "circuit_library_fwd.h" #include "circuit_types.h" #include "openfpga_port.h" +#include "ql_memory_bank_config_setting.h" /* Data type to define the protocol through which BL/WL can be manipulated */ enum e_blwl_protocol_type { @@ -54,6 +55,9 @@ class ConfigProtocol { CircuitModelId wl_memory_model() const; size_t wl_num_banks() const; + /* QL Memory Bank Config Setting */ + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting() const; + public: /* Public Mutators */ void set_type(const e_config_protocol_type& type); void set_memory_model_name(const std::string& memory_model_name); @@ -76,6 +80,9 @@ class ConfigProtocol { void set_wl_memory_model(const CircuitModelId& memory_model); void set_wl_num_banks(const size_t& num_banks); + /* QL Memory Bank Config Setting */ + QLMemoryBankConfigSetting* get_ql_memory_bank_config_setting(); + public: /* Public validators */ /* Check if internal data has any conflicts to each other. Return number of * errors detected */ @@ -131,6 +138,9 @@ class ConfigProtocol { std::string wl_memory_model_name_; CircuitModelId wl_memory_model_; size_t wl_num_banks_; + + /* QL Memory Bank Config Setting */ + QLMemoryBankConfigSetting ql_memory_bank_config_setting_; }; #endif diff --git a/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp new file mode 100644 index 000000000..87318adc2 --- /dev/null +++ b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.cpp @@ -0,0 +1,34 @@ +#include "ql_memory_bank_config_setting.h" + +#include "openfpga_tokenizer.h" +#include "vtr_assert.h" +#include "vtr_log.h" + +/************************************************************************ + * Member functions for class QLMemoryBankConfigSetting + ***********************************************************************/ + +/************************************************************************ + * Constructors + ***********************************************************************/ +QLMemoryBankConfigSetting::QLMemoryBankConfigSetting() {} + +/************************************************************************ + * Public Accessors + ***********************************************************************/ +QLMemoryBankPBSetting QLMemoryBankConfigSetting::pb_setting( + const std::string& name) const { + if (settings_.find(name) != settings_.end()) { + return settings_.at(name); + } + return QLMemoryBankPBSetting(); +} + +/************************************************************************ + * Public Mutators + ***********************************************************************/ +void QLMemoryBankConfigSetting::add_pb_setting(const std::string& name, + uint32_t num_wl) { + VTR_ASSERT(settings_.find(name) == settings_.end()); + settings_[name] = QLMemoryBankPBSetting(num_wl); +} diff --git a/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h new file mode 100644 index 000000000..593aad73a --- /dev/null +++ b/libs/libarchopenfpga/src/ql_memory_bank_config_setting.h @@ -0,0 +1,29 @@ +#ifndef QL_MEMORY_BANK_CONFIG_SETTING_H +#define QL_MEMORY_BANK_CONFIG_SETTING_H + +#include +#include + +struct QLMemoryBankPBSetting { + QLMemoryBankPBSetting(uint32_t n = 0) : num_wl(n) {} + uint32_t num_wl = 0; +}; + +/******************************************************************** + * A data structure to store QL Memory Bank configuration setting + *******************************************************************/ +class QLMemoryBankConfigSetting { + public: /* Constructors */ + QLMemoryBankConfigSetting(); + + public: /* Public Accessors */ + QLMemoryBankPBSetting pb_setting(const std::string& name) const; + + public: /* Public Mutators */ + void add_pb_setting(const std::string& name, uint32_t num_wl); + + private: /* Internal data */ + std::map settings_; +}; + +#endif diff --git a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp index b51d9f237..d93ff131e 100644 --- a/libs/libarchopenfpga/src/read_xml_config_protocol.cpp +++ b/libs/libarchopenfpga/src/read_xml_config_protocol.cpp @@ -249,6 +249,32 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz, } } +/******************************************************************** + * Parse XML codes about to + *QLMemoryBankConfigSetting + *******************************************************************/ +static void read_xml_ql_memory_bank_config_setting( + QLMemoryBankConfigSetting* setting, pugi::xml_node& Node, + const pugiutil::loc_data& loc_data) { + /* Parse configuration protocol root node */ + pugi::xml_node config_setting = + get_single_child(Node, "ql_memory_bank_config_setting", loc_data, + pugiutil::ReqOpt::OPTIONAL); + + if (config_setting) { + /* Add to ql_memory_bank_config_setting_ */ + for (pugi::xml_node xml_child : config_setting.children()) { + if (xml_child.name() != std::string("pb_type")) { + bad_tag(xml_child, loc_data, config_setting, {"pb_type"}); + } + const std::string& name_attr = + get_attribute(xml_child, "name", loc_data).as_string(); + uint32_t num_wl = get_attribute(xml_child, "num_wl", loc_data).as_uint(); + setting->add_pb_setting(name_attr, num_wl); + } + } +} + /******************************************************************** * Parse XML codes about to an object of ConfigProtocol *******************************************************************/ @@ -264,5 +290,14 @@ ConfigProtocol read_xml_config_protocol(pugi::xml_node& Node, get_single_child(xml_config, "organization", loc_data); read_xml_config_organization(xml_config_orgz, loc_data, config_protocol); + /* Parse QL Memory Bank configuration setting */ + if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK && + config_protocol.bl_protocol_type() == BLWL_PROTOCOL_FLATTEN && + config_protocol.wl_protocol_type() == BLWL_PROTOCOL_FLATTEN) { + read_xml_ql_memory_bank_config_setting( + config_protocol.get_ql_memory_bank_config_setting(), xml_config, + loc_data); + } + return config_protocol; } diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp index 012e3a529..757171c78 100644 --- a/openfpga/src/fabric/build_device_module.cpp +++ b/openfpga/src/fabric/build_device_module.cpp @@ -88,8 +88,9 @@ int build_device_module_graph( module_manager, decoder_lib, vpr_device_ctx, openfpga_ctx.vpr_device_annotation(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), openfpga_ctx.arch().tile_annotations, - openfpga_ctx.arch().config_protocol.type(), sram_model, duplicate_grid_pin, - group_config_block, verbose); + openfpga_ctx.arch().config_protocol.type(), sram_model, + openfpga_ctx.arch().config_protocol.ql_memory_bank_config_setting(), + duplicate_grid_pin, group_config_block, verbose); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_grid_modules.cpp b/openfpga/src/fabric/build_grid_modules.cpp index 4693d81eb..eaa24246b 100644 --- a/openfpga/src/fabric/build_grid_modules.cpp +++ b/openfpga/src/fabric/build_grid_modules.cpp @@ -1166,6 +1166,7 @@ static int build_physical_tile_module( const e_config_protocol_type& sram_orgz_type, const CircuitModelId& sram_model, t_physical_tile_type_ptr phy_block_type, const TileAnnotation& tile_annotation, const e_side& border_side, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, const bool& duplicate_grid_pin, const bool& group_config_block, const bool& verbose) { int status = CMD_EXEC_SUCCESS; @@ -1334,9 +1335,10 @@ static int build_physical_tile_module( module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, config_child_type); if (0 < module_num_config_bits) { - add_pb_sram_ports_to_module_manager(module_manager, grid_module, - circuit_lib, sram_model, sram_orgz_type, - module_num_config_bits); + add_pb_sram_ports_to_module_manager( + module_manager, grid_module, circuit_lib, sram_model, sram_orgz_type, + module_num_config_bits, + ql_memory_bank_config_setting->pb_setting(phy_block_type->name).num_wl); } /* Add module nets to connect memory cells inside @@ -1374,8 +1376,10 @@ int build_grid_modules( const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const TileAnnotation& tile_annotation, const e_config_protocol_type& sram_orgz_type, - const CircuitModelId& sram_model, const bool& duplicate_grid_pin, - const bool& group_config_block, const bool& verbose) { + const CircuitModelId& sram_model, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, + const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& verbose) { /* Start time count */ vtr::ScopedStartFinishTimer timer("Build grid modules"); @@ -1431,7 +1435,8 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, - io_type_side, duplicate_grid_pin, group_config_block, verbose); + io_type_side, ql_memory_bank_config_setting, duplicate_grid_pin, + group_config_block, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -1441,7 +1446,8 @@ int build_grid_modules( status = build_physical_tile_module( module_manager, decoder_lib, device_annotation, circuit_lib, sram_orgz_type, sram_model, &physical_tile, tile_annotation, NUM_SIDES, - duplicate_grid_pin, group_config_block, verbose); + ql_memory_bank_config_setting, duplicate_grid_pin, group_config_block, + verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_grid_modules.h b/openfpga/src/fabric/build_grid_modules.h index 996b9bda2..523b545ea 100644 --- a/openfpga/src/fabric/build_grid_modules.h +++ b/openfpga/src/fabric/build_grid_modules.h @@ -7,6 +7,7 @@ #include "decoder_library.h" #include "module_manager.h" #include "mux_library.h" +#include "ql_memory_bank_config_setting.h" #include "tile_annotation.h" #include "vpr_context.h" #include "vpr_device_annotation.h" @@ -24,8 +25,10 @@ int build_grid_modules( const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, const TileAnnotation& tile_annotation, const e_config_protocol_type& sram_orgz_type, - const CircuitModelId& sram_model, const bool& duplicate_grid_pin, - const bool& group_config_block, const bool& verbose); + const CircuitModelId& sram_model, + const QLMemoryBankConfigSetting* ql_memory_bank_config_setting, + const bool& duplicate_grid_pin, const bool& group_config_block, + const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index a7d137a5e..5dae3f0f4 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -1110,14 +1110,14 @@ static void add_top_module_nets_cmos_memory_bank_config_bus( /* Each memory bank has a unified number of BL/WLs */ size_t num_bls = 0; for (const auto& curr_config_bits : num_config_bits) { - num_bls = - std::max(num_bls, find_memory_decoder_data_size(curr_config_bits.first)); + num_bls = std::max( + num_bls, find_memory_decoder_data_size(curr_config_bits.first, 0, true)); } size_t num_wls = 0; for (const auto& curr_config_bits : num_config_bits) { - num_wls = - std::max(num_wls, find_memory_decoder_data_size(curr_config_bits.first)); + num_wls = std::max( + num_wls, find_memory_decoder_data_size(curr_config_bits.first, 0, false)); } /* Create separated memory bank circuitry, i.e., BL/WL decoders for each diff --git a/openfpga/src/utils/decoder_library_utils.cpp b/openfpga/src/utils/decoder_library_utils.cpp index d3232b7ae..54135a4db 100644 --- a/openfpga/src/utils/decoder_library_utils.cpp +++ b/openfpga/src/utils/decoder_library_utils.cpp @@ -77,7 +77,7 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size) { ***************************************************************************************/ size_t find_memory_decoder_addr_size(const size_t& num_mems) { return find_mux_local_decoder_addr_size( - find_memory_decoder_data_size(num_mems)); + find_memory_decoder_data_size(num_mems, 0, false)); } /*************************************************************************************** @@ -86,8 +86,18 @@ size_t find_memory_decoder_addr_size(const size_t& num_mems) { *lines and word lines, the number of data lines will be a square root of the *number of memory cells. ***************************************************************************************/ -size_t find_memory_decoder_data_size(const size_t& num_mems) { - return (size_t)std::ceil(std::sqrt((float)num_mems)); +size_t find_memory_decoder_data_size(const size_t& num_mems, + const size_t& defined_num_wl, + const bool is_bl) { + if (defined_num_wl == 0) { + return (size_t)std::ceil(std::sqrt((float)num_mems)); + } else { + if (is_bl) { + return find_memory_wl_decoder_data_size(num_mems, defined_num_wl); + } else { + return defined_num_wl; + } + } } /*************************************************************************************** diff --git a/openfpga/src/utils/decoder_library_utils.h b/openfpga/src/utils/decoder_library_utils.h index 51d6da6dd..63aa501a9 100644 --- a/openfpga/src/utils/decoder_library_utils.h +++ b/openfpga/src/utils/decoder_library_utils.h @@ -15,7 +15,9 @@ size_t find_mux_local_decoder_addr_size(const size_t& data_size); size_t find_memory_decoder_addr_size(const size_t& num_mems); -size_t find_memory_decoder_data_size(const size_t& num_mems); +size_t find_memory_decoder_data_size(const size_t& num_mems, + const size_t& defined_num_wl, + const bool is_bl); size_t find_memory_wl_decoder_data_size(const size_t& num_mems, const size_t& num_bls); diff --git a/openfpga/src/utils/memory_utils.cpp b/openfpga/src/utils/memory_utils.cpp index 0abf95b07..9dc799949 100644 --- a/openfpga/src/utils/memory_utils.cpp +++ b/openfpga/src/utils/memory_utils.cpp @@ -436,7 +436,8 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type, * - QL Memory decoders: Apply square root as BL/WLs will be grouped ********************************************************************/ size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, - const size_t& num_config_bits) { + const size_t& num_config_bits, + const size_t& defined_num_wl) { size_t sram_port_size = num_config_bits; switch (sram_orgz_type) { @@ -447,7 +448,8 @@ size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, sram_port_size = 1; break; case CONFIG_MEM_QL_MEMORY_BANK: - sram_port_size = find_memory_decoder_data_size(num_config_bits); + sram_port_size = + find_memory_decoder_data_size(num_config_bits, defined_num_wl, true); break; case CONFIG_MEM_MEMORY_BANK: break; diff --git a/openfpga/src/utils/memory_utils.h b/openfpga/src/utils/memory_utils.h index 184d0be74..a619c07fb 100644 --- a/openfpga/src/utils/memory_utils.h +++ b/openfpga/src/utils/memory_utils.h @@ -42,7 +42,8 @@ size_t generate_sram_port_size(const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits); size_t generate_pb_sram_port_size(const e_config_protocol_type sram_orgz_type, - const size_t& num_config_bits); + const size_t& num_config_bits, + const size_t& defined_num_wl); /** * @brief Compute the number of configurable children to be skipped for a given diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 70a62d148..4a52f46ff 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -419,11 +419,16 @@ void add_sram_ports_to_module_manager( void add_pb_sram_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits) { + const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits, + const uint32_t defined_num_wl) { + if (defined_num_wl) { + // Only support defined_num_wl if the configuration mode is QL Memory Bank + VTR_ASSERT(sram_orgz_type == CONFIG_MEM_QL_MEMORY_BANK); + } std::vector sram_port_names = generate_sram_port_names(circuit_lib, sram_model, sram_orgz_type); size_t sram_port_size = - generate_pb_sram_port_size(sram_orgz_type, num_config_bits); + generate_pb_sram_port_size(sram_orgz_type, num_config_bits, defined_num_wl); /* Add ports to the module manager */ switch (sram_orgz_type) { diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h index f55f73402..0bcb59042 100644 --- a/openfpga/src/utils/module_manager_utils.h +++ b/openfpga/src/utils/module_manager_utils.h @@ -74,7 +74,8 @@ void add_sram_ports_to_module_manager( void add_pb_sram_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, const CircuitLibrary& circuit_lib, const CircuitModelId& sram_model, - const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits); + const e_config_protocol_type sram_orgz_type, const size_t& num_config_bits, + const uint32_t defined_num_wl = 0); void add_primitive_pb_type_ports_to_module_manager( ModuleManager& module_manager, const ModuleId& module_id, diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml new file mode 100644 index 000000000..8fbf05b1f --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml @@ -0,0 +1,206 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index e1512386e..a268b0a6f 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -78,6 +78,7 @@ run-task basic_tests/full_testbench/ql_memory_bank $@ run-task basic_tests/full_testbench/ql_memory_bank_use_wlr $@ run-task basic_tests/full_testbench/multi_region_ql_memory_bank $@ run-task basic_tests/full_testbench/ql_memory_bank_flatten $@ +run-task basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl $@ run-task basic_tests/full_testbench/ql_memory_bank_flatten_use_wlr $@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register $@ run-task basic_tests/full_testbench/ql_memory_bank_shift_register_use_wlr $@ diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf new file mode 100644 index 000000000..8e56d8437 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/ql_memory_bank_flatten_defined_wl/config/task.conf @@ -0,0 +1,45 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_qlbankflatten_defined_wl_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout= +openfpga_fast_configuration= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test=