diff --git a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf
index bf54ec66a..cd23bc3f7 100644
--- a/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/custom_fabric_netlist_location/config/task.conf
@@ -17,12 +17,12 @@ fpga_flow=vpr_blif
 
 [OpenFPGA_SHELL]
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/custom_fabric_netlist_example_script.openfpga
-openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
-openfpga_fabric_netlist_file=./SRC/fabric_netlists.v
+openfpga_fabric_netlist_file=./FABRIC_NETLIST/fabric_netlists.v
 
 [ARCHITECTURES]
-arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_40nm.xml
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
 
 [BENCHMARKS]
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif