From dc09c47411e4ca96fc693d855a0f7f5f51cc71b3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 4 Feb 2021 18:03:56 -0700
Subject: [PATCH] [Arch] Remove packable from architecture files and replace
 with disable_packing

---
 openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml   |  2 +-
 openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml     |  2 +-
 .../k4_N4_tileable_GlobalTile4Clk_40nm.xml         |  2 +-
 .../vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml |  2 +-
 ...tileable_GlobalTileClk_registerable_io_40nm.xml |  2 +-
 .../vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml    |  2 +-
 .../vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml    |  2 +-
 .../vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml    |  2 +-
 .../k4_N4_tileable_full_output_crossbar_40nm.xml   |  2 +-
 .../k4_N4_tileable_no_local_routing_40nm.xml       |  2 +-
 .../k4_N5_tileable_pattern_local_routing_40nm.xml  |  2 +-
 openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml    |  2 +-
 ...frac_N10_tileable_adder_register_chain_40nm.xml |  4 ++--
 ...N10_tileable_adder_register_scan_chain_40nm.xml |  4 ++--
 ...able_adder_register_scan_chain_depop50_40nm.xml |  6 +++---
 ...der_register_scan_chain_depop50_spypad_40nm.xml | 14 +++++++-------
 ...der_register_scan_chain_mem16K_depop50_12nm.xml |  6 +++---
 17 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
index 97ffe88aa..cc7018c45 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileableIO_40nm.xml
@@ -144,7 +144,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
index 90a484880..214e81e9a 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
@@ -144,7 +144,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
index 9317483be..f7b554a9f 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTile4Clk_40nm.xml
@@ -147,7 +147,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
index 9d6f7d31d..507c90158 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_40nm.xml
@@ -146,7 +146,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
index c3c68f421..22e8b5f99 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClk_registerable_io_40nm.xml
@@ -150,7 +150,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
index fdbf7a440..02ea4876f 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzBr_40nm.xml
@@ -149,7 +149,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
index 2a07d020d..61639716b 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTl_40nm.xml
@@ -149,7 +149,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
index b54749174..4d69618a5 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_TileOrgzTr_40nm.xml
@@ -149,7 +149,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
index 00dc13362..69c3ce124 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml
@@ -145,7 +145,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
index b4ebcc711..766632e30 100644
--- a/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml
@@ -148,7 +148,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
index 29c20f59a..1e8c98f19 100644
--- a/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml
@@ -144,7 +144,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
index fcbc20437..f60bf5674 100644
--- a/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_N10_tileable_40nm.xml
@@ -137,7 +137,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
index f98de28e6..66dc465b2 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml
@@ -255,7 +255,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -335,7 +335,7 @@
         <output name="regout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
index 2fb64bf21..4c1b378fd 100644
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml
@@ -271,7 +271,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -355,7 +355,7 @@
         <output name="scout" num_pins="1"/>
         <clock name="clk" num_pins="1"/>
         <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="fabric" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
index 35079cc2d..f19ffe9e9 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
@@ -223,7 +223,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -311,7 +311,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -383,7 +383,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
index e6e3c11ce..88c3f7b76 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_spypad_40nm.xml
@@ -261,7 +261,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -349,7 +349,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -421,7 +421,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
@@ -776,7 +776,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -848,7 +848,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
@@ -1103,7 +1103,7 @@
         <clock name="clk" num_pins="1"/>
 
         <!-- Describe physical mode begins -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -1175,7 +1175,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>
diff --git a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
index 2ee4db855..baada7911 100755
--- a/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
+++ b/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_mem16K_depop50_12nm.xml
@@ -260,7 +260,7 @@
       <!-- A mode denotes the physical implementation of an I/O 
            This mode will be not packable but is mainly used for fabric verilog generation   
         -->
-      <mode name="physical" packable="false">
+      <mode name="physical" disable_packing="true">
         <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
           <input name="outpad" num_pins="1"/>
           <output name="inpad" num_pins="1"/>
@@ -351,7 +351,7 @@
         <!-- Timing annotation is not require for unpackable mode
              It will not be used by timing analyzer
           -->
-        <mode name="physical" packable="false">
+        <mode name="physical" disable_packing="true">
           <pb_type name="frac_logic" num_pb="1">
             <input name="in" num_pins="6"/>
             <input name="cin" num_pins="1"/>
@@ -423,7 +423,7 @@
         </mode>
         <!-- Define physical mode begins -->
         <!-- Define n2_lut5 mode begins -->
-        <mode name="n2_lut5" packable="true">
+        <mode name="n2_lut5" disable_packing="false">
           <pb_type name="lut5inter" num_pb="1">
             <input name="in" num_pins="5"/>
             <input name="cin" num_pins="1"/>