From dbacee8a0aed795d664c9f2712fc380fcda34d0f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 27 Aug 2022 20:25:50 -0700
Subject: [PATCH] [script] turn off equivalent for soft adder architecture as
 we do not expect any routing optimization

---
 .../bitstream_setting_example_script.openfpga |  2 +-
 ...n_chain_nonLR_caravel_io_skywater130nm.xml | 34 +++++++++----------
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
index 8e0c23a53..d0e0d69e2 100644
--- a/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT} --skip_sync_clustering_and_routing_results on
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --circuit_format ${OPENFPGA_VPR_CIRCUIT_FORMAT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index 6ec713ed2..fb7489051 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -142,21 +142,21 @@
           <equivalent_sites>     
              <site pb_type="clb"/>     
           </equivalent_sites>    
-          <input name="I0" num_pins="2" equivalent="full"/>    
+          <input name="I0" num_pins="2" equivalent="none"/>    
           <input name="I0i" num_pins="2" equivalent="none"/>    
-          <input name="I1" num_pins="2" equivalent="full"/>    
+          <input name="I1" num_pins="2" equivalent="none"/>    
           <input name="I1i" num_pins="2" equivalent="none"/>    
-          <input name="I2" num_pins="2" equivalent="full"/>    
+          <input name="I2" num_pins="2" equivalent="none"/>    
           <input name="I2i" num_pins="2" equivalent="none"/>    
-          <input name="I3" num_pins="2" equivalent="full"/>    
+          <input name="I3" num_pins="2" equivalent="none"/>    
           <input name="I3i" num_pins="2" equivalent="none"/>    
-          <input name="I4" num_pins="2" equivalent="full"/>    
+          <input name="I4" num_pins="2" equivalent="none"/>    
           <input name="I4i" num_pins="2" equivalent="none"/>    
-          <input name="I5" num_pins="2" equivalent="full"/>    
+          <input name="I5" num_pins="2" equivalent="none"/>    
           <input name="I5i" num_pins="2" equivalent="none"/>    
-          <input name="I6" num_pins="2" equivalent="full"/>    
+          <input name="I6" num_pins="2" equivalent="none"/>    
           <input name="I6i" num_pins="2" equivalent="none"/>    
-          <input name="I7" num_pins="2" equivalent="full"/>    
+          <input name="I7" num_pins="2" equivalent="none"/>    
           <input name="I7i" num_pins="2" equivalent="none"/>    
           <input name="reg_in" num_pins="1"/>    
           <input name="sc_in" num_pins="1"/>    
@@ -356,21 +356,21 @@
          So pin equivalence should be applied to the first 3 inputs only
 	  -->  
       <pb_type name="clb">   
-         <input name="I0" num_pins="2" equivalent="full"/>   
+         <input name="I0" num_pins="2" equivalent="none"/>   
          <input name="I0i" num_pins="2" equivalent="none"/>   
-         <input name="I1" num_pins="2" equivalent="full"/>   
+         <input name="I1" num_pins="2" equivalent="none"/>   
          <input name="I1i" num_pins="2" equivalent="none"/>   
-         <input name="I2" num_pins="2" equivalent="full"/>   
+         <input name="I2" num_pins="2" equivalent="none"/>   
          <input name="I2i" num_pins="2" equivalent="none"/>   
-         <input name="I3" num_pins="2" equivalent="full"/>   
+         <input name="I3" num_pins="2" equivalent="none"/>   
          <input name="I3i" num_pins="2" equivalent="none"/>   
-         <input name="I4" num_pins="2" equivalent="full"/>   
+         <input name="I4" num_pins="2" equivalent="none"/>   
          <input name="I4i" num_pins="2" equivalent="none"/>   
-         <input name="I5" num_pins="2" equivalent="full"/>   
+         <input name="I5" num_pins="2" equivalent="none"/>   
          <input name="I5i" num_pins="2" equivalent="none"/>   
-         <input name="I6" num_pins="2" equivalent="full"/>   
+         <input name="I6" num_pins="2" equivalent="none"/>   
          <input name="I6i" num_pins="2" equivalent="none"/>   
-         <input name="I7" num_pins="2" equivalent="full"/>   
+         <input name="I7" num_pins="2" equivalent="none"/>   
          <input name="I7i" num_pins="2" equivalent="none"/>   
          <input name="reg_in" num_pins="1"/>   
          <input name="sc_in" num_pins="1"/>   
@@ -821,4 +821,4 @@
       </pb_type>  
       <!-- Define general purpose logic block (CLB) ends -->  
    </complexblocklist> 
-</architecture>
\ No newline at end of file
+</architecture>