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[core] code complete for parsers

This commit is contained in:
tangxifan 2023-04-21 23:45:35 +08:00
parent 6e44f3f5fc
commit dba449f42a
5 changed files with 72 additions and 27 deletions
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10
libs/libarchopenfpga/src/config_protocol_xml_constants.h Normal file
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@ -0,0 +1,10 @@
#ifndef CONFIG_PROTOCOL_XML_CONSTANTS_H
#define CONFIG_PROTOCOL_XML_CONSTANTS_H
/* Constants for XML parsers, including readers and writers */
constexpr const char* XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR = "num_regions";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME = "programming_clock";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR = "port";
constexpr const char* XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR = "ccff_head_indices";
#endif

16
libs/libarchopenfpga/src/read_xml_config_protocol.cpp
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@ -14,7 +14,9 @@
/* Headers from libarchfpga */
#include "arch_error.h"
#include "config_protocol_xml_constants.h"
#include "read_xml_config_protocol.h"
#include "openfpga_port_parser.h"
#include "read_xml_util.h"
/********************************************************************
@ -52,9 +54,15 @@ static void read_xml_ccff_prog_clock(pugi::xml_node& xml_progclk,
const pugiutil::loc_data& loc_data,
ConfigProtocol& config_protocol) {
/* Find the type of configuration protocol */
const char* port_attr =
get_attribute(xml_progclk, "port", loc_data).value();
std::string port_attr =
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR, loc_data).as_string();
std::string indices_attr =
get_attribute(xml_progclk, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR, loc_data).as_string();
BasicPort port = openfpga::PortParser(port_attr).port();
config_protocol.set_prog_clock_port_ccff_head_indices_pair(port, indices_attr);
}
/********************************************************************
@ -154,7 +162,7 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
/* Parse the number of configurable regions
* At least 1 region should be defined, otherwise error out
*/
config_protocol.set_num_regions(get_attribute(xml_config_orgz, "num_regions",
config_protocol.set_num_regions(get_attribute(xml_config_orgz, XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR,
loc_data,
pugiutil::ReqOpt::OPTIONAL)
.as_int(1));
@ -169,7 +177,7 @@ static void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) {
for (pugi::xml_node xml_progclk : xml_config_orgz.children()) {
/* Error out if the XML child has an invalid name! */
if (xml_progclk.name() != std::string("programming_clock")) {
if (xml_progclk.name() != std::string(XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME)) {
bad_tag(xml_progclk, loc_data, xml_config_orgz, {"programming_clock"});
}
read_xml_ccff_prog_clock(xml_progclk, loc_data, config_protocol);

68
libs/libarchopenfpga/src/write_xml_config_protocol.cpp
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@ -12,6 +12,7 @@
#include "vtr_log.h"
/* Headers from readarchopenfpga library */
#include "config_protocol_xml_constants.h"
#include "write_xml_config_protocol.h"
#include "write_xml_utils.h"
@ -31,33 +32,54 @@ static void write_xml_config_organization(std::fstream& fp, const char* fname,
write_xml_attribute(
fp, "circuit_model_name",
circuit_lib.model_name(config_protocol.memory_model()).c_str());
write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_NUM_REGIONS_ATTR,
config_protocol.num_regions());
fp << "/>"
<< "\n";
/* Output BL/WL protocols */
fp << "\t\t\t"
<< "<bl";
write_xml_attribute(
fp, "protocol",
BLWL_PROTOCOL_TYPE_STRING[config_protocol.bl_protocol_type()]);
write_xml_attribute(
fp, "circuit_model_name",
circuit_lib.model_name(config_protocol.bl_memory_model()).c_str());
write_xml_attribute(fp, "num_banks", config_protocol.bl_num_banks());
fp << "/>"
<< "\n";
/* CCFF protocol details */
if (config_protocol.type() == CONFIG_MEM_SCAN_CHAIN) {
for (openfpga::BasicPort port : config_protocol.prog_clock_ports()) {
fp << "\t\t\t"
<< "<" << XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_NODE_NAME;
write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_PORT_ATTR,
port.to_verilog_string().c_str());
write_xml_attribute(
fp, XML_CONFIG_PROTOCOL_CCFF_PROG_CLOCK_INDICES_ATTR,
config_protocol.prog_clock_port_ccff_head_indices(port).c_str());
fp << "/>"
<< "\n";
}
}
fp << "\t\t\t"
<< "<wl";
write_xml_attribute(
fp, "protocol",
BLWL_PROTOCOL_TYPE_STRING[config_protocol.wl_protocol_type()]);
write_xml_attribute(
fp, "circuit_model_name",
circuit_lib.model_name(config_protocol.wl_memory_model()).c_str());
write_xml_attribute(fp, "num_banks", config_protocol.wl_num_banks());
fp << "/>"
<< "\n";
/* BL/WL protocol details */
if (config_protocol.type() == CONFIG_MEM_QL_MEMORY_BANK) {
fp << "\t\t\t"
<< "<bl";
write_xml_attribute(
fp, "protocol",
BLWL_PROTOCOL_TYPE_STRING[config_protocol.bl_protocol_type()]);
write_xml_attribute(
fp, "circuit_model_name",
circuit_lib.model_name(config_protocol.bl_memory_model()).c_str());
write_xml_attribute(fp, "num_banks", config_protocol.bl_num_banks());
fp << "/>"
<< "\n";
fp << "\t\t\t"
<< "<wl";
write_xml_attribute(
fp, "protocol",
BLWL_PROTOCOL_TYPE_STRING[config_protocol.wl_protocol_type()]);
write_xml_attribute(
fp, "circuit_model_name",
circuit_lib.model_name(config_protocol.wl_memory_model()).c_str());
write_xml_attribute(fp, "num_banks", config_protocol.wl_num_banks());
fp << "/>"
<< "\n";
}
fp << "\t"
<< "</organization>"

4
libs/libopenfpgautil/src/openfpga_port.cpp
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@ -106,6 +106,10 @@ bool BasicPort::contained(const BasicPort& portA) const {
/* Set original port width */
size_t BasicPort::get_origin_port_width() const { return origin_port_width_; }
std::string BasicPort::to_verilog_string() const {
return get_name() + "[" + std::to_string(get_lsb()) + ":" + std::to_string(get_msb()) + "]";
}
/************************************************************************
* Overloaded operators
***********************************************************************/

1
libs/libopenfpgautil/src/openfpga_port.h
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@ -35,6 +35,7 @@ class BasicPort {
bool contained(const BasicPort& portA)
const; /* Check if a port is contained by this port */
size_t get_origin_port_width() const;
std::string to_verilog_string() const; /* Generate verilog-style string, e.g., a[0:1] */
public: /* Mutators */
void set(const BasicPort& basic_port); /* copy */