From db71cc8a1624a7c1d58358a48abdb5f3944dcd45 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 23 Feb 2021 16:50:58 -0700
Subject: [PATCH] [Test] Add LUT adder test using quicklogic synthesis script

---
 .../config/bitstream_annotation.xml           |  3 ++
 .../lut_adder_test/config/task.conf           | 39 +++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
 create mode 100644 openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf

diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
new file mode 100644
index 000000000..735d45c23
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
@@ -0,0 +1,3 @@
+<openfpga_bitstream_setting>
+  <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" source="eblif" content=".param LUT"/>
+</openfpga_bitstream_setting>
diff --git a/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
new file mode 100644
index 000000000..1d3f0ff86
--- /dev/null
+++ b/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/task.conf
@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = false
+spice_output=false
+verilog_output=true
+timeout_each_job = 1*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/bitstream_setting_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_bitstream_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/quicklogic_tests/lut_adder_test/config/bitstream_annotation.xml
+openfpga_vpr_circuit_format=eblif
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadderSuperLUT_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/adder_8/adder_8.v
+
+[SYNTHESIS_PARAM]
+##########################
+# Due to the limitation in pack pattern, 8-bit adder benchmark cannot pass VPR
+bench1_top = adder_8
+bench0_yosys=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/quicklogic_yosys_flow_ap3_adder.ys
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=