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Lighten the regression test

This commit is contained in:
Baudouin Chauviere 2019-10-03 13:33:28 -06:00
parent c7e1f7d90b
commit db059af8b8
1 changed files with 0 additions and 15 deletions
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15
openfpga_flow/tasks/blif_vpr_flow/config/task.conf
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@ -63,18 +63,3 @@ vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_COMPACT]
fix_route_chan_width=300
vpr_fpga_verilog_include_icarus_simulator=
vpr_fpga_verilog_formal_verification_top_netlist=
vpr_fpga_verilog_include_timing=
vpr_fpga_verilog_include_signal_init=
vpr_fpga_verilog_print_autocheck_top_testbench=
vpr_fpga_bitstream_generator=
vpr_fpga_verilog_print_user_defined_template=
vpr_fpga_verilog_print_report_timing_tcl=
vpr_fpga_verilog_print_sdc_pnr=
vpr_fpga_verilog_print_sdc_analysis=
#vpr_fpga_x2p_compact_routing_hierarchy=
end_flow_with_test=