refactored routing module generation and verilog writing

vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_api.c

@@ -10,6 +10,7 @@
 #include <assert.h>
 #include <sys/stat.h>
 #include <unistd.h>
+#include <vector>
 
 /* Include vpr structs*/
 #include "util.h"
@@ -34,6 +35,7 @@
 #include "verilog_api.h"
 #include "fpga_bitstream.h"
 
+#include "fpga_x2p_globals.h"
 #include "fpga_x2p_api.h"
 
 /* Top-level API of FPGA-SPICE */
@@ -50,8 +52,27 @@ void vpr_fpga_x2p_tool_suites(t_vpr_setup vpr_setup,
   /* Build multiplexer graphs */
   MuxLibrary mux_lib = build_device_mux_library(num_rr_nodes, rr_node, switch_inf, Arch.spice->circuit_lib, &vpr_setup.RoutingArch);
 
+  /* TODO: Build global routing architecture modules */
+  /* Create a vector of switch infs. TODO: this should be replaced switch objects!!! */
+  std::vector<t_switch_inf> rr_switches;
+  for (short i = 0; i < vpr_setup.RoutingArch.num_switch; ++i) {
+    rr_switches.push_back(switch_inf[i]);
+  }
+
+  /* TODO: This should be done outside this function!!! */
+  vtr::Point<size_t> device_size(nx + 2, ny + 2);
+  std::vector<std::vector<t_grid_tile>> grids;
+  /* Organize a vector (matrix) of grids to feed the top-level module generation */
+  grids.resize(device_size.x());
+  for (size_t ix = 0; ix < device_size.x(); ++ix) {
+    grids[ix].resize(device_size.y());
+    for (size_t iy = 0; iy < device_size.y(); ++iy) {
+      grids[ix][iy] = grid[ix][iy];
+    }
+  } 
+
   /* Build module graphs */
-  ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib);
+  ModuleManager module_manager = build_device_module_graph(vpr_setup, Arch, mux_lib, grids, rr_switches, device_rr_gsb);
 
   /* Xifan TANG: SPICE Modeling, SPICE Netlist Output  */ 
   if (TRUE == vpr_setup.FPGA_SPICE_Opts.SpiceOpts.do_spice) {

vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_types.h

@@ -1,6 +1,7 @@
 #ifndef FPGA_X2P_TYPES_H
 #define FPGA_X2P_TYPES_H
 
+#include "vpr_types.h"
 #include "route_common.h"
 
 /* Define the basic data structures used for FPGA-SPICE */

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.cpp

@@ -2,6 +2,7 @@
  * This file includes the main function to build module graphs
  * for the FPGA fabric
  *******************************************************************/
+#include <vector>
 #include <time.h>
 #include <unistd.h>
 
@@ -17,6 +18,7 @@
 #include "build_wire_modules.h"
 #include "build_memory_modules.h"
 #include "build_grid_modules.h"
+#include "build_routing_modules.h"
 #include "build_module_graph.h"
 
 /********************************************************************
@@ -25,7 +27,10 @@
  *******************************************************************/
 ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
                                         const t_arch& arch,
-                                        const MuxLibrary& mux_lib) {
+                                        const MuxLibrary& mux_lib,
+                                        const std::vector<std::vector<t_grid_tile>>& grids,
+                                        const std::vector<t_switch_inf>& rr_switches,
+                                        const DeviceRRGSB& L_device_rr_gsb) {
   /* Check if the routing architecture we support*/
   if (UNI_DIRECTIONAL != vpr_setup.RoutingArch.directionality) {
     vpr_printf(TIO_MESSAGE_ERROR, 
@@ -104,7 +109,17 @@ ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
   build_grid_modules(module_manager, arch.spice->circuit_lib, mux_lib,  
                      arch.sram_inf.verilog_sram_inf_orgz->type, sram_model);
 
-  /* TODO: Build global routing architecture modules */
+  if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
+    build_unique_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
+                                 arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, grids, 
+                                 vpr_setup.RoutingArch, rr_switches);
+  } else {
+    VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
+    build_flatten_routing_modules(module_manager, L_device_rr_gsb, arch.spice->circuit_lib, 
+                                  arch.sram_inf.verilog_sram_inf_orgz->type, sram_model, grids, 
+                                  vpr_setup.RoutingArch, rr_switches);
+  }
+
 
   /* TODO: Build FPGA fabric top-level module */
 

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph.h

@@ -1,12 +1,17 @@
 #ifndef BUILD_MODULE_GRAPH_H
 #define BUILD_MODULE_GRAPH_H
 
+#include <vector>
 #include "vpr_types.h"
+#include "rr_blocks.h"
 #include "mux_library.h"
 #include "module_manager.h"
 
 ModuleManager build_device_module_graph(const t_vpr_setup& vpr_setup,
                                         const t_arch& arch,
-                                        const MuxLibrary& mux_lib);
+                                        const MuxLibrary& mux_lib,
+                                        const std::vector<std::vector<t_grid_tile>>& grids,
+                                        const std::vector<t_switch_inf>& rr_switches,
+                                        const DeviceRRGSB& L_device_rr_gsb);
 
 #endif

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.cpp

@@ -5,8 +5,33 @@
 #include <vector>
 #include "vtr_assert.h"
 
+#include "fpga_x2p_naming.h" 
+#include "fpga_x2p_pbtypes_utils.h" 
 #include "build_module_graph_utils.h" 
 
+/*********************************************************************
+ * Generate the port name for a Grid
+ * This is a wrapper function for generate_port_name()
+ * which can automatically decode the port name by the pin side and height
+ *********************************************************************/
+std::string generate_grid_side_port_name(const std::vector<std::vector<t_grid_tile>>& grids,
+                                         const vtr::Point<size_t>& coordinate,
+                                         const e_side& side, 
+                                         const size_t& pin_id) {
+  /* Output the pins on the side*/ 
+  size_t height = find_grid_pin_height(grids, coordinate, pin_id);
+  if (1 != grids[coordinate.x()][coordinate.y()].type->pinloc[height][side][pin_id]) {
+    Side side_manager(side);
+    vpr_printf(TIO_MESSAGE_ERROR, 
+               "(File:%s, [LINE%d])Fail to generate a grid pin (x=%lu, y=%lu, height=%lu, side=%s, index=%d)\n",
+               __FILE__, __LINE__, 
+               coordinate.x(), coordinate.y(), height, side_manager.c_str(), pin_id);
+    exit(1);
+  } 
+  return generate_grid_port_name(coordinate, height, side, pin_id, true);
+}
+
+
 /********************************************************************
  * Find input port of a buffer/inverter module
  ********************************************************************/

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_module_graph_utils.h

@@ -4,9 +4,20 @@
 #ifndef BUILD_MODULE_GRAPH_UTILS_H
 #define BUILD_MODULE_GRAPH_UTILS_H
 
+#include <string>
+#include <vector>
+#include "spice_types.h" 
+#include "sides.h" 
+#include "vtr_geometry.h" 
+#include "vpr_types.h" 
 #include "module_manager.h" 
 #include "circuit_library.h" 
 
+std::string generate_grid_side_port_name(const std::vector<std::vector<t_grid_tile>>& grids,
+                                         const vtr::Point<size_t>& coordinate,
+                                         const e_side& side, 
+                                         const size_t& pin_id);
+
 ModulePortId find_inverter_buffer_module_port(const ModuleManager& module_manager, 
                                               const ModuleId& module_id, 
                                               const CircuitLibrary& circuit_lib, 

vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.h

@@ -0,0 +1,33 @@
+/********************************************************************
+ * Header file for build_routing_modules.cpp
+ *******************************************************************/
+#ifndef BUILD_ROUTING_MODULES_H
+#define BUILD_ROUTING_MODULES_H
+
+#include "spice_types.h"
+#include "vpr_types.h"
+#include "rr_blocks.h"
+#include "mux_library.h"
+#include "circuit_library.h"
+#include "module_manager.h"
+
+void build_flatten_routing_modules(ModuleManager& module_manager,
+                                   const DeviceRRGSB& L_device_rr_gsb,
+                                   const CircuitLibrary& circuit_lib,
+                                   const e_sram_orgz& sram_orgz_type,
+                                   const CircuitModelId& sram_model,
+                                   const std::vector<std::vector<t_grid_tile>>& grids,
+                                   const t_det_routing_arch& routing_arch,
+                                   const std::vector<t_switch_inf>& rr_switches); 
+
+void build_unique_routing_modules(ModuleManager& module_manager,
+                                  const DeviceRRGSB& L_device_rr_gsb,
+                                  const CircuitLibrary& circuit_lib,
+                                  const e_sram_orgz& sram_orgz_type,
+                                  const CircuitModelId& sram_model,
+                                  const std::vector<std::vector<t_grid_tile>>& grids,
+                                  const t_det_routing_arch& routing_arch,
+                                  const std::vector<t_switch_inf>& rr_switches); 
+
+
+#endif

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_api.c

@@ -13,6 +13,7 @@
 #include <vector>
 
 /* Include vpr structs*/
+#include "vtr_assert.h"
 #include "vtr_geometry.h"
 #include "util.h"
 #include "physical_types.h"
@@ -280,11 +281,25 @@ void vpr_fpga_verilog(ModuleManager& module_manager,
                           vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
 
   /* Dump routing resources: switch blocks, connection blocks and channel tracks */
-  print_verilog_routing_resources(module_manager, mux_lib, sram_verilog_orgz_info, 
+  print_verilog_routing_resources(module_manager, sram_verilog_orgz_info, 
                                   src_dir_path, rr_dir_path, Arch, vpr_setup.RoutingArch,
                                   num_rr_nodes, rr_node, rr_node_indices, rr_indexed_data,
                                   vpr_setup.FPGA_SPICE_Opts);
 
+  if (TRUE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy) {
+    print_verilog_unique_routing_modules(module_manager, device_rr_gsb,  
+                                         vpr_setup.RoutingArch,
+                                         std::string(src_dir_path), std::string(rr_dir_path),
+                                         TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
+  } else {
+    VTR_ASSERT(FALSE == vpr_setup.FPGA_SPICE_Opts.compact_routing_hierarchy);
+    print_verilog_flatten_routing_modules(module_manager, device_rr_gsb, 
+                                          vpr_setup.RoutingArch,
+                                          std::string(src_dir_path), std::string(rr_dir_path),
+                                          TRUE == vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts.dump_explicit_verilog);
+  }
+
+
   /* Dump logic blocks 
    * Branches to go: 
    * 1. a compact output

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.h

@@ -142,13 +142,7 @@ void dump_verilog_routing_connection_box_subckt(t_sram_orgz_info* cur_sram_orgz_
                                                 boolean compact_routing_hierarchy,
                                                 bool is_explicit_mapping);
 
-
-std::string generate_grid_side_port_name(const vtr::Point<size_t>& coordinate,
-                                         const e_side& side, 
-                                         const size_t& pin_id);
-
 void print_verilog_routing_resources(ModuleManager& module_manager,
-                                     const MuxLibrary& mux_lib,
                                      t_sram_orgz_info* cur_sram_orgz_info,
                                      char* verilog_dir,
                                      char* subckt_dir,
@@ -159,4 +153,18 @@ void print_verilog_routing_resources(ModuleManager& module_manager,
                                      t_rr_indexed_data* LL_rr_indexed_data,
                                      const t_fpga_spice_opts& FPGA_SPICE_Opts);
 
+void print_verilog_flatten_routing_modules(ModuleManager& module_manager,
+                                           const DeviceRRGSB& L_device_rr_gsb,
+                                           const t_det_routing_arch& routing_arch,
+                                           const std::string& verilog_dir,
+                                           const std::string& subckt_dir,
+                                           const bool& use_explicit_port_map);
+
+void print_verilog_unique_routing_modules(ModuleManager& module_manager,
+                                          const DeviceRRGSB& L_device_rr_gsb,
+                                          const t_det_routing_arch& routing_arch,
+                                          const std::string& verilog_dir,
+                                          const std::string& subckt_dir,
+                                          const bool& use_explicit_port_map);
+
 #endif

vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_module.cpp

@@ -19,7 +19,7 @@
 #include "build_top_module_directs.h"
 
 #include "verilog_global.h"
-#include "verilog_routing.h"
+#include "build_module_graph_utils.h"
 #include "verilog_writer_utils.h"
 #include "verilog_module_writer.h"
 #include "verilog_top_module.h"
@@ -401,7 +401,7 @@ void add_top_module_nets_connect_grids_and_sb(ModuleManager& module_manager,
       /* Collect sink-related information */
       vtr::Point<size_t> sink_sb_port_coord(module_sb.get_opin_node(side_manager.get_side(), inode)->xlow,
                                             module_sb.get_opin_node(side_manager.get_side(), inode)->ylow);
-      std::string sink_sb_port_name = generate_grid_side_port_name(sink_sb_port_coord,
+      std::string sink_sb_port_name = generate_grid_side_port_name(grids, sink_sb_port_coord,
                                                                    module_sb.get_opin_node_grid_side(side_manager.get_side(), inode),
                                                                    src_grid_pin_index); 
       ModulePortId sink_sb_port_id = module_manager.find_module_port(sink_sb_module, sink_sb_port_name);
@@ -526,7 +526,7 @@ void add_top_module_nets_connect_grids_and_cb(ModuleManager& module_manager,
       /* Collect source-related information */
       t_rr_node* module_ipin_node = module_cb.get_ipin_node(cb_ipin_side, inode);
       vtr::Point<size_t> cb_src_port_coord(module_ipin_node->xlow, module_ipin_node->ylow);
-      std::string src_cb_port_name = generate_grid_side_port_name(cb_src_port_coord,
+      std::string src_cb_port_name = generate_grid_side_port_name(grids, cb_src_port_coord,
                                                                   module_cb.get_ipin_node_grid_side(cb_ipin_side, inode),
                                                                   module_ipin_node->ptc_num); 
       ModulePortId src_cb_port_id = module_manager.find_module_port(src_cb_module, src_cb_port_name);