diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml
new file mode 100644
index 000000000..abcf209f6
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml
@@ -0,0 +1,7 @@
+<pin_constraints>
+  <!-- For a given .blif file, we want to assign 
+       - the reset signal to the op_reset[0] port of the FPGA fabric
+    -->
+  <set_io pin="op_reset[0]" net="reset"/>
+</pin_constraints>
+
diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf
index 58be5a2bb..07e326a1e 100644
--- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf
+++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/task.conf
@@ -19,6 +19,7 @@ fpga_flow=yosys_vpr
 openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_without_ace_script.openfpga
 openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_fracff_40nm_cc_openfpga.xml
 openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
+openfpga_pin_constraints_file=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks/basic_tests/k4_series/k4n4_fracff/config/pin_constraints.xml
 # Yosys script parameters
 yosys_cell_sim_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_sim.v
 yosys_dff_map_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_yosys_techlib/openfpga_dff_map.v