From da79ef687c53351b4a184f1e7ab02156f05dd9d3 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 15 Feb 2020 20:54:37 -0700
Subject: [PATCH] add missing files

---
 openfpga/src/base/openfpga_verilog.cpp | 38 ++++++++++++++++++++++++++
 openfpga/src/base/openfpga_verilog.h   | 23 ++++++++++++++++
 2 files changed, 61 insertions(+)
 create mode 100644 openfpga/src/base/openfpga_verilog.cpp
 create mode 100644 openfpga/src/base/openfpga_verilog.h

diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp
new file mode 100644
index 000000000..076127f4a
--- /dev/null
+++ b/openfpga/src/base/openfpga_verilog.cpp
@@ -0,0 +1,38 @@
+/********************************************************************
+ * This file includes functions to compress the hierachy of routing architecture
+ *******************************************************************/
+/* Headers from vtrutil library */
+#include "vtr_time.h"
+#include "vtr_log.h"
+
+#include "verilog_api.h"
+#include "openfpga_verilog.h"
+
+/* Include global variables of VPR */
+#include "globals.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * A wrapper function to call the fabric_verilog function of FPGA-Verilog 
+ *******************************************************************/
+void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
+                          const Command& cmd, const CommandContext& cmd_context) {
+
+  CommandOptionId opt_output_dir = cmd.option("file");
+  CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
+  CommandOptionId opt_verbose = cmd.option("verbose");
+  
+  fpga_fabric_verilog(openfpga_ctx.module_graph(),
+                      openfpga_ctx.arch().circuit_lib,
+                      openfpga_ctx.mux_lib(),
+                      g_vpr_ctx.device().grid,
+                      openfpga_ctx.device_rr_gsb(),
+                      cmd_context.option_value(cmd, opt_output_dir),
+                      openfpga_ctx.flow_manager().compress_routing(),
+                      cmd_context.option_enable(cmd, opt_explicit_port_mapping),
+                      cmd_context.option_enable(cmd, opt_verbose));
+} 
+
+} /* end namespace openfpga */
diff --git a/openfpga/src/base/openfpga_verilog.h b/openfpga/src/base/openfpga_verilog.h
new file mode 100644
index 000000000..a62d19411
--- /dev/null
+++ b/openfpga/src/base/openfpga_verilog.h
@@ -0,0 +1,23 @@
+#ifndef OPENFPGA_VERILOG_H
+#define OPENFPGA_VERILOG_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include "command.h"
+#include "command_context.h"
+#include "openfpga_context.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
+                          const Command& cmd, const CommandContext& cmd_context); 
+
+} /* end namespace openfpga */
+
+#endif