From da36b735c6dc9457430f3baf56b2db309d53a837 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 24 Jul 2023 12:13:45 -0700 Subject: [PATCH] [core] syntax --- openfpga/src/annotation/fabric_tile.cpp | 62 +- openfpga/src/annotation/fabric_tile.h | 37 +- openfpga/src/base/openfpga_naming.cpp | 6 +- openfpga/src/base/openfpga_naming.h | 3 +- openfpga/src/fabric/build_tile_modules.cpp | 66 ++- openfpga/src/fabric/build_top_module.cpp | 6 +- openfpga/src/fabric/build_top_module.h | 3 +- .../build_top_module_child_tile_instance.cpp | 537 ++++++++++-------- .../build_top_module_child_tile_instance.h | 8 +- .../src/fabric/build_top_module_memory.cpp | 2 +- openfpga/src/fabric/build_top_module_memory.h | 4 + .../src/fabric/build_top_module_utils.cpp | 11 +- openfpga/src/fabric/build_top_module_utils.h | 7 +- 13 files changed, 439 insertions(+), 313 deletions(-) diff --git a/openfpga/src/annotation/fabric_tile.cpp b/openfpga/src/annotation/fabric_tile.cpp index cfe3985c4..39bac50fc 100644 --- a/openfpga/src/annotation/fabric_tile.cpp +++ b/openfpga/src/annotation/fabric_tile.cpp @@ -78,17 +78,20 @@ FabricTileId FabricTile::find_tile(const vtr::Point& coord) const { return tile_coord2id_lookup_[coord.x()][coord.y()]; } -FabricTileId FabricTile::find_tile_by_pb_coordinate(const vtr::Point& coord) const { +FabricTileId FabricTile::find_tile_by_pb_coordinate( + const vtr::Point& coord) const { if (coord.x() >= pb_coord2id_lookup_.size()) { VTR_LOG_ERROR( - "Programmable block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "Programmable block coordinate [%lu][%lu] exceeds the maximum range " + "[%lu][%lu]!\n", coord.x(), coord.y(), pb_coord2id_lookup_.size(), pb_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); } if (coord.y() >= pb_coord2id_lookup_[coord.x()].size()) { VTR_LOG_ERROR( - "Programmable block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "Programmable block coordinate [%lu][%lu] exceeds the maximum range " + "[%lu][%lu]!\n", coord.x(), coord.y(), pb_coord2id_lookup_.size(), pb_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); @@ -96,19 +99,22 @@ FabricTileId FabricTile::find_tile_by_pb_coordinate(const vtr::Point& co return pb_coord2id_lookup_[coord.x()][coord.y()]; } -FabricTileId FabricTile::find_tile_by_cb_coordinate(const t_rr_type& cb_type, const vtr::Point& coord) const { +FabricTileId FabricTile::find_tile_by_cb_coordinate( + const t_rr_type& cb_type, const vtr::Point& coord) const { switch (cb_type) { case CHANX: { if (coord.x() >= cbx_coord2id_lookup_.size()) { VTR_LOG_ERROR( - "X-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "X-direction connection block coordinate [%lu][%lu] exceeds the " + "maximum range [%lu][%lu]!\n", coord.x(), coord.y(), cbx_coord2id_lookup_.size(), cbx_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); } if (coord.y() >= cbx_coord2id_lookup_[coord.x()].size()) { VTR_LOG_ERROR( - "X-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "X-direction connection block coordinate [%lu][%lu] exceeds the " + "maximum range [%lu][%lu]!\n", coord.x(), coord.y(), cbx_coord2id_lookup_.size(), cbx_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); @@ -118,14 +124,16 @@ FabricTileId FabricTile::find_tile_by_cb_coordinate(const t_rr_type& cb_type, co case CHANY: { if (coord.x() >= cby_coord2id_lookup_.size()) { VTR_LOG_ERROR( - "Y-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "Y-direction connection block coordinate [%lu][%lu] exceeds the " + "maximum range [%lu][%lu]!\n", coord.x(), coord.y(), cby_coord2id_lookup_.size(), cby_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); } if (coord.y() >= cby_coord2id_lookup_[coord.x()].size()) { VTR_LOG_ERROR( - "Y-direction connection block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "Y-direction connection block coordinate [%lu][%lu] exceeds the " + "maximum range [%lu][%lu]!\n", coord.x(), coord.y(), cby_coord2id_lookup_.size(), cby_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); @@ -138,17 +146,20 @@ FabricTileId FabricTile::find_tile_by_cb_coordinate(const t_rr_type& cb_type, co } } -FabricTileId FabricTile::find_tile_by_sb_coordinate(const vtr::Point& coord) const { +FabricTileId FabricTile::find_tile_by_sb_coordinate( + const vtr::Point& coord) const { if (coord.x() >= sb_coord2id_lookup_.size()) { VTR_LOG_ERROR( - "Switch block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "Switch block coordinate [%lu][%lu] exceeds the maximum range " + "[%lu][%lu]!\n", coord.x(), coord.y(), sb_coord2id_lookup_.size(), sb_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); } if (coord.y() >= sb_coord2id_lookup_[coord.x()].size()) { VTR_LOG_ERROR( - "Switch block coordinate [%lu][%lu] exceeds the maximum range [%lu][%lu]!\n", + "Switch block coordinate [%lu][%lu] exceeds the maximum range " + "[%lu][%lu]!\n", coord.x(), coord.y(), sb_coord2id_lookup_.size(), sb_coord2id_lookup_[0].size()); return FabricTileId::INVALID(); @@ -327,7 +338,7 @@ bool FabricTile::register_tile_in_lookup(const FabricTileId& tile_id, } bool FabricTile::register_pb_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord) { + const vtr::Point& coord) { if (coord.x() >= pb_coord2id_lookup_.size()) { VTR_LOG_ERROR( "Fast look-up has not been re-allocated properly! Given x='%lu' exceeds " @@ -344,7 +355,8 @@ bool FabricTile::register_pb_in_lookup(const FabricTileId& tile_id, } /* Throw error if this coord is already registered! */ if (pb_coord2id_lookup_[coord.x()][coord.y()]) { - VTR_LOG_ERROR("Programmable block at [%lu][%lu] has already been registered!\n"); + VTR_LOG_ERROR( + "Programmable block at [%lu][%lu] has already been registered!\n"); return false; } pb_coord2id_lookup_[coord.x()][coord.y()] = tile_id; @@ -353,7 +365,7 @@ bool FabricTile::register_pb_in_lookup(const FabricTileId& tile_id, } bool FabricTile::register_cbx_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord) { + const vtr::Point& coord) { if (coord.x() >= cbx_coord2id_lookup_.size()) { VTR_LOG_ERROR( "Fast look-up has not been re-allocated properly! Given x='%lu' exceeds " @@ -370,7 +382,9 @@ bool FabricTile::register_cbx_in_lookup(const FabricTileId& tile_id, } /* Throw error if this coord is already registered! */ if (cbx_coord2id_lookup_[coord.x()][coord.y()]) { - VTR_LOG_ERROR("X-direction connection block at [%lu][%lu] has already been registered!\n"); + VTR_LOG_ERROR( + "X-direction connection block at [%lu][%lu] has already been " + "registered!\n"); return false; } cbx_coord2id_lookup_[coord.x()][coord.y()] = tile_id; @@ -379,7 +393,7 @@ bool FabricTile::register_cbx_in_lookup(const FabricTileId& tile_id, } bool FabricTile::register_cby_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord) { + const vtr::Point& coord) { if (coord.x() >= cby_coord2id_lookup_.size()) { VTR_LOG_ERROR( "Fast look-up has not been re-allocated properly! Given x='%lu' exceeds " @@ -396,7 +410,9 @@ bool FabricTile::register_cby_in_lookup(const FabricTileId& tile_id, } /* Throw error if this coord is already registered! */ if (cby_coord2id_lookup_[coord.x()][coord.y()]) { - VTR_LOG_ERROR("Y-direction connection block at [%lu][%lu] has already been registered!\n"); + VTR_LOG_ERROR( + "Y-direction connection block at [%lu][%lu] has already been " + "registered!\n"); return false; } cby_coord2id_lookup_[coord.x()][coord.y()] = tile_id; @@ -405,7 +421,7 @@ bool FabricTile::register_cby_in_lookup(const FabricTileId& tile_id, } bool FabricTile::register_sb_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord) { + const vtr::Point& coord) { if (coord.x() >= sb_coord2id_lookup_.size()) { VTR_LOG_ERROR( "Fast look-up has not been re-allocated properly! Given x='%lu' exceeds " @@ -462,8 +478,8 @@ bool FabricTile::set_tile_coordinate(const FabricTileId& tile_id, } int FabricTile::add_pb_coordinate(const FabricTileId& tile_id, - const vtr::Point& coord, - const vtr::Point& gsb_coord) { + const vtr::Point& coord, + const vtr::Point& gsb_coord) { VTR_ASSERT(valid_tile_id(tile_id)); pb_coords_[tile_id].push_back(coord); pb_gsb_coords_[tile_id].push_back(gsb_coord); @@ -472,8 +488,8 @@ int FabricTile::add_pb_coordinate(const FabricTileId& tile_id, } int FabricTile::add_cb_coordinate(const FabricTileId& tile_id, - const t_rr_type& cb_type, - const vtr::Point& coord) { + const t_rr_type& cb_type, + const vtr::Point& coord) { VTR_ASSERT(valid_tile_id(tile_id)); switch (cb_type) { case CHANX: @@ -491,7 +507,7 @@ int FabricTile::add_cb_coordinate(const FabricTileId& tile_id, } int FabricTile::add_sb_coordinate(const FabricTileId& tile_id, - const vtr::Point& coord) { + const vtr::Point& coord) { VTR_ASSERT(valid_tile_id(tile_id)); sb_coords_[tile_id].push_back(coord); /* Register in fast look-up */ diff --git a/openfpga/src/annotation/fabric_tile.h b/openfpga/src/annotation/fabric_tile.h index dee4a783a..7f2091637 100644 --- a/openfpga/src/annotation/fabric_tile.h +++ b/openfpga/src/annotation/fabric_tile.h @@ -36,12 +36,18 @@ class FabricTile { FabricTileId unique_tile(const vtr::Point& coord) const; /** @brief Find the tile info with a given coordinate */ FabricTileId find_tile(const vtr::Point& coord) const; - /** @brief Find the id of a tile, with a given coordinate of the programmable block under the tile */ - FabricTileId find_tile_by_pb_coordinate(const vtr::Point& coord) const; - /** @brief Find the id of a tile, with a given coordinate of the connection block under the tile */ - FabricTileId find_tile_by_cb_coordinate(const t_rr_type& cb_type, const vtr::Point& coord) const; - /** @brief Find the id of a tile, with a given coordinate of the switch block under the tile */ - FabricTileId find_tile_by_sb_coordinate(const vtr::Point& coord) const; + /** @brief Find the id of a tile, with a given coordinate of the programmable + * block under the tile */ + FabricTileId find_tile_by_pb_coordinate( + const vtr::Point& coord) const; + /** @brief Find the id of a tile, with a given coordinate of the connection + * block under the tile */ + FabricTileId find_tile_by_cb_coordinate( + const t_rr_type& cb_type, const vtr::Point& coord) const; + /** @brief Find the id of a tile, with a given coordinate of the switch block + * under the tile */ + FabricTileId find_tile_by_sb_coordinate( + const vtr::Point& coord) const; /** @brief Find the coordinate of the unique tile w.r.t the tile with a tile * id */ vtr::Point unique_tile_coordinate(const FabricTileId& tile_id) const; @@ -82,12 +88,12 @@ class FabricTile { bool set_tile_coordinate(const FabricTileId& tile_id, const vtr::Point& coord); int add_pb_coordinate(const FabricTileId& tile_id, - const vtr::Point& coord, - const vtr::Point& gsb_coord); + const vtr::Point& coord, + const vtr::Point& gsb_coord); int add_cb_coordinate(const FabricTileId& tile_id, const t_rr_type& cb_type, - const vtr::Point& coord); + const vtr::Point& coord); int add_sb_coordinate(const FabricTileId& tile_id, - const vtr::Point& coord); + const vtr::Point& coord); /** @brief Build a list of unique tiles by comparing the coordinates in * DeviceRRGSB */ void build_unique_tiles(); @@ -118,13 +124,13 @@ class FabricTile { bool register_tile_in_lookup(const FabricTileId& tile_id, const vtr::Point& coord); bool register_pb_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord); + const vtr::Point& coord); bool register_cbx_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord); + const vtr::Point& coord); bool register_cby_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord); + const vtr::Point& coord); bool register_sb_in_lookup(const FabricTileId& tile_id, - const vtr::Point& coord); + const vtr::Point& coord); private: /* Internal Data */ vtr::vector ids_; @@ -142,7 +148,8 @@ class FabricTile { vtr::vector>> cbx_coords_; vtr::vector>> cby_coords_; vtr::vector>> sb_coords_; - /* A few fast lookup to spot tile by coordinate of programmable blocks, connection blocks and switch blocks */ + /* A few fast lookup to spot tile by coordinate of programmable blocks, + * connection blocks and switch blocks */ std::vector> pb_coord2id_lookup_; std::vector> cbx_coord2id_lookup_; std::vector> cby_coord2id_lookup_; diff --git a/openfpga/src/base/openfpga_naming.cpp b/openfpga/src/base/openfpga_naming.cpp index 2551585d2..7153b5b65 100644 --- a/openfpga/src/base/openfpga_naming.cpp +++ b/openfpga/src/base/openfpga_naming.cpp @@ -506,9 +506,11 @@ std::string generate_tile_module_name(const vtr::Point& tile_coord) { } /********************************************************************* - * Generate the port name for a tile. Note that use the index to make the tile port name unique! + * Generate the port name for a tile. Note that use the index to make the tile + *port name unique! *********************************************************************/ -std::string generate_tile_module_port_name(const std::string& prefix, const std::string& port_name) { +std::string generate_tile_module_port_name(const std::string& prefix, + const std::string& port_name) { return prefix + port_name; } diff --git a/openfpga/src/base/openfpga_naming.h b/openfpga/src/base/openfpga_naming.h index 8efe39a68..389e4c951 100644 --- a/openfpga/src/base/openfpga_naming.h +++ b/openfpga/src/base/openfpga_naming.h @@ -112,7 +112,8 @@ std::string generate_connection_block_module_name( std::string generate_tile_module_name(const vtr::Point& tile_coord); -std::string generate_tile_module_port_name(const vtr::Point& tile_coord, const std::string& port_name); +std::string generate_tile_module_port_name(const std::string& prefix, + const std::string& port_name); std::string generate_tile_module_netlist_name(const std::string& block_name, const std::string& postfix); diff --git a/openfpga/src/fabric/build_tile_modules.cpp b/openfpga/src/fabric/build_tile_modules.cpp index 78b2fff75..d979e29c9 100644 --- a/openfpga/src/fabric/build_tile_modules.cpp +++ b/openfpga/src/fabric/build_tile_modules.cpp @@ -64,9 +64,9 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const std::vector& pb_instances, - const std::vector& sb_instances, - const size_t& isb, const bool& compact_routing_hierarchy, - const bool& frame_view, const bool& verbose) { + const std::vector& sb_instances, const size_t& isb, + const bool& compact_routing_hierarchy, const bool& frame_view, + const bool& verbose) { /* Skip those Switch blocks that do not exist */ if (false == rr_gsb.is_sb_exist()) { return CMD_EXEC_SUCCESS; @@ -199,7 +199,10 @@ static int build_tile_module_port_and_nets_between_sb_and_pb( } else { /* Create a port on the tile module and create the net if required. * Create a proper name to avoid naming conflicts */ - src_grid_port.set_name(generate_tile_module_port_name(fabric_tile.sb_coordinates(fabric_tile_id, isb), src_grid_port.get_name())); + src_grid_port.set_name(generate_tile_module_port_name( + generate_switch_block_module_name( + fabric_tile.sb_coordinates(fabric_tile_id)[isb]), + src_grid_port.get_name())); ModulePortId src_tile_port_id = module_manager.add_port( tile_module, src_grid_port, ModuleManager::e_module_port_type::MODULE_INPUT_PORT); @@ -289,10 +292,9 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const t_rr_type& cb_type, const std::vector& pb_instances, - const std::vector& cb_instances, - const size_t& icb, - const bool& compact_routing_hierarchy, const bool& frame_view, - const bool& verbose) { + const std::map>& cb_instances, + const size_t& icb, const bool& compact_routing_hierarchy, + const bool& frame_view, const bool& verbose) { size_t cb_instance = cb_instances.at(cb_type)[icb]; /* We could have two different coordinators, one is the instance, the other is * the module */ @@ -420,7 +422,13 @@ static int build_tile_module_port_and_nets_between_cb_and_pb( } else { /* Create a port on the tile module and create the net if required. * FIXME: Create a proper name to avoid naming conflicts */ - src_cb_port.set_name(generate_tile_module_port_name(fabric_tile.cb_coordinates(fabric_tile_id, cb_type, icb), src_cb_port.get_name())); + const RRGSB& cb_inst_rr_gsb = device_rr_gsb.get_gsb( + fabric_tile.cb_coordinates(fabric_tile_id, cb_type)[icb]); + std::string cb_instance_name_in_tile = + generate_connection_block_module_name( + cb_type, cb_inst_rr_gsb.get_cb_coordinate(cb_type)); + src_cb_port.set_name(generate_tile_module_port_name( + cb_instance_name_in_tile, src_cb_port.get_name())); ModulePortId sink_tile_port_id = module_manager.add_port( tile_module, src_cb_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); @@ -493,10 +501,9 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& fabric_tile_id, const std::map>& cb_instances, - const std::vector& sb_instances, - const size_t& isb, - const bool& compact_routing_hierarchy, - const bool& frame_view, const bool& verbose) { + const std::vector& sb_instances, const size_t& isb, + const bool& compact_routing_hierarchy, const bool& frame_view, + const bool& verbose) { size_t sb_instance = sb_instances[isb]; /* We could have two different coordinators, one is the instance, the other is * the module */ @@ -674,7 +681,10 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( module_manager.find_module_port(sb_module_id, chan_input_port_name); BasicPort chan_input_port = module_manager.module_port(sb_module_id, sb_chan_input_port_id); - chan_input_port.set_name(generate_tile_module_port_name(fabric_tile.sb_coordinates(fabric_tile_id, isb), chan_input_port.get_name())); + chan_input_port.set_name(generate_tile_module_port_name( + generate_switch_block_module_name( + fabric_tile.sb_coordinates(fabric_tile_id)[isb]), + chan_input_port.get_name())); ModulePortId tile_chan_input_port_id = module_manager.add_port( tile_module, chan_input_port, ModuleManager::e_module_port_type::MODULE_INPUT_PORT); @@ -704,7 +714,10 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( module_manager.find_module_port(sb_module_id, chan_output_port_name); BasicPort chan_output_port = module_manager.module_port(sb_module_id, sb_chan_output_port_id); - chan_output_port.set_name(generate_tile_module_port_name(fabric_tile.sb_coordinates(fabric_tile_id, isb), chan_output_port.get_name())); + chan_output_port.set_name(generate_tile_module_port_name( + generate_switch_block_module_name( + fabric_tile.sb_coordinates(fabric_tile_id)[isb]), + chan_output_port.get_name())); ModulePortId tile_chan_output_port_id = module_manager.add_port( tile_module, chan_output_port, ModuleManager::e_module_port_type::MODULE_OUTPUT_PORT); @@ -741,7 +754,9 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( *block is the only submodule under the tile. Also, it could happen that the *programmable block drives or is driven by other blocks from another tile. As a *result, we should build the nets for these unconnected pins - * Note that direct connections, e.g., carry chain is not handled at tile-level. It will be handled in the top-level module, which should not case a negative impact on the physical design. + * Note that direct connections, e.g., carry chain is not handled at tile-level. + *It will be handled in the top-level module, which should not case a negative + *impact on the physical design. * * +------------+ * | |-->grid_xxx @@ -753,10 +768,9 @@ static int build_tile_module_port_and_nets_between_sb_and_cb( static int build_tile_port_and_nets_from_pb( ModuleManager& module_manager, const ModuleId& tile_module, const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, - const vtr::Point& pb_coord, - const std::vector& pb_instances, - const size_t& ipb, - const bool& frame_view, const bool& verbose) { + const vtr::Point& pb_coord, const std::vector& pb_instances, + const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, + const size_t& ipb, const bool& frame_view, const bool& verbose) { size_t pb_instance = pb_instances[ipb]; t_physical_tile_type_ptr phy_tile = grids.get_physical_type(pb_coord.x(), pb_coord.y()); @@ -828,7 +842,12 @@ static int build_tile_port_and_nets_from_pb( return CMD_EXEC_FATAL_ERROR; } /* Create a proper name to avoid naming conflicts */ - pb_port.set_name(generate_tile_module_port_name(fabric_tile.pb_coordinates(fabric_tile_id, ipb), pb_port.get_name())); + std::string pb_instance_name_in_tile = + generate_grid_block_module_name_in_top_module( + std::string(GRID_MODULE_NAME_PREFIX), grids, + fabric_tile.pb_coordinates(curr_fabric_tile_id)[ipb]); + pb_port.set_name(generate_tile_module_port_name( + pb_instance_name_in_tile, pb_port.get_name())); /* Find the port from the pb module and see if it is already been * driven or driving a net. if not, create a new port at the tile @@ -956,8 +975,7 @@ static int build_tile_module_ports_and_nets( status_code = build_tile_module_port_and_nets_between_cb_and_pb( module_manager, tile_module, grids, vpr_device_annotation, device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, fabric_tile_id, - cb_type, pb_instances, cb_instances, icb, true, frame_view, - verbose); + cb_type, pb_instances, cb_instances, icb, true, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -986,7 +1004,7 @@ static int build_tile_module_ports_and_nets( fabric_tile.pb_coordinates(fabric_tile_id)[ipb]; status_code = build_tile_port_and_nets_from_pb( module_manager, tile_module, grids, vpr_device_annotation, pb_coord, - pb_instances, ipb, frame_view, verbose); + pb_instances, fabric_tile, fabric_tile_id, ipb, frame_view, verbose); if (status_code != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } diff --git a/openfpga/src/fabric/build_top_module.cpp b/openfpga/src/fabric/build_top_module.cpp index 898159431..cb98ed8dd 100644 --- a/openfpga/src/fabric/build_top_module.cpp +++ b/openfpga/src/fabric/build_top_module.cpp @@ -79,8 +79,10 @@ int build_top_module( } else { /* TODO: Build the tile instances under the top module */ status = build_top_module_tile_child_instances( - module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk, rr_clock_lookup, vpr_device_annotation, grids, tile_annotation, rr_graph, device_rr_gsb, tile_direct, arch_direct, - fabric_tile, config_protocol, sram_model, fabric_key, frame_view, verbose); + module_manager, top_module, blwl_sr_banks, circuit_lib, clk_ntwk, + rr_clock_lookup, vpr_device_annotation, grids, tile_annotation, rr_graph, + device_rr_gsb, tile_direct, arch_direct, fabric_tile, config_protocol, + sram_model, fabric_key, frame_view, verbose); } if (status != CMD_EXEC_SUCCESS) { diff --git a/openfpga/src/fabric/build_top_module.h b/openfpga/src/fabric/build_top_module.h index 7ee641072..46fe36219 100644 --- a/openfpga/src/fabric/build_top_module.h +++ b/openfpga/src/fabric/build_top_module.h @@ -44,8 +44,7 @@ int build_top_module( const CircuitModelId& sram_model, const FabricTile& fabric_tile, const bool& frame_view, const bool& compact_routing_hierarchy, const bool& duplicate_grid_pin, const FabricKey& fabric_key, - const bool& generate_random_fabric_key, - const bool& verbose); + const bool& generate_random_fabric_key, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp index 119ed3e34..103cf0148 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.cpp +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.cpp @@ -15,6 +15,7 @@ /* Headers from openfpgashell library */ #include "build_module_graph_utils.h" +#include "build_routing_module_utils.h" #include "build_top_module_child_tile_instance.h" #include "build_top_module_connection.h" #include "build_top_module_directs.h" @@ -26,7 +27,9 @@ #include "module_manager_utils.h" #include "openfpga_device_grid_utils.h" #include "openfpga_naming.h" +#include "openfpga_physical_tile_utils.h" #include "openfpga_reserved_words.h" +#include "openfpga_rr_graph_utils.h" #include "rr_gsb_utils.h" /* begin namespace openfpga */ @@ -249,7 +252,8 @@ static void add_top_module_tile_io_children( } /******************************************************************** - * Add module nets to connect a switch block in a given tile to the programmable block in adjacent tiles + * Add module nets to connect a switch block in a given tile to the programmable + *block in adjacent tiles * * TileA | TileB * +------------+ | +------------+ @@ -279,23 +283,24 @@ static void add_top_module_tile_io_children( static int build_top_module_tile_nets_between_sb_and_pb( ModuleManager& module_manager, const ModuleId& top_module, const ModuleId& curr_tile_module, - const vtr::Matrix& tile_instance_ids, - const size_t& curr_tile_instance_id, - const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const vtr::Matrix& tile_instance_ids, + const size_t& curr_tile_instance_id, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& sb_idx_in_curr_fabric_tile, - const bool& compact_routing_hierarchy, - const bool& verbose) { + const bool& compact_routing_hierarchy, const bool& verbose) { /* Skip those Switch blocks that do not exist */ if (false == rr_gsb.is_sb_exist()) { return CMD_EXEC_SUCCESS; } - vtr::Point sink_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); - FabricTileId sink_unique_tile = fabric_tile.unique_tile(curr_fabric_tile_id); - vtr::Point sink_sb_coord_in_unique_tile = fabric_tile.sb_coordinates(src_unique_tile)[sb_idx_in_curr_fabric_tile]; + vtr::Point sink_tile_coord = + fabric_tile.tile_coordinate(curr_fabric_tile_id); + FabricTileId sink_unique_tile = fabric_tile.unique_tile(sink_tile_coord); + vtr::Point sink_sb_coord_in_unique_tile = + fabric_tile.sb_coordinates(sink_unique_tile)[sb_idx_in_curr_fabric_tile]; std::string sink_sb_instance_name_in_unique_tile = generate_switch_block_module_name(sink_sb_coord_in_unique_tile); @@ -336,12 +341,13 @@ static int build_top_module_tile_nets_between_sb_and_pb( continue; } - /* Find the source tile id, coordinate etc., which is required to find source tile module and port - * Relationship between source tile and its unique module - * Take an example: + /* Find the source tile id, coordinate etc., which is required to find + * source tile module and port Relationship between source tile and its + * unique module Take an example: * - * grid_pin name should follow unique module [i0][j0] of src_tile[x0][y0] - * sb_pin name should follow unique module [i1][j1] of des_tile[x1][y1] + * grid_pin name should follow unique module [i0][j0] of + * src_tile[x0][y0] sb_pin name should follow unique module [i1][j1] of + * des_tile[x1][y1] * * However, instance id should follow the origin tiles * @@ -362,12 +368,17 @@ static int build_top_module_tile_nets_between_sb_and_pb( * +------------+ +--------------+ * */ - FabricTileId src_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); - size_t pb_idx_in_src_fabric_tile = fabric_tile.find_pb_index_in_tile(src_fabric_tile_id, grid_coordinate); - vtr::Point src_tile_coord = fabric_tile.tile_coordinate(src_fabric_tile_id); - vtr::Point src_unique_tile_coord = fabric_tile.unique_tile_coordinate(src_fabric_tile_id); + FabricTileId src_fabric_tile_id = + fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); + size_t pb_idx_in_src_fabric_tile = + fabric_tile.find_pb_index_in_tile(src_fabric_tile_id, grid_coordinate); + vtr::Point src_tile_coord = + fabric_tile.tile_coordinate(src_fabric_tile_id); + vtr::Point src_unique_tile_coord = + fabric_tile.unique_tile_coordinate(src_fabric_tile_id); FabricTileId src_unique_tile = fabric_tile.unique_tile(src_tile_coord); - vtr::Point src_pb_coord_in_unique_tile = fabric_tile.pb_coordinates(src_unique_tile)[pb_idx_in_src_fabric_tile]; + vtr::Point src_pb_coord_in_unique_tile = + fabric_tile.pb_coordinates(src_unique_tile)[pb_idx_in_src_fabric_tile]; std::string src_tile_module_name = generate_tile_module_name(src_unique_tile_coord); ModuleId src_tile_module = @@ -378,16 +389,21 @@ static int build_top_module_tile_nets_between_sb_and_pb( size_t src_grid_pin_index = rr_graph.node_pin_num( rr_gsb.get_opin_node(side_manager.get_side(), inode)); - std::string src_grid_port_name = generate_grid_module_port_name_in_top_module( - grid_coordinate, src_grid_pin_index, vpr_device_annotation, + std::string src_grid_port_name = + generate_grid_module_port_name_in_top_module( + grids, grid_coordinate, src_grid_pin_index, vpr_device_annotation, rr_graph, rr_gsb.get_opin_node(side_manager.get_side(), inode)); - std::string src_grid_module_name = generate_grid_block_module_name_in_top_module(std::string(GRID_MODULE_NAME_PREFIX), grids, src_pb_coord_in_unique_tile); - std::string src_tile_grid_port_name = generate_tile_module_port_name(src_grid_module_name, src_grid_port_name); - ModulePortId src_tile_grid_port_id = - module_manager.find_module_port(src_tile_module, src_tile_grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(src_tile_module, - src_tile_grid_port_id)); + std::string src_grid_module_name = + generate_grid_block_module_name_in_top_module( + std::string(GRID_MODULE_NAME_PREFIX), grids, + src_pb_coord_in_unique_tile); + std::string src_tile_grid_port_name = generate_tile_module_port_name( + src_grid_module_name, src_grid_port_name); + ModulePortId src_tile_grid_port_id = module_manager.find_module_port( + src_tile_module, src_tile_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + src_tile_module, src_tile_grid_port_id)); BasicPort src_tile_grid_port = module_manager.module_port(src_tile_module, src_tile_grid_port_id); @@ -404,24 +420,26 @@ static int build_top_module_tile_nets_between_sb_and_pb( grids, vpr_device_annotation, rr_graph, module_sb.get_opin_node(side_manager.get_side(), inode)); - std::string sink_tile_sb_port_name = generate_tile_module_port_name(sink_sb_instance_name_in_unique_tile, sink_sb_port_name); - ModulePortId sink_tile_sb_port_id = - module_manager.find_module_port(tile_module, sink_tile_sb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(tile_module, - sink_tile_sb_port_id)); + std::string sink_tile_sb_port_name = generate_tile_module_port_name( + sink_sb_instance_name_in_unique_tile, sink_sb_port_name); + ModulePortId sink_tile_sb_port_id = module_manager.find_module_port( + curr_tile_module, sink_tile_sb_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + curr_tile_module, sink_tile_sb_port_id)); BasicPort sink_tile_sb_port = - module_manager.module_port(tile_module, sink_tile_sb_port_id); + module_manager.module_port(curr_tile_module, sink_tile_sb_port_id); /* Create nets */ - VTR_LOGV(verbose, - "Build inter-tile nets between switch block '%s' in tile[%lu][%lu] and " - "programmable block in tile[%lu][%lu]\n", - sink_sb_instance_name_in_unique_tile.c_str(), - sink_tile_coord.x(), sink_tile_coord.y(), - src_tile_coord.x(), src_tile_coord.y()); + VTR_LOGV( + verbose, + "Build inter-tile nets between switch block '%s' in tile[%lu][%lu] and " + "programmable block in tile[%lu][%lu]\n", + sink_sb_instance_name_in_unique_tile.c_str(), sink_tile_coord.x(), + sink_tile_coord.y(), src_tile_coord.x(), src_tile_coord.y()); /* Source and sink port should match in size */ - VTR_ASSERT(src_tile_grid_port.get_width() == sink_tile_sb_port.get_width()); + VTR_ASSERT(src_tile_grid_port.get_width() == + sink_tile_sb_port.get_width()); /* Create a net for each pin */ for (size_t pin_id = 0; pin_id < src_tile_grid_port.pins().size(); @@ -498,21 +516,24 @@ static int build_top_module_tile_nets_between_sb_and_pb( *******************************************************************/ static int build_top_module_tile_nets_between_cb_and_pb( ModuleManager& module_manager, const ModuleId& top_module, - const ModuleId& tile_module, - const vtr::Matrix& tile_instance_ids, - const size_t& tile_instance_id, - const DeviceGrid& grids, const VprDeviceAnnotation& vpr_device_annotation, + const ModuleId& tile_module, const vtr::Matrix& tile_instance_ids, + const size_t& tile_instance_id, const DeviceGrid& grids, + const VprDeviceAnnotation& vpr_device_annotation, const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, const RRGSB& rr_gsb, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const t_rr_type& cb_type, const size_t& cb_idx_in_curr_fabric_tile, - const bool& compact_routing_hierarchy, - const bool& verbose) { - vtr::Point src_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); - FabricTileId src_unique_tile = fabric_tile.unique_tile(curr_fabric_tile_id); - vtr::Point src_cb_coord_in_unique_tile = fabric_tile.cb_coordinates(src_unique_tile, cb_type)[cb_idx_in_curr_fabric_tile]; + const bool& compact_routing_hierarchy, const bool& verbose) { + vtr::Point src_tile_coord = + fabric_tile.tile_coordinate(curr_fabric_tile_id); + FabricTileId src_unique_tile = fabric_tile.unique_tile(src_tile_coord); + vtr::Point src_cb_coord_in_unique_tile = fabric_tile.cb_coordinates( + src_unique_tile, cb_type)[cb_idx_in_curr_fabric_tile]; + const RRGSB& src_cb_inst_rr_gsb = + device_rr_gsb.get_gsb(src_cb_coord_in_unique_tile); std::string src_cb_instance_name_in_unique_tile = - generate_connection_block_module_name(cb_type, sink_sb_coord_in_unique_tile); + generate_connection_block_module_name( + cb_type, src_cb_inst_rr_gsb.get_cb_coordinate(cb_type)); /* We could have two different coordinators, one is the instance, the other is * the module */ @@ -558,7 +579,8 @@ static int build_top_module_tile_nets_between_cb_and_pb( rr_graph.node_ylow(module_ipin_node)); std::string src_cb_port_name = generate_cb_module_grid_port_name( cb_ipin_side, grids, vpr_device_annotation, rr_graph, module_ipin_node); - std::string src_tile_cb_port_name = generate_tile_module_port_name(src_cb_instance_name_in_unique_tile, src_cb_port_name); + std::string src_tile_cb_port_name = generate_tile_module_port_name( + src_cb_instance_name_in_unique_tile, src_cb_port_name); ModulePortId src_cb_port_id = module_manager.find_module_port(tile_module, src_cb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(tile_module, @@ -579,30 +601,40 @@ static int build_top_module_tile_nets_between_cb_and_pb( continue; } - FabricTileId sink_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); - size_t pb_idx_in_sink_fabric_tile = fabric_tile.find_pb_index_in_tile(sink_fabric_tile_id, grid_coordinate); - vtr::Point sink_tile_coord = fabric_tile.tile_coordinate(sink_fabric_tile_id); - vtr::Point sink_unique_tile_coord = fabric_tile.unique_tile_coordinate(sink_fabric_tile_id); + FabricTileId sink_fabric_tile_id = + fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); + size_t pb_idx_in_sink_fabric_tile = + fabric_tile.find_pb_index_in_tile(sink_fabric_tile_id, grid_coordinate); + vtr::Point sink_tile_coord = + fabric_tile.tile_coordinate(sink_fabric_tile_id); + vtr::Point sink_unique_tile_coord = + fabric_tile.unique_tile_coordinate(sink_fabric_tile_id); FabricTileId sink_unique_tile = fabric_tile.unique_tile(sink_tile_coord); - vtr::Point sink_pb_coord_in_unique_tile = fabric_tile.pb_coordinates(sink_unique_tile)[pb_idx_in_sink_fabric_tile]; + vtr::Point sink_pb_coord_in_unique_tile = + fabric_tile.pb_coordinates( + sink_unique_tile)[pb_idx_in_sink_fabric_tile]; std::string sink_tile_module_name = generate_tile_module_name(sink_unique_tile_coord); ModuleId sink_tile_module = module_manager.find_module(sink_tile_module_name); VTR_ASSERT(true == module_manager.valid_module_id(sink_tile_module)); - size_t sink_tile_instance_id = tile_instance_ids[sink_tile_coord.x()][sink_tile_coord.y()]; + size_t sink_tile_instance_id = + tile_instance_ids[sink_tile_coord.x()][sink_tile_coord.y()]; std::string sink_grid_module_name = generate_grid_block_module_name_in_top_module( - std::string(GRID_MODULE_NAME_PREFIX), grids, sink_pb_coord_in_unique_tile); + std::string(GRID_MODULE_NAME_PREFIX), grids, + sink_pb_coord_in_unique_tile); size_t sink_grid_pin_index = rr_graph.node_pin_num(instance_ipin_node); - std::string sink_grid_port_name = generate_grid_module_port_name_in_top_module( - grid_coordinate, sink_grid_pin_index, vpr_device_annotation, + std::string sink_grid_port_name = + generate_grid_module_port_name_in_top_module( + grids, grid_coordinate, sink_grid_pin_index, vpr_device_annotation, rr_graph, rr_gsb.get_ipin_node(cb_ipin_side, inode)); - std::string sink_tile_grid_port_name = generate_tile_module_port_name(sink_grid_module_name, sink_grid_port_name); + std::string sink_tile_grid_port_name = generate_tile_module_port_name( + sink_grid_module_name, sink_grid_port_name); ModulePortId sink_grid_port_id = module_manager.find_module_port(sink_tile_module, sink_grid_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id( @@ -615,8 +647,7 @@ static int build_top_module_tile_nets_between_cb_and_pb( VTR_ASSERT(src_cb_port.get_width() == sink_grid_port.get_width()); /* Create a net for each pin */ - for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); - ++pin_id) { + for (size_t pin_id = 0; pin_id < src_cb_port.pins().size(); ++pin_id) { ModuleNetId net = create_module_source_pin_net( module_manager, top_module, tile_module, tile_instance_id, src_cb_port_id, src_cb_port.pins()[pin_id]); @@ -673,24 +704,23 @@ static int build_top_module_tile_nets_between_cb_and_pb( *******************************************************************/ static int build_top_module_tile_nets_between_sb_and_cb( ModuleManager& module_manager, const ModuleId& top_module, - const ModuleId& tile_module, - const vtr::Matrix& tile_instance_ids, - const size_t& tile_instance_id, - const DeviceRRGSB& device_rr_gsb, const RRGraphView& rr_graph, - const RRGSB& rr_gsb, const FabricTile& fabric_tile, - const FabricTileId& curr_fabric_tile_id, + const ModuleId& tile_module, const vtr::Matrix& tile_instance_ids, + const size_t& tile_instance_id, const DeviceRRGSB& device_rr_gsb, + const RRGraphView& rr_graph, const RRGSB& rr_gsb, + const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const size_t& sb_idx_in_curr_fabric_tile, - const bool& compact_routing_hierarchy, - const bool& verbose) { + const bool& compact_routing_hierarchy, const bool& verbose) { /* We could have two different coordinators, one is the instance, the other is * the module */ vtr::Point instance_sb_coordinate(rr_gsb.get_sb_x(), rr_gsb.get_sb_y()); vtr::Point module_gsb_sb_coordinate(rr_gsb.get_x(), rr_gsb.get_y()); - vtr::Point sb_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); - FabricTileId sb_unique_tile = fabric_tile.unique_tile(curr_fabric_tile_id); - vtr::Point sb_coord_in_unique_tile = fabric_tile.sb_coordinates(sb_unique_tile)[sb_idx_in_curr_fabric_tile]; + vtr::Point sb_tile_coord = + fabric_tile.tile_coordinate(curr_fabric_tile_id); + FabricTileId sb_unique_tile = fabric_tile.unique_tile(sb_tile_coord); + vtr::Point sb_coord_in_unique_tile = + fabric_tile.sb_coordinates(sb_unique_tile)[sb_idx_in_curr_fabric_tile]; std::string sb_instance_name_in_unique_tile = generate_switch_block_module_name(sb_coord_in_unique_tile); @@ -774,50 +804,53 @@ static int build_top_module_tile_nets_between_sb_and_cb( instance_cb.get_cb_y(cb_type)); /* Check if the grid is inside the tile, if not, create ports */ - if (fabric_tile.cb_in_tile(fabric_tile_id, cb_type, + if (fabric_tile.cb_in_tile(curr_fabric_tile_id, cb_type, instance_cb_coordinate)) { continue; } /* Collect cb tile information */ - FabricTileId cb_tile = fabric_tile.find_tile_by_cb_coordinate(cb_type, instance_gsb_cb_coordinate); - vtr::Point cb_tile_coord = fabric_tile.tile_coordindate(cb_tile); - size_t cb_idx_in_cb_tile = fabric_tile.find_cb_index_in_tile(cb_tile, cb_type, instance_gsb_cb_coordinate); + FabricTileId cb_tile = fabric_tile.find_tile_by_cb_coordinate( + cb_type, instance_gsb_cb_coordinate); + vtr::Point cb_tile_coord = fabric_tile.tile_coordinate(cb_tile); + size_t cb_idx_in_cb_tile = fabric_tile.find_cb_index_in_tile( + cb_tile, cb_type, instance_gsb_cb_coordinate); FabricTileId cb_unique_tile = fabric_tile.unique_tile(cb_tile_coord); - vtr::Point cb_unique_tile_coord = fabric_tile.tile_coordindate(cb_unique_tile); - vtr::Point cb_coord_in_cb_unique_tile = fabric_tile.cb_coordinates(cb_unique_tile, cb_type)[cb_idx_in_cb_tile]; + vtr::Point cb_unique_tile_coord = + fabric_tile.tile_coordinate(cb_unique_tile); + vtr::Point cb_coord_in_cb_unique_tile = + fabric_tile.cb_coordinates(cb_unique_tile, cb_type)[cb_idx_in_cb_tile]; std::string cb_instance_name_in_unique_tile = - generate_connection_block_module_name(cb_type, cb_coord_in_cb_unique_tile); + generate_connection_block_module_name(cb_type, + cb_coord_in_cb_unique_tile); std::string cb_tile_module_name = generate_tile_module_name(cb_unique_tile_coord); - ModuleId cb_tile_module = - module_manager.find_module(cb_tile_module_name); + ModuleId cb_tile_module = module_manager.find_module(cb_tile_module_name); VTR_ASSERT(true == module_manager.valid_module_id(cb_tile_module)); size_t cb_tile_instance = tile_instance_ids[cb_tile_coord.x()][cb_tile_coord.y()]; /* Create nets */ for (size_t itrack = 0; - itrack < module_sb.get_chan_width(side_manager.get_side()); - ++itrack) { + itrack < module_sb.get_chan_width(side_manager.get_side()); ++itrack) { std::string sb_port_name = generate_sb_module_track_port_name( rr_graph.node_type( module_sb.get_chan_node(side_manager.get_side(), itrack)), side_manager.get_side(), module_sb.get_chan_node_direction(side_manager.get_side(), itrack)); /* Prepare SB-related port information */ - std::string sb_tile_sb_port_name = generate_tile_module_port_name(sb_instance_name_in_unique_tile, sb_port_name); + std::string sb_tile_sb_port_name = generate_tile_module_port_name( + sb_instance_name_in_unique_tile, sb_port_name); ModulePortId sb_port_id = module_manager.find_module_port(tile_module, sb_tile_sb_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(tile_module, - sb_port_id)); - BasicPort sb_port = - module_manager.module_port(tile_module, sb_port_id); + VTR_ASSERT(true == + module_manager.valid_module_port_id(tile_module, sb_port_id)); + BasicPort sb_port = module_manager.module_port(tile_module, sb_port_id); /* Prepare CB-related port information */ PORTS cb_port_direction = OUT_PORT; /* The cb port direction should be opposite to the sb port !!! */ - if (OUT_PORT == module_sb.get_chan_node_direction( - side_manager.get_side(), itrack)) { + if (OUT_PORT == + module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { cb_port_direction = IN_PORT; } else { VTR_ASSERT(IN_PORT == module_sb.get_chan_node_direction( @@ -828,11 +861,12 @@ static int build_top_module_tile_nets_between_sb_and_cb( * right sides of the switch block, which indicated bottom and left * sides of the connection blocks */ - bool use_cb_upper_port = (TOP == side_manager.get_side()) || - (RIGHT == side_manager.get_side()); + bool use_cb_upper_port = + (TOP == side_manager.get_side()) || (RIGHT == side_manager.get_side()); std::string cb_port_name = generate_cb_module_track_port_name( cb_type, cb_port_direction, use_cb_upper_port); - std::string cb_tile_cb_port_name = generate_tile_module_port_name(cb_instance_name_in_unique_tile, cb_port_name); + std::string cb_tile_cb_port_name = generate_tile_module_port_name( + cb_instance_name_in_unique_tile, cb_port_name); ModulePortId cb_port_id = module_manager.find_module_port(cb_tile_module, cb_tile_cb_port_name); VTR_ASSERT(true == module_manager.valid_module_port_id(cb_tile_module, @@ -844,11 +878,11 @@ static int build_top_module_tile_nets_between_sb_and_cb( * If sb port is an output (source), cb port is an input (sink) * If sb port is an input (sink), cb port is an output (source) */ - if (OUT_PORT == module_sb.get_chan_node_direction( - side_manager.get_side(), itrack)) { + if (OUT_PORT == + module_sb.get_chan_node_direction(side_manager.get_side(), itrack)) { ModuleNetId net = create_module_source_pin_net( - module_manager, top_module, tile_module, tile_instance_id, - sb_port_id, itrack / 2); + module_manager, top_module, tile_module, tile_instance_id, sb_port_id, + itrack / 2); module_manager.add_module_net_sink(top_module, net, cb_tile_module, cb_tile_instance, cb_port_id, itrack / 2); @@ -869,8 +903,10 @@ static int build_top_module_tile_nets_between_sb_and_cb( /******************************************************************** * Add module nets to connect the pins between tiles - * To make it easy, this function will iterate over all the tiles, through which we can obtain the coordinates - * of each programmable block (PB), connection block (CB) and switch block (SB). With the coordinates, we can then trace the connections between these blocks using the RRGSB data structure. + * To make it easy, this function will iterate over all the tiles, through which + *we can obtain the coordinates of each programmable block (PB), connection + *block (CB) and switch block (SB). With the coordinates, we can then trace the + *connections between these blocks using the RRGSB data structure. * * +--------+ +----------+ * | Tile |--->| Tile | @@ -878,17 +914,26 @@ static int build_top_module_tile_nets_between_sb_and_cb( * +--------+ +----------+ * * The inter-tile connections can be categorized into four types: - * - PB-to-SB connections: We use the GSB to find the connections with a given SB coordinate. Note that we only care the connections where the driver PB is not in this tile. - * - CB-to-PB connections: We use the GSB to find the connections with a given CB coordinate. Note that we only care the connections where the sink PB is not in this tile. - * - SB-to-CB connections: We use the GSB to find the connections with a given SB coordinate. Note that we only care the connections where the sink CB is not in this tile. - * - PB-to-PB connections: We use the tile direct data structure to find all the connections. Note that we only care the connections where the driver PB is not in this tile. + * - PB-to-SB connections: We use the GSB to find the connections with a given + *SB coordinate. Note that we only care the connections where the driver PB is + *not in this tile. + * - CB-to-PB connections: We use the GSB to find the connections with a given + *CB coordinate. Note that we only care the connections where the sink PB is not + *in this tile. + * - SB-to-CB connections: We use the GSB to find the connections with a given + *SB coordinate. Note that we only care the connections where the sink CB is not + *in this tile. + * - PB-to-PB connections: We use the tile direct data structure to find all the + *connections. Note that we only care the connections where the driver PB is not + *in this tile. * *******************************************************************/ static int add_top_module_nets_around_one_tile( ModuleManager& module_manager, const ModuleId& top_module, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const vtr::Matrix& tile_instance_ids, const RRGraphView& rr_graph, - const DeviceRRGSB& device_rr_gsb, const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, + const vtr::Matrix& tile_instance_ids, + const RRGraphView& rr_graph_view, const DeviceRRGSB& device_rr_gsb, + const FabricTile& fabric_tile, const FabricTileId& curr_fabric_tile_id, const bool& verbose) { int status = CMD_EXEC_SUCCESS; @@ -900,22 +945,25 @@ static int add_top_module_nets_around_one_tile( if (!module_manager.valid_module_id(tile_module)) { return CMD_EXEC_FATAL_ERROR; } - + /* Find the instance id for this tile */ - vtr::Point tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); + vtr::Point tile_coord = + fabric_tile.tile_coordinate(curr_fabric_tile_id); size_t tile_instance_id = tile_instance_ids[tile_coord.x()][tile_coord.y()]; /* Get the submodule of Switch blocks one by one, build connections between sb * and pb */ - for (size_t isb = 0; isb < fabric_tile.sb_coordinates(fabric_tile_id).size(); - ++isb) { + for (size_t isb = 0; + isb < fabric_tile.sb_coordinates(curr_fabric_tile_id).size(); ++isb) { vtr::Point sb_coord = - fabric_tile.sb_coordinates(fabric_tile_id)[isb]; + fabric_tile.sb_coordinates(curr_fabric_tile_id)[isb]; const RRGSB& rr_gsb = device_rr_gsb.get_gsb(sb_coord); - status_code = build_top_module_tile_nets_between_sb_and_pb( - module_manager, top_module, tile_module, tile_instance_ids, tile_instance_id, grids, vpr_device_annotation, device_rr_gsb, - rr_graph_view, rr_gsb, fabric_tile, curr_fabric_tile_id, isb, true, verbose); - if (status_code != CMD_EXEC_SUCCESS) { + status = build_top_module_tile_nets_between_sb_and_pb( + module_manager, top_module, tile_module, tile_instance_ids, + tile_instance_id, grids, vpr_device_annotation, device_rr_gsb, + rr_graph_view, rr_gsb, fabric_tile, curr_fabric_tile_id, isb, true, + verbose); + if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } } @@ -923,35 +971,33 @@ static int add_top_module_nets_around_one_tile( * between cb and pb */ for (t_rr_type cb_type : {CHANX, CHANY}) { for (size_t icb = 0; - icb < fabric_tile.cb_coordinates(fabric_tile_id, cb_type).size(); + icb < fabric_tile.cb_coordinates(curr_fabric_tile_id, cb_type).size(); ++icb) { vtr::Point cb_coord = - fabric_tile.cb_coordinates(fabric_tile_id, cb_type)[icb]; + fabric_tile.cb_coordinates(curr_fabric_tile_id, cb_type)[icb]; const RRGSB& rr_gsb = device_rr_gsb.get_gsb(cb_coord); - status_code = build_top_module_tile_nets_between_cb_and_pb( - module_manager, top_module, tile_module, tile_instance_ids, tile_instance_id, - grids, vpr_device_annotation, - device_rr_gsb, rr_graph_view, rr_gsb, - fabric_tile, curr_fabric_tile_id, - cb_type, icb, true, - verbose); - if (status_code != CMD_EXEC_SUCCESS) { + status = build_top_module_tile_nets_between_cb_and_pb( + module_manager, top_module, tile_module, tile_instance_ids, + tile_instance_id, grids, vpr_device_annotation, device_rr_gsb, + rr_graph_view, rr_gsb, fabric_tile, curr_fabric_tile_id, cb_type, icb, + true, verbose); + if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } } } /* Get the submodule of connection blocks one by one, build connections * between sb and cb */ - for (size_t isb = 0; isb < fabric_tile.sb_coordinates(fabric_tile_id).size(); - ++isb) { + for (size_t isb = 0; + isb < fabric_tile.sb_coordinates(curr_fabric_tile_id).size(); ++isb) { vtr::Point sb_coord = - fabric_tile.sb_coordinates(fabric_tile_id)[isb]; + fabric_tile.sb_coordinates(curr_fabric_tile_id)[isb]; const RRGSB& rr_gsb = device_rr_gsb.get_gsb(sb_coord); - status_code = build_top_module_tile_nets_between_sb_and_cb( - module_manager, top_module, tile_module, tile_instance_ids, tile_instance_id, device_rr_gsb, rr_graph_view, rr_gsb, - fabric_tile, curr_fabric_tile_id, isb, true, - verbose); - if (status_code != CMD_EXEC_SUCCESS) { + status = build_top_module_tile_nets_between_sb_and_cb( + module_manager, top_module, tile_module, tile_instance_ids, + tile_instance_id, device_rr_gsb, rr_graph_view, rr_gsb, fabric_tile, + curr_fabric_tile_id, isb, true, verbose); + if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } } @@ -960,7 +1006,8 @@ static int add_top_module_nets_around_one_tile( } /******************************************************************** - * Walk through each tile instance and add module nets to connect the pins between tiles + * Walk through each tile instance and add module nets to connect the pins + *between tiles *******************************************************************/ static int add_top_module_nets_connect_tiles( ModuleManager& module_manager, const ModuleId& top_module, @@ -980,7 +1027,8 @@ static int add_top_module_nets_connect_tiles( } status = add_top_module_nets_around_one_tile( module_manager, top_module, vpr_device_annotation, grids, - tile_instance_ids, rr_graph, device_rr_gsb, fabric_tile, curr_fabric_tile_id, verbose); + tile_instance_ids, rr_graph, device_rr_gsb, fabric_tile, + curr_fabric_tile_id, verbose); if (status != CMD_EXEC_SUCCESS) { return CMD_EXEC_FATAL_ERROR; } @@ -996,7 +1044,7 @@ static int add_top_module_nets_connect_tiles( * +-----------------------> Tail * +<----------------------+ * | - * ... + * ... * +---------------------->+ * +<----------------------+ * head ----------------------->+ @@ -1005,8 +1053,7 @@ static void organize_top_module_tile_based_memory_modules( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, const DeviceGrid& grids, - const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile) { /* Ensure clean vectors to return */ VTR_ASSERT(true == module_manager.configurable_children(top_module).empty()); @@ -1034,18 +1081,21 @@ static void organize_top_module_tile_based_memory_modules( if (!fabric_tile.valid_tile_id(curr_fabric_tile_id)) { continue; } - vtr::Point curr_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); - vtr::Point unique_tile_coord = fabric_tile.unique_tile_coordinate(curr_fabric_tile_id); + vtr::Point curr_tile_coord = + fabric_tile.tile_coordinate(curr_fabric_tile_id); + vtr::Point unique_tile_coord = + fabric_tile.unique_tile_coordinate(curr_fabric_tile_id); std::string tile_module_name = generate_tile_module_name(unique_tile_coord); - ModuleId tile_module = mnodule_manager.find_module(tile_module_name); + ModuleId tile_module = module_manager.find_module(tile_module_name); VTR_ASSERT(module_manager.valid_module_id(tile_module)); - + if (0 < find_module_num_config_bits(module_manager, tile_module, circuit_lib, sram_model, - sram_orgz_type)) { + config_protocol.type())) { module_manager.add_configurable_child( top_module, tile_module, - tile_instance_ids[curr_tile_coord.x()][curr_tile_coord.y()], curr_tile_coord); + tile_instance_ids[curr_tile_coord.x()][curr_tile_coord.y()], + vtr::Point(curr_tile_coord.x(), curr_tile_coord.y())); } } @@ -1060,9 +1110,8 @@ static void organize_top_module_tile_based_memory_modules( ********************************************************************/ ModulePinInfo find_tile_module_chan_port( const ModuleManager& module_manager, const ModuleId& tile_module, - const vtr::Point& cb_coord_in_tile, - const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type, - const RRNodeId& chan_rr_node) { + const vtr::Point& cb_coord_in_tile, const RRGraphView& rr_graph, + const RRGSB& rr_gsb, const t_rr_type& cb_type, const RRNodeId& chan_rr_node) { ModulePinInfo input_port_info; /* Generate the input port object */ switch (rr_graph.node_type(chan_rr_node)) { @@ -1074,7 +1123,9 @@ ModulePinInfo find_tile_module_chan_port( /* Create a port description for the middle output */ std::string input_port_name = generate_cb_module_track_port_name( cb_type, IN_PORT, 0 == chan_node_track_id % 2); - std::string tile_input_port_name = generate_tile_module_port_name(generate_connection_block_module_name(cb_type, cb_coord_in_tile), input_port_name); + std::string tile_input_port_name = generate_tile_module_port_name( + generate_connection_block_module_name(cb_type, cb_coord_in_tile), + input_port_name); /* Must find a valid port id in the Switch Block module */ input_port_info.first = module_manager.find_module_port(tile_module, tile_input_port_name); @@ -1099,8 +1150,7 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( ModuleManager& module_manager, const ModuleId& top_module, const ModulePortId& top_module_port, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, - const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile, + const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk, const std::string& clk_tree_name, const RRClockSpatialLookup& rr_clock_lookup) { int status = CMD_EXEC_SUCCESS; @@ -1150,20 +1200,29 @@ static int build_top_module_global_net_from_tile_clock_arch_tree( const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate( entry_track_type, vtr::Point(entry_point.x(), entry_point.y())); vtr::Point cb_coord_in_tile = rr_gsb.get_sb_coordinate(); - FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_cb_coordinate(entry_track_type, cb_coord_in_tile); - vtr::Point curr_fabric_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); - FabricTileId unique_fabric_tile_id = fabric_tile.unique_tile(curr_fabric_tile_coord); - vtr::Point unique_fabric_tile_coord = fabric_tile.tile_coordinate(unique_fabric_tile_id); - - ModuleId tile_module = module_manager.find_module(generate_tile_module_name(unique_fabric_tile_coord)); - size_t tile_instance = tile_instance_ids[curr_fabric_tile_coord.x()][curr_fabric_tile_coord.y()]; + FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_cb_coordinate( + entry_track_type, cb_coord_in_tile); + vtr::Point curr_fabric_tile_coord = + fabric_tile.tile_coordinate(curr_fabric_tile_id); + FabricTileId unique_fabric_tile_id = + fabric_tile.unique_tile(curr_fabric_tile_coord); + vtr::Point unique_fabric_tile_coord = + fabric_tile.tile_coordinate(unique_fabric_tile_id); + + ModuleId tile_module = module_manager.find_module( + generate_tile_module_name(unique_fabric_tile_coord)); + size_t tile_instance = tile_instance_ids[curr_fabric_tile_coord.x()] + [curr_fabric_tile_coord.y()]; /* Find the port name */ - size_t cb_idx_in_curr_fabric_tile = fabric_tile.find_cb_index_in_tile(curr_fabric_tile_id, entry_track_type, cb_coord_in_tile); - vtr::Point cb_coord_in_unique_fabric_tile = fabric_tile.cb_coordinates(unique_fabric_tile_id, entry_track_type)[cb_idx_in_curr_fabric_tile]; + size_t cb_idx_in_curr_fabric_tile = fabric_tile.find_cb_index_in_tile( + curr_fabric_tile_id, entry_track_type, cb_coord_in_tile); + vtr::Point cb_coord_in_unique_fabric_tile = + fabric_tile.cb_coordinates( + unique_fabric_tile_id, entry_track_type)[cb_idx_in_curr_fabric_tile]; ModulePinInfo des_pin_info = find_tile_module_chan_port( - module_manager, tile_module, cb_coord_in_unique_fabric_tile, rr_graph, rr_gsb, entry_track_type, - entry_rr_node); + module_manager, tile_module, cb_coord_in_unique_fabric_tile, rr_graph, + rr_gsb, entry_track_type, entry_rr_node); /* Configure the net sink */ BasicPort sink_port = @@ -1187,29 +1246,38 @@ static int build_top_module_global_net_for_given_tile_module( const TileGlobalPortId& tile_global_port, const BasicPort& tile_port_to_connect, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const vtr::Point& grid_coordinate, - const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const vtr::Point& grid_coordinate, const e_side& border_side, + const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile) { /* Get the tile module and instance */ - FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); - vtr::Point curr_fabric_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id); - FabricTileId unique_fabric_tile_id = fabric_tile.unique_tile(curr_fabric_tile_coord); - vtr::Point unique_fabric_tile_coord = fabric_tile.tile_coordinate(unique_fabric_tile_id); - std::string tile_module_name = generate_tile_module_name(unique_fabric_tile_coord); + FabricTileId curr_fabric_tile_id = + fabric_tile.find_tile_by_pb_coordinate(grid_coordinate); + vtr::Point curr_fabric_tile_coord = + fabric_tile.tile_coordinate(curr_fabric_tile_id); + FabricTileId unique_fabric_tile_id = + fabric_tile.unique_tile(curr_fabric_tile_coord); + vtr::Point unique_fabric_tile_coord = + fabric_tile.tile_coordinate(unique_fabric_tile_id); + std::string tile_module_name = + generate_tile_module_name(unique_fabric_tile_coord); ModuleId tile_module = module_manager.find_module(tile_module_name); VTR_ASSERT(true == module_manager.valid_module_id(tile_module)); - size_t tile_instance = tile_instance_ids[curr_fabric_tile_coord.x()][curr_fabric_tile_coord.y()]; + size_t tile_instance = + tile_instance_ids[curr_fabric_tile_coord.x()][curr_fabric_tile_coord.y()]; /* Get the grid coordinate in the context of the tile */ - size_t pb_idx_in_curr_fabric_tile = fabric_tile.find_pb_index_in_tile(curr_fabric_tile_id, grid_coordinate); - vtr::Point pb_coord_in_unique_fabric_tile = fabric_tile.pb_coordinates(unique_fabric_tile_id)[pb_idx_in_curr_fabric_tile]; + size_t pb_idx_in_curr_fabric_tile = + fabric_tile.find_pb_index_in_tile(curr_fabric_tile_id, grid_coordinate); + vtr::Point pb_coord_in_unique_fabric_tile = + fabric_tile.pb_coordinates( + unique_fabric_tile_id)[pb_idx_in_curr_fabric_tile]; t_physical_tile_type_ptr physical_tile = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); /* Find the module name for this type of grid */ std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); - std::string grid_instance_name = generate_grid_block_module_name_in_top_module( - grid_module_name_prefix, grids, pb_coord_in_unique_fabric_tile); + std::string grid_instance_name = + generate_grid_block_module_name_in_top_module( + grid_module_name_prefix, grids, pb_coord_in_unique_fabric_tile); /* Find the source port at the top-level module */ BasicPort src_port = module_manager.module_port(top_module, top_module_port); @@ -1287,15 +1355,16 @@ static int build_top_module_global_net_for_given_tile_module( std::string grid_port_name = generate_grid_port_name(grid_pin_width, grid_pin_height, subtile_index, pin_side, grid_pin_info); - std::string tile_grid_port_name = generate_tile_module_port_name(grid_instance_name, grid_port_name); + std::string tile_grid_port_name = + generate_tile_module_port_name(grid_instance_name, grid_port_name); ModulePortId tile_grid_port_id = - module_manager.find_module_port(grid_module, tile_grid_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(tile_module, - tile_port_id)); + module_manager.find_module_port(tile_module, tile_grid_port_name); + VTR_ASSERT(true == module_manager.valid_module_port_id( + tile_module, tile_grid_port_id)); - VTR_ASSERT( - 1 == - module_manager.module_port(tile_module, tile_grid_port_id).get_width()); + VTR_ASSERT(1 == + module_manager.module_port(tile_module, tile_grid_port_id) + .get_width()); ModuleNetId net = create_module_source_pin_net( module_manager, top_module, top_module, 0, top_module_port, @@ -1304,7 +1373,7 @@ static int build_top_module_global_net_for_given_tile_module( /* Configure the net sink */ BasicPort sink_port = - module_manager.module_port(tile_module, tile_port_id); + module_manager.module_port(tile_module, tile_grid_port_id); module_manager.add_module_net_sink(top_module, net, tile_module, tile_instance, tile_grid_port_id, sink_port.pins()[0]); @@ -1324,8 +1393,7 @@ static int build_top_module_global_net_from_tile_modules( const ModulePortId& top_module_port, const TileAnnotation& tile_annotation, const TileGlobalPortId& tile_global_port, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile) { + const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile) { int status = CMD_EXEC_SUCCESS; std::map>> io_coordinates = @@ -1402,7 +1470,8 @@ static int build_top_module_global_net_from_tile_modules( status = build_top_module_global_net_for_given_tile_module( module_manager, top_module, top_module_port, tile_annotation, tile_global_port, tile_port, vpr_device_annotation, grids, - vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, fabric_tile); + vtr::Point(ix, iy), NUM_SIDES, tile_instance_ids, + fabric_tile); if (CMD_EXEC_FATAL_ERROR == status) { return status; } @@ -1469,9 +1538,8 @@ static int add_top_module_global_ports_from_tile_modules( const TileAnnotation& tile_annotation, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, - const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk, - const RRClockSpatialLookup& rr_clock_lookup) { + const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, + const ClockNetwork& clk_ntwk, const RRClockSpatialLookup& rr_clock_lookup) { int status = CMD_EXEC_SUCCESS; /* Add the global ports which are NOT yet added to the top-level module @@ -1527,7 +1595,8 @@ static int add_top_module_global_ports_from_tile_modules( } else { status = build_top_module_global_net_from_tile_modules( module_manager, top_module, top_module_port, tile_annotation, - tile_global_port, vpr_device_annotation, grids, tile_instance_ids, fabric_tile); + tile_global_port, vpr_device_annotation, grids, tile_instance_ids, + fabric_tile); } if (status == CMD_EXEC_FATAL_ERROR) { return status; @@ -1552,10 +1621,9 @@ static void add_module_nets_connect_tile_direct_connection( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile, - const TileDirect& tile_direct, - const TileDirectId& tile_direct_id, const ArchDirect& arch_direct) { + const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, + const TileDirect& tile_direct, const TileDirectId& tile_direct_id, + const ArchDirect& arch_direct) { vtr::Point device_size(grids.width(), grids.height()); std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX); @@ -1564,42 +1632,54 @@ static void add_module_nets_connect_tile_direct_connection( tile_direct.from_tile_coordinate(tile_direct_id); t_physical_tile_type_ptr src_grid_type = grids.get_physical_type(src_clb_coord.x(), src_clb_coord.y()); - FabricTileId src_tile_id = fabric_tile.find_tile_by_pb_coordinate(src_clb_coord); + FabricTileId src_tile_id = + fabric_tile.find_tile_by_pb_coordinate(src_clb_coord); vtr::Point src_tile_coord = fabric_tile.tile_coordinate(src_tile_id); FabricTileId src_unique_tile_id = fabric_tile.unique_tile(src_tile_coord); - vtr::Point src_unique_tile_coord = fabric_tile.tile_coordinate(src_unique_tile_id); - std::string src_module_name = generate_tile_module_name(src_unique_tile_coord); + vtr::Point src_unique_tile_coord = + fabric_tile.tile_coordinate(src_unique_tile_id); + std::string src_module_name = + generate_tile_module_name(src_unique_tile_coord); ModuleId src_tile_module = module_manager.find_module(src_module_name); VTR_ASSERT(true == module_manager.valid_module_id(src_tile_module)); /* Record the instance id */ size_t src_tile_instance = tile_instance_ids[src_tile_coord.x()][src_tile_coord.y()]; /* Grid instance name in the unique tile */ - size_t pb_idx_in_src_tile = fabric_tile.find_pb_index_in_tile(src_tile_id, src_clb_coord); - vtr::Point pb_coord_in_unique_src_tile = fabric_tile.pb_coordinates(src_unique_tile_id)[pb_idx_in_src_tile]; - std::string src_grid_instance_name = generate_grid_block_module_name_in_top_module( - grid_module_name_prefix, grids, pb_coord_in_unique_src_tile); + size_t pb_idx_in_src_tile = + fabric_tile.find_pb_index_in_tile(src_tile_id, src_clb_coord); + vtr::Point pb_coord_in_unique_src_tile = + fabric_tile.pb_coordinates(src_unique_tile_id)[pb_idx_in_src_tile]; + std::string src_grid_instance_name = + generate_grid_block_module_name_in_top_module( + grid_module_name_prefix, grids, pb_coord_in_unique_src_tile); /* Find the module name of sink clb */ vtr::Point des_clb_coord = tile_direct.to_tile_coordinate(tile_direct_id); t_physical_tile_type_ptr sink_grid_type = grids.get_physical_type(des_clb_coord.x(), des_clb_coord.y()); - FabricTileId des_tile_id = fabric_tile.find_tile_by_pb_coordinate(des_clb_coord); + FabricTileId des_tile_id = + fabric_tile.find_tile_by_pb_coordinate(des_clb_coord); vtr::Point des_tile_coord = fabric_tile.tile_coordinate(des_tile_id); FabricTileId des_unique_tile_id = fabric_tile.unique_tile(des_tile_coord); - vtr::Point des_unique_tile_coord = fabric_tile.tile_coordinate(des_unique_tile_id); - std::string des_module_name = generate_tile_module_name(des_unique_tile_coord); + vtr::Point des_unique_tile_coord = + fabric_tile.tile_coordinate(des_unique_tile_id); + std::string des_module_name = + generate_tile_module_name(des_unique_tile_coord); ModuleId des_tile_module = module_manager.find_module(des_module_name); VTR_ASSERT(true == module_manager.valid_module_id(des_tile_module)); /* Record the instance id */ size_t des_tile_instance = tile_instance_ids[des_tile_coord.x()][des_tile_coord.y()]; /* Grid instance name in the unique tile */ - size_t pb_idx_in_des_tile = fabric_tile.find_pb_index_in_tile(des_tile_id, des_clb_coord); - vtr::Point pb_coord_in_unique_des_tile = fabric_tile.pb_coordinates(des_unique_tile_id)[pb_idx_in_des_tile]; - std::string des_grid_instance_name = generate_grid_block_module_name_in_top_module( - grid_module_name_prefix, grids, pb_coord_in_unique_des_tile); + size_t pb_idx_in_des_tile = + fabric_tile.find_pb_index_in_tile(des_tile_id, des_clb_coord); + vtr::Point pb_coord_in_unique_des_tile = + fabric_tile.pb_coordinates(des_unique_tile_id)[pb_idx_in_des_tile]; + std::string des_grid_instance_name = + generate_grid_block_module_name_in_top_module( + grid_module_name_prefix, grids, pb_coord_in_unique_des_tile); /* Find the module id of a direct connection module */ CircuitModelId direct_circuit_model = @@ -1654,14 +1734,15 @@ static void add_module_nets_connect_tile_direct_connection( std::string src_port_name = generate_grid_port_name(src_pin_width, src_pin_height, src_subtile_index, src_pin_grid_side, src_pin_info); - src_port_name = generate_tile_module_port_name(src_grid_instance_name, src_port_name); + src_port_name = + generate_tile_module_port_name(src_grid_instance_name, src_port_name); ModulePortId src_port_id = module_manager.find_module_port(src_tile_module, src_port_name); if (true != module_manager.valid_module_port_id(src_tile_module, src_port_id)) { VTR_LOG_ERROR("Fail to find port '%s[%lu][%lu].%s'\n", - src_module_name.c_str(), src_tile_coord.x(), src_tile_coord.y(), - src_port_name.c_str()); + src_module_name.c_str(), src_tile_coord.x(), + src_tile_coord.y(), src_port_name.c_str()); } VTR_ASSERT(true == module_manager.valid_module_port_id(src_tile_module, src_port_id)); @@ -1690,14 +1771,14 @@ static void add_module_nets_connect_tile_direct_connection( std::string sink_port_name = generate_grid_port_name(sink_pin_width, sink_pin_height, sink_subtile_index, sink_pin_grid_side, sink_pin_info); - sink_port_name = generate_tile_module_port_name(des_grid_instance_name, sink_port_name); + sink_port_name = + generate_tile_module_port_name(des_grid_instance_name, sink_port_name); ModulePortId sink_port_id = module_manager.find_module_port(des_tile_module, sink_port_name); - VTR_ASSERT(true == module_manager.valid_module_port_id(des_tile_module, - sink_port_id)); VTR_ASSERT( - 1 == - module_manager.module_port(des_tile_module, sink_port_id).get_width()); + true == module_manager.valid_module_port_id(des_tile_module, sink_port_id)); + VTR_ASSERT( + 1 == module_manager.module_port(des_tile_module, sink_port_id).get_width()); /* Add a submodule of direct connection module to the top-level module */ size_t direct_instance_id = @@ -1735,10 +1816,8 @@ static void add_top_module_nets_connect_tile_direct_connections( ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, - const vtr::Matrix& tile_instance_ids, - const FabricTile& fabric_tile, - const TileDirect& tile_direct, - const ArchDirect& arch_direct) { + const vtr::Matrix& tile_instance_ids, const FabricTile& fabric_tile, + const TileDirect& tile_direct, const ArchDirect& arch_direct) { vtr::ScopedStartFinishTimer timer( "Add module nets for inter-tile connections"); @@ -1761,11 +1840,9 @@ int build_top_module_tile_child_instances( const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, - const ArchDirect& arch_direct, - const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, - const CircuitModelId& sram_model, - const FabricKey& fabric_key, const bool& frame_view, - const bool& verbose) { + const ArchDirect& arch_direct, const FabricTile& fabric_tile, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, + const FabricKey& fabric_key, const bool& frame_view, const bool& verbose) { int status = CMD_EXEC_SUCCESS; vtr::Matrix tile_instance_ids; status = add_top_module_tile_instances(module_manager, top_module, @@ -1795,11 +1872,13 @@ int build_top_module_tile_child_instances( tile_instance_ids, fabric_tile, tile_direct, arch_direct); } - /* Add global ports from tile modules: how to connect to clock architecture and the global port from tile annotation + /* Add global ports from tile modules: how to connect to clock architecture + * and the global port from tile annotation */ - status = add_top_module_global_ports_from_tile_modules( module_manager, top_module, - tile_annotation, vpr_device_annotation, grids, rr_graph, device_rr_gsb, - tile_instance_ids, fabric_tile, clk_ntwk, rr_clock_lookup); + status = add_top_module_global_ports_from_tile_modules( + module_manager, top_module, tile_annotation, vpr_device_annotation, grids, + rr_graph, device_rr_gsb, tile_instance_ids, fabric_tile, clk_ntwk, + rr_clock_lookup); if (CMD_EXEC_FATAL_ERROR == status) { return status; } diff --git a/openfpga/src/fabric/build_top_module_child_tile_instance.h b/openfpga/src/fabric/build_top_module_child_tile_instance.h index d0b03bb05..02df43e76 100644 --- a/openfpga/src/fabric/build_top_module_child_tile_instance.h +++ b/openfpga/src/fabric/build_top_module_child_tile_instance.h @@ -40,11 +40,9 @@ int build_top_module_tile_child_instances( const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids, const TileAnnotation& tile_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const TileDirect& tile_direct, - const ArchDirect& arch_direct, - const FabricTile& fabric_tile, const ConfigProtocol& config_protocol, - const CircuitModelId& sram_model, - const FabricKey& fabric_key, const bool& frame_view, - const bool& verbose); + const ArchDirect& arch_direct, const FabricTile& fabric_tile, + const ConfigProtocol& config_protocol, const CircuitModelId& sram_model, + const FabricKey& fabric_key, const bool& frame_view, const bool& verbose); } /* end namespace openfpga */ diff --git a/openfpga/src/fabric/build_top_module_memory.cpp b/openfpga/src/fabric/build_top_module_memory.cpp index 74a8713a1..92eef9967 100644 --- a/openfpga/src/fabric/build_top_module_memory.cpp +++ b/openfpga/src/fabric/build_top_module_memory.cpp @@ -262,7 +262,7 @@ static void organize_top_module_tile_memory_modules( * - This function should NOT modify configurable children * *******************************************************************/ -static void build_top_module_configurable_regions( +void build_top_module_configurable_regions( ModuleManager& module_manager, const ModuleId& top_module, const ConfigProtocol& config_protocol) { vtr::ScopedStartFinishTimer timer( diff --git a/openfpga/src/fabric/build_top_module_memory.h b/openfpga/src/fabric/build_top_module_memory.h index 0f4a17d6a..a452588ec 100644 --- a/openfpga/src/fabric/build_top_module_memory.h +++ b/openfpga/src/fabric/build_top_module_memory.h @@ -37,6 +37,10 @@ void organize_top_module_memory_modules( const std::map>& cb_instance_ids, const bool& compact_routing_hierarchy); +void build_top_module_configurable_regions( + ModuleManager& module_manager, const ModuleId& top_module, + const ConfigProtocol& config_protocol); + void shuffle_top_module_configurable_children( ModuleManager& module_manager, const ModuleId& top_module, const ConfigProtocol& config_protocol); diff --git a/openfpga/src/fabric/build_top_module_utils.cpp b/openfpga/src/fabric/build_top_module_utils.cpp index e52ad6519..1fe1bd158 100644 --- a/openfpga/src/fabric/build_top_module_utils.cpp +++ b/openfpga/src/fabric/build_top_module_utils.cpp @@ -11,6 +11,7 @@ /* Module builder headers */ #include "build_top_module_utils.h" +#include "openfpga_rr_graph_utils.h" /* begin namespace openfpga */ namespace openfpga { @@ -46,10 +47,10 @@ std::string generate_grid_block_module_name_in_top_module( * Note that it may be useful for other modules but not tried yet! *******************************************************************/ std::string generate_grid_module_port_name_in_top_module( - const vtr::Point& grid_coordinate, + const DeviceGrid& grids, const vtr::Point& grid_coordinate, const size_t& sink_grid_pin_index, - const VprDeviceAnnotation& vpr_device_annotation, - const RRGraph& rr_graph, const RRNodeId& inode) { + const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, + const RRNodeId& inode) { t_physical_tile_type_ptr grid_type_descriptor = grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y()); size_t sink_grid_pin_width = @@ -66,9 +67,7 @@ std::string generate_grid_module_port_name_in_top_module( subtile_index < grid_type_descriptor->capacity); std::string sink_grid_port_name = generate_grid_port_name( sink_grid_pin_width, sink_grid_pin_height, subtile_index, - get_rr_graph_single_node_side( - rr_graph, rr_gsb.get_ipin_node(cb_ipin_side, inode)), - sink_grid_pin_info); + get_rr_graph_single_node_side(rr_graph, inode), sink_grid_pin_info); return sink_grid_port_name; } diff --git a/openfpga/src/fabric/build_top_module_utils.h b/openfpga/src/fabric/build_top_module_utils.h index 392e9e09d..3a871b3e1 100644 --- a/openfpga/src/fabric/build_top_module_utils.h +++ b/openfpga/src/fabric/build_top_module_utils.h @@ -9,6 +9,7 @@ #include "device_grid.h" #include "rr_gsb.h" +#include "vpr_device_annotation.h" #include "vtr_geometry.h" /******************************************************************** @@ -23,10 +24,10 @@ std::string generate_grid_block_module_name_in_top_module( const vtr::Point& grid_coord); std::string generate_grid_module_port_name_in_top_module( - const vtr::Point& grid_coordinate, + const DeviceGrid& grids, const vtr::Point& grid_coordinate, const size_t& sink_grid_pin_index, - const VprDeviceAnnotation& vpr_device_annotation, - const RRGraph& rr_graph, const RRNodeId& inode); + const VprDeviceAnnotation& vpr_device_annotation, const RRGraphView& rr_graph, + const RRNodeId& inode); t_rr_type find_top_module_cb_type_by_sb_side(const e_side& sb_side);