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[Tool] Now autocheck top testbench consider pin constraints to generate operating clock sources for benchmarks

This commit is contained in:
tangxifan 2021-01-19 17:29:59 -07:00
parent 0670c2de59
commit da200658c1
3 changed files with 82 additions and 26 deletions
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4
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -215,7 +215,9 @@ int fpga_verilog_testbench(const ModuleManager &module_manager,
circuit_lib,
config_protocol,
fabric_global_port_info,
atom_ctx, place_ctx, io_location_map,
atom_ctx, place_ctx,
pin_constraints,
io_location_map,
netlist_annotation,
netlist_name,
top_testbench_file_path,

102
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -482,6 +482,71 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
print_verilog_comment(fp, std::string("----- End connecting global ports of FPGA fabric to stimuli -----"));
}
/********************************************************************
* This function prints the clock ports for all the benchmark clock nets
* It will search the pin constraints to see if a clock is constrained to a specific pin
* If constrained,
* - connect this clock to default values if it is set to be OPEN
* - connect this clock to a specific clock source from simulation settings!!!
* Otherwise,
* - connect this clock to the default clock port
*******************************************************************/
static
void print_verilog_top_testbench_benchmark_clock_ports(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& top_module,
const std::vector<std::string>& clock_port_names,
const PinConstraints& pin_constraints,
const SimulationSetting& simulation_parameters,
const BasicPort& default_clock_port) {
/* Create a clock port if the benchmark have one but not in the default name!
* We will wire the clock directly to the operating clock directly
*/
for (const std::string clock_port_name : clock_port_names) {
if (0 == clock_port_name.compare(default_clock_port.get_name())) {
continue;
}
/* Ensure the clock port name is not a duplication of global ports of the FPGA module */
bool print_clock_port = true;
for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) {
if (0 == clock_port_name.compare(module_port.get_name())) {
print_clock_port = false;
}
}
if (false == print_clock_port) {
continue;
}
BasicPort clock_source_to_connect = default_clock_port;
/* Check pin constraints to see if this clock is constrained to a specific pin
* If constrained,
* - connect this clock to default values if it is set to be OPEN
* - connect this clock to a specific clock source from simulation settings!!!
*/
for (const PinConstraintId& pin_constraint : pin_constraints.pin_constraints()) {
if (clock_port_name != pin_constraints.net(pin_constraint)) {
continue;
}
/* Skip all the unrelated pin constraints */
VTR_ASSERT(clock_port_name == pin_constraints.net(pin_constraint));
/* Try to find which clock source is considered in simulation settings for this pin */
for (const SimulationClockId& sim_clock_id : simulation_parameters.clocks()) {
if (pin_constraints.pin(pin_constraint) == simulation_parameters.clock_port(sim_clock_id)) {
std::string sim_clock_port_name = generate_top_testbench_clock_name(std::string(TOP_TB_OP_CLOCK_PORT_PREFIX), simulation_parameters.clock_name(sim_clock_id));
clock_source_to_connect = BasicPort(sim_clock_port_name, 1);
}
}
}
/* Print the clock and wire it to the clock source */
print_verilog_comment(fp, std::string("----- Create a clock for benchmark and wire it to " + clock_source_to_connect.get_name() + " -------"));
BasicPort clock_port(clock_port_name, 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, clock_port) << ";" << std::endl;
print_verilog_wire_connection(fp, clock_port, clock_source_to_connect, false);
}
}
/********************************************************************
* This function prints the top testbench module declaration
* and internal wires/port declaration
@ -506,6 +571,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
const AtomContext& atom_ctx,
const VprNetlistAnnotation& netlist_annotation,
const std::vector<std::string>& clock_port_names,
const PinConstraints& pin_constraints,
const SimulationSetting& simulation_parameters,
const ConfigProtocol& config_protocol,
const std::string& circuit_name){
@ -598,30 +664,13 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
print_verilog_top_testbench_config_protocol_port(fp, config_protocol,
module_manager, top_module);
/* Create a clock port if the benchmark have one but not in the default name!
* We will wire the clock directly to the operating clock directly
*/
for (const std::string clock_port_name : clock_port_names) {
if (0 == clock_port_name.compare(op_clock_port.get_name())) {
continue;
}
/* Ensure the clock port name is not a duplication of global ports of the FPGA module */
bool print_clock_port = true;
for (const BasicPort& module_port : module_manager.module_ports_by_type(top_module, ModuleManager::MODULE_GLOBAL_PORT)) {
if (0 == clock_port_name.compare(module_port.get_name())) {
print_clock_port = false;
}
}
if (false == print_clock_port) {
continue;
}
/* Print the clock and wire it to op_clock */
print_verilog_comment(fp, std::string("----- Create a clock for benchmark and wire it to op_clock -------"));
BasicPort clock_port(clock_port_name, 1);
fp << "\t" << generate_verilog_port(VERILOG_PORT_WIRE, clock_port) << ";" << std::endl;
print_verilog_wire_connection(fp, clock_port, op_clock_port, false);
}
/* Print clock ports */
print_verilog_top_testbench_benchmark_clock_ports(fp,
module_manager, top_module,
clock_port_names,
pin_constraints,
simulation_parameters,
op_clock_port);
print_verilog_testbench_shared_ports(fp, atom_ctx, netlist_annotation,
clock_port_names,
@ -1841,6 +1890,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const FabricGlobalPortInfo& global_ports,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const PinConstraints& pin_constraints,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,
@ -1893,7 +1943,9 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
/* Start of testbench */
print_verilog_top_testbench_ports(fp, module_manager, top_module,
atom_ctx, netlist_annotation, clock_port_names,
atom_ctx, netlist_annotation,
clock_port_names,
pin_constraints,
simulation_parameters, config_protocol,
circuit_name);

2
openfpga/src/fpga_verilog/verilog_top_testbench.h
View File

@ -12,6 +12,7 @@
#include "circuit_library.h"
#include "config_protocol.h"
#include "vpr_context.h"
#include "pin_constraints.h"
#include "io_location_map.h"
#include "fabric_global_port_info.h"
#include "vpr_netlist_annotation.h"
@ -33,6 +34,7 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
const FabricGlobalPortInfo& global_ports,
const AtomContext& atom_ctx,
const PlacementContext& place_ctx,
const PinConstraints& pin_constraints,
const IoLocationMap& io_location_map,
const VprNetlistAnnotation& netlist_annotation,
const std::string& circuit_name,