diff --git a/docs/source/manual/arch_lang/circuit_model_examples.rst b/docs/source/manual/arch_lang/circuit_model_examples.rst index acc94704c..437cea837 100644 --- a/docs/source/manual/arch_lang/circuit_model_examples.rst +++ b/docs/source/manual/arch_lang/circuit_model_examples.rst @@ -339,10 +339,10 @@ SRAM with BL/WL/WLR ``````````````````` .. _fig_sram_blwlr: -.. figure:: ./figures/sram_blwlr.png +.. figure:: ./figures/sram_blwlr.svg :scale: 100% - An example of a SRAM with Bit-Line (BL) and Word-Line (WL) control signals + An example of a SRAM with Bit-Line (BL), Word-Line (WL) and WL read control signals The following XML codes describes the SRAM cell shown in :numref:`fig_sram_blwlr`. diff --git a/docs/source/manual/arch_lang/figures/sram_blwlr.svg b/docs/source/manual/arch_lang/figures/sram_blwlr.svg new file mode 100644 index 000000000..838dd54ed --- /dev/null +++ b/docs/source/manual/arch_lang/figures/sram_blwlr.svg @@ -0,0 +1,213 @@ + + + + + + + + + + + + + + + + + + + + + Produced by OmniGraffle 7.18.5\n2021-09-21 03:12:41 +0000 + + Canvas 1 + + Layer 1 + + + + + + WL + + + + + BL + + + + + + + + + + + + + + + + + SRAM + + + + + out + + + + + outb + + + + + BL + + + + + WL + + + + + + + + + + + + + + + + + + + + + WLR + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + outb + + + + + + + + + + + out + + + + + + + + + + + + + + + + + + + WLR + + + + + GND + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +