diff --git a/openfpga/src/fabric/build_device_module.cpp b/openfpga/src/fabric/build_device_module.cpp
index 90778f8b7..45c77a050 100644
--- a/openfpga/src/fabric/build_device_module.cpp
+++ b/openfpga/src/fabric/build_device_module.cpp
@@ -164,6 +164,12 @@ int add_fpga_core_to_device_module_graph(ModuleManager& module_manager,
   VTR_LOGV(verbose, "Created a wrapper module '%s' on top of '%s'\n",
            top_module_name.c_str(), core_module_name.c_str());
 
+  /* Now fpga_core should be the only configurable child under the top-level
+   * module */
+  module_manager.add_configurable_child(new_top_module, top_module, 0);
+
+  /* TODO: Update the fabric global ports */
+
   return status;
 }
 
diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
index e4bd1b79c..689a77c89 100644
--- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp
@@ -155,10 +155,22 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx,
    */
   std::string top_block_name = generate_fpga_top_module_name();
   ConfigBlockId top_block = bitstream_manager.add_block(top_block_name);
-  const ModuleId& top_module =
-    openfpga_ctx.module_graph().find_module(top_block_name);
+  ModuleId top_module = openfpga_ctx.module_graph().find_module(top_block_name);
   VTR_ASSERT(true == openfpga_ctx.module_graph().valid_module_id(top_module));
 
+  /* Create the core block when the fpga_core is added */
+  std::string core_block_name = generate_fpga_core_module_name();
+  const ModuleId& core_module =
+    openfpga_ctx.module_graph().find_module(core_block_name);
+  if (openfpga_ctx.module_graph().valid_module_id(core_module)) {
+    ConfigBlockId core_block = bitstream_manager.add_block(core_block_name);
+    bitstream_manager.add_child_block(top_block, core_block);
+    /* Now we use the core_block as the top-level block for the remaining
+     * functions */
+    top_module = core_module;
+    top_block = core_block;
+  }
+
   /* Estimate the number of blocks to be added to the database */
   size_t num_blocks_to_reserve = rec_estimate_device_bitstream_num_blocks(
     openfpga_ctx.module_graph(), top_module);
diff --git a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
index 141237841..b4d526627 100644
--- a/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
+++ b/openfpga/src/fpga_bitstream/build_fabric_bitstream.cpp
@@ -768,17 +768,30 @@ FabricBitstream build_fabric_dependent_bitstream(
   VTR_ASSERT(true == module_manager.valid_module_id(top_module));
 
   /* Find the top block in bitstream manager, which has not parents */
-  std::vector<ConfigBlockId> top_block =
+  std::vector<ConfigBlockId> top_blocks =
     find_bitstream_manager_top_blocks(bitstream_manager);
   /* Make sure we have only 1 top block and its name matches the top module */
-  VTR_ASSERT(1 == top_block.size());
+  VTR_ASSERT(1 == top_blocks.size());
   VTR_ASSERT(
-    0 == top_module_name.compare(bitstream_manager.block_name(top_block[0])));
+    0 == top_module_name.compare(bitstream_manager.block_name(top_blocks[0])));
+  ConfigBlockId top_block = top_blocks[0];
+
+  /* Create the core block when the fpga_core is added */
+  std::string core_block_name = generate_fpga_core_module_name();
+  const ModuleId& core_module = module_manager.find_module(core_block_name);
+  if (module_manager.valid_module_id(core_module)) {
+    /* Now we use the core_block as the top-level block for the remaining
+     * functions */
+    VTR_ASSERT(bitstream_manager.block_children(top_block).size() == 1);
+    ConfigBlockId core_block = bitstream_manager.block_children(top_block)[0];
+    top_module = core_module;
+    top_block = core_block;
+  }
 
   /* Start build-up formally */
   build_module_fabric_dependent_bitstream(
-    config_protocol, circuit_lib, bitstream_manager, top_block[0],
-    module_manager, top_module, fabric_bitstream);
+    config_protocol, circuit_lib, bitstream_manager, top_block, module_manager,
+    top_module, fabric_bitstream);
 
   VTR_LOGV(verbose, "Built %lu configuration bits for fabric\n",
            fabric_bitstream.num_bits());