diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
index 8dbf6a29a..6a4a69e68 100644
--- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadder_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -252,6 +252,12 @@
     <pb_type name="clb.fle[physical].fabric.frac_logic.carry_follower" circuit_model_name="CARRY_MUX2"/>
     <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="SDFFRQ"/>
     <!-- Binding operating pb_type to physical pb_type -->
+    <!-- Binding operating pb_types in mode 'arithmetic' -->
+    <pb_type name="clb.fle[arithmetic].soft_adder.adder_lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1">
+    </pb_type>
+    <pb_type name="clb.fle[arithmetic].soft_adder.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
+    <pb_type name="clb.fle[arithmetic].soft_adder.carry_follower" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.carry_follower"/>
+    <!-- Binding operating pb_types in mode 'n2_lut3' -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->
       <port name="in" physical_mode_port="in[0:2]"/>
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
index b7c308935..89104d53b 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -33,7 +33,15 @@
         <port name="inpad"/>
       </output_ports>
     </model>
-
+    <model name="adder_lut4">
+      <input_ports>
+        <port name="in"/>
+      </input_ports>
+      <output_ports>
+        <port name="lut2_out"/>
+        <port name="lut4_out"/>
+      </output_ports>
+    </model>
     <model name="frac_lut4">
       <input_ports>
         <port name="in"/>
@@ -479,6 +487,59 @@
           </interconnect>
         </mode>
         <!-- Physical mode definition end (physical implementation of the fle) -->
+        <!-- Arithmetic mode definition begin -->
+        <mode name="arithematic">
+          <pb_type name="soft_adder" num_pb="1">
+            <input name="in" num_pins="4"/>
+            <input name="cin" num_pins="1"/>
+            <output name="out" num_pins="1"/>
+            <output name="cout" num_pins="1"/>
+            <clock name="clk" num_pins="1"/>
+            <!-- Define special LUT marco to be used as adder -->
+            <pb_type name="adder_lut4" blif_model=".subckt adder_lut4" num_pb="1">
+              <input name="in" num_pins="4"/>
+              <output name="lut2_out" num_pins="2"/>
+              <output name="lut4_out" num_pins="1"/>
+            </pb_type>
+            <pb_type name="carry_follower" blif_model=".subckt carry_follower" num_pb="1">
+              <input name="a" num_pins="1"/>
+              <input name="b" num_pins="1"/>
+              <input name="cin" num_pins="1"/>
+              <output name="cout" num_pins="1"/>
+            </pb_type>
+            <!-- Define flip-flop -->
+            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
+              <input name="D" num_pins="1" port_class="D"/>
+              <output name="Q" num_pins="1" port_class="Q"/>
+              <clock name="clk" num_pins="1" port_class="clock"/>
+              <T_setup value="66e-12" port="ff.D" clock="clk"/>
+              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
+            </pb_type>
+            <interconnect>
+              <direct name="direct1" input="soft_adder.in[0:1]" output="adder_lut4.in[0:1]"/>
+              <direct name="direct2" input="soft_adder.cin" output="adder_lut4.in[2:2]"/>
+              <direct name="direct3" input="soft_adder.in[3:3]" output="adder_lut4.in[3:3]"/>
+              <direct name="direct4" input="soft_adder.cin" output="carry_follower.b"/>
+              <direct name="direct5" input="adder_lut4.lut2_out[1:1]" output="carry_follower.a"/>
+              <direct name="direct6" input="adder_lut4.lut2_out[0:0]" output="carry_follower.cin"/>
+              <direct name="direct7" input="carry_follower.cout" output="soft_adder.cout"/>
+              <direct name="direct8" input="adder_lut4.lut4_out[0:0]" output="ff[0:0].D">
+              <complete name="complete1" input="soft_adder.clk" output="ff[0:0].clk"/>
+              <mux name="mux1" input="adder_lut4.lut4_out[0:0] ff[0:0].Q" output="soft_adder.out[0:0]">
+                <delay_constant max="25e-12" in_port="adder_lut4.lut4_out[0:0]" out_port="soft_adder.out[0:0]"/>
+                <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="soft_adder.out[0:0]"/>
+              </mux>
+            </interconnect>
+          </pb_type>
+          <interconnect>
+            <direct name="direct1" input="fle.in" output="soft_adder.in"/>
+            <direct name="direct2" input="fle.cin" output="soft_adder.cin"/>
+            <direct name="direct3" input="soft_adder.out" output="fle.out[0:0]"/>
+            <direct name="direct4" input="soft_adder.cout" output="fle.cout"/>
+            <direct name="direct5" input="fle.clk" output="soft_adder.clk"/>
+          </interconnect>
+        </mode>
+        <!-- Arithmetic mode definition end -->
         <!-- Dual 3-LUT mode definition begin -->
         <mode name="n2_lut3">
           <pb_type name="lut3inter" num_pb="1">