From d86eb04c5d540577fa3b9c4643d2c41642923324 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 1 Sep 2022 14:03:51 -0700
Subject: [PATCH] [test] now no timestamp test case covers gsb files

---
 .../no_time_stamp_example_script.openfpga     |   6 +-
 .../and2_include_netlists.v                   |   6 +-
 .../fabric_io_location.xml                    |  39 ++++++
 .../fabric_netlists.v                         |  66 ++++-----
 .../gsb_xml/cbx_0__0_.xml                     |   2 +
 .../gsb_xml/cbx_0__1_.xml                     |   2 +
 .../gsb_xml/cbx_1__0_.xml                     |  90 ++++++++++++
 .../gsb_xml/cbx_1__1_.xml                     |  90 ++++++++++++
 .../gsb_xml/cby_0__1_.xml                     |  82 +++++++++++
 .../gsb_xml/cby_0__2_.xml                     |   2 +
 .../gsb_xml/cby_1__1_.xml                     |  90 ++++++++++++
 .../gsb_xml/cby_1__2_.xml                     |   2 +
 .../gsb_xml/sb_0__0_.xml                      | 132 ++++++++++++++++++
 .../gsb_xml/sb_0__1_.xml                      | 130 +++++++++++++++++
 .../gsb_xml/sb_1__0_.xml                      | 132 ++++++++++++++++++
 .../gsb_xml/sb_1__1_.xml                      | 130 +++++++++++++++++
 .../gsb_xml_no_rr_info/cbx_0__0_.xml          |   2 +
 .../gsb_xml_no_rr_info/cbx_0__1_.xml          |   2 +
 .../gsb_xml_no_rr_info/cbx_1__0_.xml          |  90 ++++++++++++
 .../gsb_xml_no_rr_info/cbx_1__1_.xml          |  90 ++++++++++++
 .../gsb_xml_no_rr_info/cby_0__1_.xml          |  82 +++++++++++
 .../gsb_xml_no_rr_info/cby_0__2_.xml          |   2 +
 .../gsb_xml_no_rr_info/cby_1__1_.xml          |  90 ++++++++++++
 .../gsb_xml_no_rr_info/cby_1__2_.xml          |   2 +
 .../gsb_xml_no_rr_info/sb_0__0_.xml           | 132 ++++++++++++++++++
 .../gsb_xml_no_rr_info/sb_0__1_.xml           | 130 +++++++++++++++++
 .../gsb_xml_no_rr_info/sb_1__0_.xml           | 132 ++++++++++++++++++
 .../gsb_xml_no_rr_info/sb_1__1_.xml           | 130 +++++++++++++++++
 28 files changed, 1848 insertions(+), 37 deletions(-)
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_io_location.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml
 create mode 100644 openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml

diff --git a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
index cd2274b43..609d5fff6 100644
--- a/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/no_time_stamp_example_script.openfpga
@@ -34,7 +34,11 @@ write_fabric_hierarchy --file ./fabric_hierarchy.txt
 
 # Write the fabric I/O attributes to a file
 # This is used by pin constraint files
-write_fabric_io_info --file ./fabric_io_location.xml --verbose --no_time_stamp
+write_fabric_io_info --file ${OPENFPGA_OUTPUT_DIR}/fabric_io_location.xml --verbose --no_time_stamp
+
+# Write gsb to XML
+write_gsb_to_xml --file ${OPENFPGA_OUTPUT_DIR}/gsb_xml --verbose
+write_gsb_to_xml --file ${OPENFPGA_OUTPUT_DIR}/gsb_xml_no_rr_info --verbose --exclude_rr_info
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_include_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_include_netlists.v
index dfbd052c4..3620fd132 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_include_netlists.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_include_netlists.v
@@ -8,9 +8,9 @@
 `timescale 1ns / 1ps
 
 // ------ Include fabric top-level netlists -----
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v"
 
 `include "and2_output_verilog.v"
 
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_top_formal_verification.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_top_formal_verification.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/and2_formal_random_top_tb.v"
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_io_location.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_io_location.xml
new file mode 100644
index 000000000..e7000bde6
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_io_location.xml
@@ -0,0 +1,39 @@
+<!--
+	- FPGA Fabric I/O Information
+	- Generated by OpenFPGA
+-->
+
+<io_coordinates>
+	<io pad="gfpga_pad_GPIO_PAD[24]" x="0" y="1" z="0"/>
+	<io pad="gfpga_pad_GPIO_PAD[25]" x="0" y="1" z="1"/>
+	<io pad="gfpga_pad_GPIO_PAD[26]" x="0" y="1" z="2"/>
+	<io pad="gfpga_pad_GPIO_PAD[27]" x="0" y="1" z="3"/>
+	<io pad="gfpga_pad_GPIO_PAD[28]" x="0" y="1" z="4"/>
+	<io pad="gfpga_pad_GPIO_PAD[29]" x="0" y="1" z="5"/>
+	<io pad="gfpga_pad_GPIO_PAD[30]" x="0" y="1" z="6"/>
+	<io pad="gfpga_pad_GPIO_PAD[31]" x="0" y="1" z="7"/>
+	<io pad="gfpga_pad_GPIO_PAD[16]" x="1" y="0" z="0"/>
+	<io pad="gfpga_pad_GPIO_PAD[17]" x="1" y="0" z="1"/>
+	<io pad="gfpga_pad_GPIO_PAD[18]" x="1" y="0" z="2"/>
+	<io pad="gfpga_pad_GPIO_PAD[19]" x="1" y="0" z="3"/>
+	<io pad="gfpga_pad_GPIO_PAD[20]" x="1" y="0" z="4"/>
+	<io pad="gfpga_pad_GPIO_PAD[21]" x="1" y="0" z="5"/>
+	<io pad="gfpga_pad_GPIO_PAD[22]" x="1" y="0" z="6"/>
+	<io pad="gfpga_pad_GPIO_PAD[23]" x="1" y="0" z="7"/>
+	<io pad="gfpga_pad_GPIO_PAD[0]" x="1" y="2" z="0"/>
+	<io pad="gfpga_pad_GPIO_PAD[1]" x="1" y="2" z="1"/>
+	<io pad="gfpga_pad_GPIO_PAD[2]" x="1" y="2" z="2"/>
+	<io pad="gfpga_pad_GPIO_PAD[3]" x="1" y="2" z="3"/>
+	<io pad="gfpga_pad_GPIO_PAD[4]" x="1" y="2" z="4"/>
+	<io pad="gfpga_pad_GPIO_PAD[5]" x="1" y="2" z="5"/>
+	<io pad="gfpga_pad_GPIO_PAD[6]" x="1" y="2" z="6"/>
+	<io pad="gfpga_pad_GPIO_PAD[7]" x="1" y="2" z="7"/>
+	<io pad="gfpga_pad_GPIO_PAD[8]" x="2" y="1" z="0"/>
+	<io pad="gfpga_pad_GPIO_PAD[9]" x="2" y="1" z="1"/>
+	<io pad="gfpga_pad_GPIO_PAD[10]" x="2" y="1" z="2"/>
+	<io pad="gfpga_pad_GPIO_PAD[11]" x="2" y="1" z="3"/>
+	<io pad="gfpga_pad_GPIO_PAD[12]" x="2" y="1" z="4"/>
+	<io pad="gfpga_pad_GPIO_PAD[13]" x="2" y="1" z="5"/>
+	<io pad="gfpga_pad_GPIO_PAD[14]" x="2" y="1" z="6"/>
+	<io pad="gfpga_pad_GPIO_PAD[15]" x="2" y="1" z="7"/>
+</io_coordinates>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v
index 3bd241f1f..194cfe001 100644
--- a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fabric_netlists.v
@@ -8,46 +8,46 @@
 `timescale 1ns / 1ps
 
 // ------ Include defines: preproc flags -----
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_defines.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_defines.v"
 
 // ------ Include user-defined netlists -----
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/dff.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/openfpga_cell_library/verilog/gpio.v"
 // ------ Include primitive module netlists -----
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/arch_encoder.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/local_encoder.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/mux_primitives.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/muxes.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/luts.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/wires.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/memories.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/inv_buf_passgate.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/arch_encoder.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/local_encoder.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/mux_primitives.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/muxes.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/luts.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/wires.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/memories.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/sub_module/shift_register_banks.v"
 
 // ------ Include logic block netlists -----
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_top.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_right.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_bottom.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_left.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_clb.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_physical__iopad.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_io_mode_io_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__lut4.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4_mode_default__ff.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle_mode_n1_lut4__ble4.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_default__fle.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/logical_tile_clb_mode_clb_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_top.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_right.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_bottom.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_io_left.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/lb/grid_clb.v"
 
 // ------ Include routing module netlists -----
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__0_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__1_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__0_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__1_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__0_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__1_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_0__1_.v"
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_1__1_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__0_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_0__1_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__0_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/sb_1__1_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__0_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cbx_1__1_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_0__1_.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/routing/cby_1__1_.v"
 
 // ------ Include fabric top-level netlists -----
-`include "/home/tangxifan/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_top.v"
+`include "/home/tangxifan/test/OpenFPGA/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/fpga_top.v"
 
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml
new file mode 100644
index 000000000..88ecd4adb
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__0_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="0" y="0" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml
new file mode 100644
index 000000000..e65930df0
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_0__1_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="0" y="1" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml
new file mode 100644
index 000000000..39781ad36
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__0_.xml
@@ -0,0 +1,90 @@
+<rr_cb x="1" y="0" num_sides="4">
+	<IPIN side="top" index="0" node_id="80" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="149" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="150" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="161" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="162" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="173" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="174" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="1" node_id="81" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="149" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="150" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="151" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="152" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="163" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="164" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="2" node_id="82" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="151" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="152" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="153" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="154" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="165" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="166" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="0" node_id="24" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="153" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="154" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="155" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="156" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="167" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="168" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="1" node_id="25" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="155" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="156" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="157" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="158" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="169" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="170" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="2" node_id="26" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="157" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="158" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="159" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="160" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="171" index="22" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="172" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="3" node_id="27" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="159" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="160" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="161" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="162" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="173" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="174" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="4" node_id="28" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="149" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="150" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="161" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="162" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="163" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="164" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="5" node_id="29" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="151" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="152" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="163" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="164" index="15" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="165" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="166" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="6" node_id="30" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="153" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="154" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="165" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="166" index="17" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="167" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="168" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="7" node_id="31" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="155" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="156" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="167" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="168" index="19" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="169" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="170" index="21" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml
new file mode 100644
index 000000000..660956573
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cbx_1__1_.xml
@@ -0,0 +1,90 @@
+<rr_cb x="1" y="1" num_sides="4">
+	<IPIN side="top" index="0" node_id="141" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="175" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="176" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="187" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="188" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="199" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="200" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="1" node_id="142" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="175" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="176" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="177" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="178" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="189" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="190" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="2" node_id="143" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="177" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="178" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="179" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="180" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="191" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="192" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="3" node_id="144" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="179" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="180" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="181" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="182" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="193" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="194" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="4" node_id="145" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="181" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="182" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="183" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="184" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="195" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="196" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="5" node_id="146" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="183" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="184" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="185" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="186" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="197" index="22" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="198" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="6" node_id="147" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="185" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="186" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="187" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="188" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="199" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="200" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="7" node_id="148" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="175" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="176" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="187" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="188" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="189" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="190" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="0" node_id="74" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="177" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="178" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="189" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="190" index="15" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="191" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="192" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="1" node_id="75" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="179" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="180" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="191" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="192" index="17" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="193" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="194" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="2" node_id="76" mux_size="6">
+		<driver_node type="CHANX" side="left" node_id="181" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="182" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="193" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="194" index="19" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="195" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" node_id="196" index="21" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
new file mode 100644
index 000000000..99aadddf5
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__1_.xml
@@ -0,0 +1,82 @@
+<rr_cb x="0" y="1" num_sides="4">
+	<IPIN side="right" index="0" node_id="83" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="1" node_id="84" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="0" node_id="56" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="1" node_id="57" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="2" node_id="58" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="207" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="208" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="221" index="20" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="222" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="3" node_id="59" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="209" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="210" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="223" index="22" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="224" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="4" node_id="60" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="211" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="212" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="225" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="226" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="5" node_id="61" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="201" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="202" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="213" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="214" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="6" node_id="62" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="203" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="204" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="215" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="216" index="15" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="7" node_id="63" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="205" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="206" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="217" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="218" index="17" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="219" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="220" index="19" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml
new file mode 100644
index 000000000..f0437dd4b
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_0__2_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="0" y="2" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
new file mode 100644
index 000000000..eefaf5cd9
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__1_.xml
@@ -0,0 +1,90 @@
+<rr_cb x="1" y="1" num_sides="4">
+	<IPIN side="right" index="0" node_id="109" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="251" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="252" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="1" node_id="110" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="2" node_id="111" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="3" node_id="112" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="4" node_id="113" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="235" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="236" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="247" index="20" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="248" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="5" node_id="114" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="235" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="236" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="237" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="238" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="249" index="22" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="250" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="6" node_id="115" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="237" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="238" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="251" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="252" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="7" node_id="116" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="227" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="228" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="239" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="240" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="0" node_id="77" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="229" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="230" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="241" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="242" index="15" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="1" node_id="78" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="231" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="232" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="243" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="244" index="17" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="2" node_id="79" mux_size="6">
+		<driver_node type="CHANY" side="top" node_id="233" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="234" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="245" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="246" index="19" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="247" index="20" segment_id="0"/>
+		<driver_node type="CHANY" side="top" node_id="248" index="21" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml
new file mode 100644
index 000000000..fe935ebef
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/cby_1__2_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="1" y="2" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml
new file mode 100644
index 000000000..97758d454
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__0_.xml
@@ -0,0 +1,132 @@
+<rr_sb x="0" y="0" num_sides="4">
+	<CHANY side="top" index="0" node_id="201" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="0" node_id="48" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="1" node_id="49" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="7" node_id="55" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="3" node_id="152" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="2" node_id="203" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="1" node_id="49" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="2" node_id="50" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="5" node_id="154" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="4" node_id="205" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="2" node_id="50" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="3" node_id="51" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="7" node_id="156" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="6" node_id="207" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="3" node_id="51" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="4" node_id="52" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="9" node_id="158" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="8" node_id="209" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="4" node_id="52" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="5" node_id="53" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="11" node_id="160" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="10" node_id="211" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="5" node_id="53" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="6" node_id="54" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="13" node_id="162" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="12" node_id="213" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="0" node_id="48" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="6" node_id="54" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="7" node_id="55" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="15" node_id="164" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="14" node_id="215" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="1" node_id="49" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="7" node_id="55" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="17" node_id="166" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="16" node_id="217" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="2" node_id="50" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="8" node_id="73" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_0__pin_O_1_"/>
+		<driver_node type="CHANX" side="right" index="19" node_id="168" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="18" node_id="219" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="3" node_id="51" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="21" node_id="170" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="20" node_id="221" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="4" node_id="52" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="23" node_id="172" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="22" node_id="223" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="5" node_id="53" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="25" node_id="174" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANY side="top" index="24" node_id="225" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="0" node_id="48" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="6" node_id="54" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="right" index="1" node_id="150" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+	</CHANY>
+	<CHANX side="right" index="0" node_id="149" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="25" node_id="226" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="0" node_id="72" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_0_"/>
+		<driver_node type="OPIN" side="right" index="1" node_id="16" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="7" node_id="22" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="2" node_id="151" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="1" node_id="202" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="1" node_id="16" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="2" node_id="17" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="8" node_id="23" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="4" node_id="153" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="3" node_id="204" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="2" node_id="17" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="3" node_id="18" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="6" node_id="155" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="5" node_id="206" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="3" node_id="18" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="4" node_id="19" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="8" node_id="157" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="7" node_id="208" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="4" node_id="19" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="5" node_id="20" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="10" node_id="159" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="9" node_id="210" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="5" node_id="20" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="6" node_id="21" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="12" node_id="161" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="11" node_id="212" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="0" node_id="72" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_0_"/>
+		<driver_node type="OPIN" side="right" index="6" node_id="21" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="7" node_id="22" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="14" node_id="163" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="13" node_id="214" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="1" node_id="16" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="7" node_id="22" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="8" node_id="23" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="16" node_id="165" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="15" node_id="216" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="2" node_id="17" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="8" node_id="23" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="18" node_id="167" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="17" node_id="218" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="3" node_id="18" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="20" node_id="169" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="19" node_id="220" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="4" node_id="19" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="22" node_id="171" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="21" node_id="222" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="5" node_id="20" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="right" index="24" node_id="173" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="CHANY" side="top" index="23" node_id="224" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="right" index="0" node_id="72" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_O_0_"/>
+		<driver_node type="OPIN" side="right" index="6" node_id="21" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANX>
+</rr_sb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml
new file mode 100644
index 000000000..750160da5
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_0__1_.xml
@@ -0,0 +1,130 @@
+<rr_sb x="0" y="1" num_sides="4">
+	<CHANX side="right" index="0" node_id="175" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="0" node_id="133" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="1" node_id="134" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="7" node_id="140" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="22" node_id="223" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="2" node_id="177" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="1" node_id="134" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="2" node_id="135" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="20" node_id="221" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="4" node_id="179" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="2" node_id="135" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="3" node_id="136" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="18" node_id="219" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="6" node_id="181" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="3" node_id="136" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="4" node_id="137" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="16" node_id="217" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="8" node_id="183" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="4" node_id="137" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="5" node_id="138" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="14" node_id="215" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="10" node_id="185" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="5" node_id="138" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="6" node_id="139" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="12" node_id="213" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="12" node_id="187" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="0" node_id="133" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="6" node_id="139" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="7" node_id="140" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="10" node_id="211" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="14" node_id="189" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="1" node_id="134" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="7" node_id="140" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="8" node_id="209" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="16" node_id="191" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="2" node_id="135" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="8" node_id="70" grid_side="top" sb_module_pin_name="right_left_grid_top_width_0_height_0_subtile_0__pin_O_2_"/>
+		<driver_node type="CHANY" side="bottom" index="6" node_id="207" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="18" node_id="193" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="3" node_id="136" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="4" node_id="205" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="20" node_id="195" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="4" node_id="137" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="2" node_id="203" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="22" node_id="197" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="5" node_id="138" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="0" node_id="201" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANX side="right" index="24" node_id="199" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_right_out">
+		<driver_node type="OPIN" side="right" index="0" node_id="133" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="right" index="6" node_id="139" grid_side="bottom" sb_module_pin_name="right_left_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANY" side="bottom" index="24" node_id="225" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+	</CHANX>
+	<CHANY side="bottom" index="1" node_id="202" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="23" node_id="198" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="0" node_id="73" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_0__pin_O_1_"/>
+		<driver_node type="OPIN" side="bottom" index="1" node_id="48" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="7" node_id="54" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="3" node_id="204" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="21" node_id="196" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="1" node_id="48" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="2" node_id="49" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="8" node_id="55" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="5" node_id="206" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="19" node_id="194" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="2" node_id="49" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="3" node_id="50" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="7" node_id="208" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="17" node_id="192" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="3" node_id="50" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="4" node_id="51" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="9" node_id="210" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="15" node_id="190" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="4" node_id="51" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="5" node_id="52" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="11" node_id="212" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="13" node_id="188" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="5" node_id="52" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="6" node_id="53" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="13" node_id="214" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="11" node_id="186" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="6" node_id="53" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="7" node_id="54" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="15" node_id="216" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="9" node_id="184" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="1" node_id="48" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="7" node_id="54" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="8" node_id="55" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="17" node_id="218" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="7" node_id="182" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="2" node_id="49" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="8" node_id="55" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="19" node_id="220" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="5" node_id="180" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="3" node_id="50" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_2__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="21" node_id="222" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="3" node_id="178" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="4" node_id="51" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="23" node_id="224" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="1" node_id="176" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="5" node_id="52" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANY>
+	<CHANY side="bottom" index="25" node_id="226" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="CHANX" side="right" index="25" node_id="200" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_right_in"/>
+		<driver_node type="OPIN" side="bottom" index="6" node_id="53" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANY>
+</rr_sb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml
new file mode 100644
index 000000000..22e827258
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__0_.xml
@@ -0,0 +1,132 @@
+<rr_sb x="1" y="0" num_sides="4">
+	<CHANY side="top" index="0" node_id="227" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="0" node_id="71" grid_side="right" sb_module_pin_name="top_bottom_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
+		<driver_node type="OPIN" side="top" index="1" node_id="101" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="7" node_id="107" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="0" node_id="149" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="2" node_id="229" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="1" node_id="101" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="2" node_id="102" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="8" node_id="108" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="24" node_id="173" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="4" node_id="231" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="2" node_id="102" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="3" node_id="103" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="22" node_id="171" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="6" node_id="233" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="3" node_id="103" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="4" node_id="104" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="20" node_id="169" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="8" node_id="235" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="4" node_id="104" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="5" node_id="105" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="18" node_id="167" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="10" node_id="237" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="5" node_id="105" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="6" node_id="106" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="16" node_id="165" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="12" node_id="239" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="6" node_id="106" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="7" node_id="107" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="14" node_id="163" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="14" node_id="241" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="1" node_id="101" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="7" node_id="107" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="8" node_id="108" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="12" node_id="161" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="16" node_id="243" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="2" node_id="102" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="top" index="8" node_id="108" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="10" node_id="159" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="18" node_id="245" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="3" node_id="103" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="8" node_id="157" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="20" node_id="247" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="4" node_id="104" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="6" node_id="155" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="22" node_id="249" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="5" node_id="105" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="4" node_id="153" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="top" index="24" node_id="251" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_top_out">
+		<driver_node type="OPIN" side="top" index="6" node_id="106" grid_side="left" sb_module_pin_name="top_bottom_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="2" node_id="151" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANX side="left" index="1" node_id="150" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="1" node_id="228" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="0" node_id="72" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_0_"/>
+		<driver_node type="OPIN" side="left" index="1" node_id="16" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="7" node_id="22" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="3" node_id="152" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="25" node_id="252" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="1" node_id="16" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="2" node_id="17" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="8" node_id="23" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="5" node_id="154" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="23" node_id="250" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="2" node_id="17" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="3" node_id="18" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="7" node_id="156" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="21" node_id="248" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="3" node_id="18" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="4" node_id="19" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="9" node_id="158" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="19" node_id="246" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="4" node_id="19" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="5" node_id="20" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="11" node_id="160" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="17" node_id="244" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="5" node_id="20" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="6" node_id="21" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="13" node_id="162" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="15" node_id="242" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="0" node_id="72" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_0_"/>
+		<driver_node type="OPIN" side="left" index="6" node_id="21" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="7" node_id="22" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="15" node_id="164" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="13" node_id="240" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="1" node_id="16" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="7" node_id="22" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="8" node_id="23" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="17" node_id="166" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="11" node_id="238" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="2" node_id="17" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="8" node_id="23" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="19" node_id="168" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="9" node_id="236" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="3" node_id="18" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_2__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="21" node_id="170" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="7" node_id="234" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="4" node_id="19" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="23" node_id="172" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="5" node_id="232" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="5" node_id="20" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="25" node_id="174" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="top" index="3" node_id="230" segment_id="0" segment_name="L4" sb_module_pin_name="chany_top_in"/>
+		<driver_node type="OPIN" side="left" index="0" node_id="72" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_O_0_"/>
+		<driver_node type="OPIN" side="left" index="6" node_id="21" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANX>
+</rr_sb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml
new file mode 100644
index 000000000..483099103
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml/sb_1__1_.xml
@@ -0,0 +1,130 @@
+<rr_sb x="1" y="1" num_sides="4">
+	<CHANY side="bottom" index="1" node_id="228" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="0" node_id="101" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="1" node_id="102" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="7" node_id="108" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="2" node_id="177" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="3" node_id="230" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="1" node_id="102" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="2" node_id="103" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="4" node_id="179" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="5" node_id="232" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="2" node_id="103" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="3" node_id="104" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="6" node_id="181" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="7" node_id="234" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="3" node_id="104" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="4" node_id="105" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="8" node_id="183" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="9" node_id="236" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="4" node_id="105" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="5" node_id="106" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="10" node_id="185" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="11" node_id="238" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="5" node_id="106" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="6" node_id="107" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="12" node_id="187" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="13" node_id="240" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="0" node_id="101" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="6" node_id="107" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="7" node_id="108" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="14" node_id="189" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="15" node_id="242" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="1" node_id="102" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="7" node_id="108" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_7__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="16" node_id="191" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="17" node_id="244" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="2" node_id="103" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="8" node_id="71" grid_side="right" sb_module_pin_name="bottom_top_grid_right_width_0_height_0_subtile_0__pin_O_3_"/>
+		<driver_node type="CHANX" side="left" index="18" node_id="193" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="19" node_id="246" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="3" node_id="104" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="20" node_id="195" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="21" node_id="248" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="4" node_id="105" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="22" node_id="197" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="23" node_id="250" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="5" node_id="106" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="24" node_id="199" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANY side="bottom" index="25" node_id="252" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chany_bottom_out">
+		<driver_node type="OPIN" side="bottom" index="0" node_id="101" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="bottom" index="6" node_id="107" grid_side="left" sb_module_pin_name="bottom_top_grid_left_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="CHANX" side="left" index="0" node_id="175" segment_id="0" segment_name="L4" sb_module_pin_name="chanx_left_in"/>
+	</CHANY>
+	<CHANX side="left" index="1" node_id="176" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="24" node_id="251" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="0" node_id="133" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="1" node_id="134" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="7" node_id="140" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="3" node_id="178" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="0" node_id="227" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="1" node_id="134" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="2" node_id="135" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="5" node_id="180" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="2" node_id="229" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="2" node_id="135" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="3" node_id="136" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="7" node_id="182" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="4" node_id="231" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="3" node_id="136" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="4" node_id="137" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="9" node_id="184" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="6" node_id="233" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="4" node_id="137" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="5" node_id="138" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="11" node_id="186" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="8" node_id="235" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="5" node_id="138" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="6" node_id="139" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="13" node_id="188" segment_id="0" segment_name="L4" mux_size="4" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="10" node_id="237" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="0" node_id="133" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="6" node_id="139" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="7" node_id="140" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="15" node_id="190" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="12" node_id="239" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="1" node_id="134" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_1__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="7" node_id="140" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_7__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="17" node_id="192" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="14" node_id="241" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="2" node_id="135" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_2__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="8" node_id="70" grid_side="top" sb_module_pin_name="left_right_grid_top_width_0_height_0_subtile_0__pin_O_2_"/>
+	</CHANX>
+	<CHANX side="left" index="19" node_id="194" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="16" node_id="243" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="3" node_id="136" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_3__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="21" node_id="196" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="18" node_id="245" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="4" node_id="137" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_4__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="23" node_id="198" segment_id="0" segment_name="L4" mux_size="2" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="20" node_id="247" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="5" node_id="138" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_5__pin_inpad_0_"/>
+	</CHANX>
+	<CHANX side="left" index="25" node_id="200" segment_id="0" segment_name="L4" mux_size="3" sb_module_pin_name="chanx_left_out">
+		<driver_node type="CHANY" side="bottom" index="22" node_id="249" segment_id="0" segment_name="L4" sb_module_pin_name="chany_bottom_in"/>
+		<driver_node type="OPIN" side="left" index="0" node_id="133" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_0__pin_inpad_0_"/>
+		<driver_node type="OPIN" side="left" index="6" node_id="139" grid_side="bottom" sb_module_pin_name="left_right_grid_bottom_width_0_height_0_subtile_6__pin_inpad_0_"/>
+	</CHANX>
+</rr_sb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml
new file mode 100644
index 000000000..88ecd4adb
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__0_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="0" y="0" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml
new file mode 100644
index 000000000..e65930df0
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_0__1_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="0" y="1" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml
new file mode 100644
index 000000000..1bb2753a1
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__0_.xml
@@ -0,0 +1,90 @@
+<rr_cb x="1" y="0" num_sides="4">
+	<IPIN side="top" index="0" mux_size="6">
+		<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="1" mux_size="6">
+		<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="2" mux_size="6">
+		<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="0" mux_size="6">
+		<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="1" mux_size="6">
+		<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="2" mux_size="6">
+		<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="22" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="3" mux_size="6">
+		<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="4" mux_size="6">
+		<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="5" mux_size="6">
+		<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="6" mux_size="6">
+		<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="7" mux_size="6">
+		<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="21" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml
new file mode 100644
index 000000000..aa95d1a45
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cbx_1__1_.xml
@@ -0,0 +1,90 @@
+<rr_cb x="1" y="1" num_sides="4">
+	<IPIN side="top" index="0" mux_size="6">
+		<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="1" mux_size="6">
+		<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="2" mux_size="6">
+		<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="3" mux_size="6">
+		<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="4" mux_size="6">
+		<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="5" mux_size="6">
+		<driver_node type="CHANX" side="left" index="8" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="9" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="22" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="6" mux_size="6">
+		<driver_node type="CHANX" side="left" index="10" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="11" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="24" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="top" index="7" mux_size="6">
+		<driver_node type="CHANX" side="left" index="0" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="1" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="12" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="13" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="0" mux_size="6">
+		<driver_node type="CHANX" side="left" index="2" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="3" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="14" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="15" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="1" mux_size="6">
+		<driver_node type="CHANX" side="left" index="4" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="5" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="16" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="17" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="bottom" index="2" mux_size="6">
+		<driver_node type="CHANX" side="left" index="6" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="7" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="18" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="19" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="20" segment_id="0"/>
+		<driver_node type="CHANX" side="left" index="21" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml
new file mode 100644
index 000000000..5ecb11950
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__1_.xml
@@ -0,0 +1,82 @@
+<rr_cb x="0" y="1" num_sides="4">
+	<IPIN side="right" index="0" mux_size="6">
+		<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="1" mux_size="6">
+		<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="0" mux_size="6">
+		<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="1" mux_size="6">
+		<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="2" mux_size="6">
+		<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="3" mux_size="6">
+		<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="22" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="4" mux_size="6">
+		<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="5" mux_size="6">
+		<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="6" mux_size="6">
+		<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="7" mux_size="6">
+		<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml
new file mode 100644
index 000000000..f0437dd4b
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_0__2_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="0" y="2" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml
new file mode 100644
index 000000000..edec22d72
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__1_.xml
@@ -0,0 +1,90 @@
+<rr_cb x="1" y="1" num_sides="4">
+	<IPIN side="right" index="0" mux_size="6">
+		<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="1" mux_size="6">
+		<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="2" mux_size="6">
+		<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="3" mux_size="6">
+		<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="4" mux_size="6">
+		<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="5" mux_size="6">
+		<driver_node type="CHANY" side="top" index="8" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="9" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="22" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="23" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="6" mux_size="6">
+		<driver_node type="CHANY" side="top" index="10" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="11" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="24" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="25" segment_id="0"/>
+	</IPIN>
+	<IPIN side="right" index="7" mux_size="6">
+		<driver_node type="CHANY" side="top" index="0" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="1" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="12" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="13" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="0" mux_size="6">
+		<driver_node type="CHANY" side="top" index="2" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="3" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="14" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="15" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="1" mux_size="6">
+		<driver_node type="CHANY" side="top" index="4" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="5" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="16" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="17" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
+	</IPIN>
+	<IPIN side="left" index="2" mux_size="6">
+		<driver_node type="CHANY" side="top" index="6" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="7" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="18" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="19" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="20" segment_id="0"/>
+		<driver_node type="CHANY" side="top" index="21" segment_id="0"/>
+	</IPIN>
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml
new file mode 100644
index 000000000..fe935ebef
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/cby_1__2_.xml
@@ -0,0 +1,2 @@
+<rr_cb x="1" y="2" num_sides="4">
+</rr_cb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml
new file mode 100644
index 000000000..e1012a9b1
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__0_.xml
@@ -0,0 +1,132 @@
+<rr_sb x="0" y="0" num_sides="4">
+	<CHANY side="top" index="0" mux_size="4">
+		<driver_node type="OPIN" side="top" index="0"/>
+		<driver_node type="OPIN" side="top" index="1"/>
+		<driver_node type="OPIN" side="top" index="7"/>
+		<driver_node type="CHANX" side="right" index="3"/>
+	</CHANY>
+	<CHANY side="top" index="2" mux_size="3">
+		<driver_node type="OPIN" side="top" index="1"/>
+		<driver_node type="OPIN" side="top" index="2"/>
+		<driver_node type="CHANX" side="right" index="5"/>
+	</CHANY>
+	<CHANY side="top" index="4" mux_size="3">
+		<driver_node type="OPIN" side="top" index="2"/>
+		<driver_node type="OPIN" side="top" index="3"/>
+		<driver_node type="CHANX" side="right" index="7"/>
+	</CHANY>
+	<CHANY side="top" index="6" mux_size="3">
+		<driver_node type="OPIN" side="top" index="3"/>
+		<driver_node type="OPIN" side="top" index="4"/>
+		<driver_node type="CHANX" side="right" index="9"/>
+	</CHANY>
+	<CHANY side="top" index="8" mux_size="3">
+		<driver_node type="OPIN" side="top" index="4"/>
+		<driver_node type="OPIN" side="top" index="5"/>
+		<driver_node type="CHANX" side="right" index="11"/>
+	</CHANY>
+	<CHANY side="top" index="10" mux_size="3">
+		<driver_node type="OPIN" side="top" index="5"/>
+		<driver_node type="OPIN" side="top" index="6"/>
+		<driver_node type="CHANX" side="right" index="13"/>
+	</CHANY>
+	<CHANY side="top" index="12" mux_size="4">
+		<driver_node type="OPIN" side="top" index="0"/>
+		<driver_node type="OPIN" side="top" index="6"/>
+		<driver_node type="OPIN" side="top" index="7"/>
+		<driver_node type="CHANX" side="right" index="15"/>
+	</CHANY>
+	<CHANY side="top" index="14" mux_size="3">
+		<driver_node type="OPIN" side="top" index="1"/>
+		<driver_node type="OPIN" side="top" index="7"/>
+		<driver_node type="CHANX" side="right" index="17"/>
+	</CHANY>
+	<CHANY side="top" index="16" mux_size="3">
+		<driver_node type="OPIN" side="top" index="2"/>
+		<driver_node type="OPIN" side="top" index="8"/>
+		<driver_node type="CHANX" side="right" index="19"/>
+	</CHANY>
+	<CHANY side="top" index="18" mux_size="2">
+		<driver_node type="OPIN" side="top" index="3"/>
+		<driver_node type="CHANX" side="right" index="21"/>
+	</CHANY>
+	<CHANY side="top" index="20" mux_size="2">
+		<driver_node type="OPIN" side="top" index="4"/>
+		<driver_node type="CHANX" side="right" index="23"/>
+	</CHANY>
+	<CHANY side="top" index="22" mux_size="2">
+		<driver_node type="OPIN" side="top" index="5"/>
+		<driver_node type="CHANX" side="right" index="25"/>
+	</CHANY>
+	<CHANY side="top" index="24" mux_size="3">
+		<driver_node type="OPIN" side="top" index="0"/>
+		<driver_node type="OPIN" side="top" index="6"/>
+		<driver_node type="CHANX" side="right" index="1"/>
+	</CHANY>
+	<CHANX side="right" index="0" mux_size="4">
+		<driver_node type="CHANY" side="top" index="25"/>
+		<driver_node type="OPIN" side="right" index="0"/>
+		<driver_node type="OPIN" side="right" index="1"/>
+		<driver_node type="OPIN" side="right" index="7"/>
+	</CHANX>
+	<CHANX side="right" index="2" mux_size="4">
+		<driver_node type="CHANY" side="top" index="1"/>
+		<driver_node type="OPIN" side="right" index="1"/>
+		<driver_node type="OPIN" side="right" index="2"/>
+		<driver_node type="OPIN" side="right" index="8"/>
+	</CHANX>
+	<CHANX side="right" index="4" mux_size="3">
+		<driver_node type="CHANY" side="top" index="3"/>
+		<driver_node type="OPIN" side="right" index="2"/>
+		<driver_node type="OPIN" side="right" index="3"/>
+	</CHANX>
+	<CHANX side="right" index="6" mux_size="3">
+		<driver_node type="CHANY" side="top" index="5"/>
+		<driver_node type="OPIN" side="right" index="3"/>
+		<driver_node type="OPIN" side="right" index="4"/>
+	</CHANX>
+	<CHANX side="right" index="8" mux_size="3">
+		<driver_node type="CHANY" side="top" index="7"/>
+		<driver_node type="OPIN" side="right" index="4"/>
+		<driver_node type="OPIN" side="right" index="5"/>
+	</CHANX>
+	<CHANX side="right" index="10" mux_size="3">
+		<driver_node type="CHANY" side="top" index="9"/>
+		<driver_node type="OPIN" side="right" index="5"/>
+		<driver_node type="OPIN" side="right" index="6"/>
+	</CHANX>
+	<CHANX side="right" index="12" mux_size="4">
+		<driver_node type="CHANY" side="top" index="11"/>
+		<driver_node type="OPIN" side="right" index="0"/>
+		<driver_node type="OPIN" side="right" index="6"/>
+		<driver_node type="OPIN" side="right" index="7"/>
+	</CHANX>
+	<CHANX side="right" index="14" mux_size="4">
+		<driver_node type="CHANY" side="top" index="13"/>
+		<driver_node type="OPIN" side="right" index="1"/>
+		<driver_node type="OPIN" side="right" index="7"/>
+		<driver_node type="OPIN" side="right" index="8"/>
+	</CHANX>
+	<CHANX side="right" index="16" mux_size="3">
+		<driver_node type="CHANY" side="top" index="15"/>
+		<driver_node type="OPIN" side="right" index="2"/>
+		<driver_node type="OPIN" side="right" index="8"/>
+	</CHANX>
+	<CHANX side="right" index="18" mux_size="2">
+		<driver_node type="CHANY" side="top" index="17"/>
+		<driver_node type="OPIN" side="right" index="3"/>
+	</CHANX>
+	<CHANX side="right" index="20" mux_size="2">
+		<driver_node type="CHANY" side="top" index="19"/>
+		<driver_node type="OPIN" side="right" index="4"/>
+	</CHANX>
+	<CHANX side="right" index="22" mux_size="2">
+		<driver_node type="CHANY" side="top" index="21"/>
+		<driver_node type="OPIN" side="right" index="5"/>
+	</CHANX>
+	<CHANX side="right" index="24" mux_size="3">
+		<driver_node type="CHANY" side="top" index="23"/>
+		<driver_node type="OPIN" side="right" index="0"/>
+		<driver_node type="OPIN" side="right" index="6"/>
+	</CHANX>
+</rr_sb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml
new file mode 100644
index 000000000..18eb5f107
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_0__1_.xml
@@ -0,0 +1,130 @@
+<rr_sb x="0" y="1" num_sides="4">
+	<CHANX side="right" index="0" mux_size="4">
+		<driver_node type="OPIN" side="right" index="0"/>
+		<driver_node type="OPIN" side="right" index="1"/>
+		<driver_node type="OPIN" side="right" index="7"/>
+		<driver_node type="CHANY" side="bottom" index="22"/>
+	</CHANX>
+	<CHANX side="right" index="2" mux_size="3">
+		<driver_node type="OPIN" side="right" index="1"/>
+		<driver_node type="OPIN" side="right" index="2"/>
+		<driver_node type="CHANY" side="bottom" index="20"/>
+	</CHANX>
+	<CHANX side="right" index="4" mux_size="3">
+		<driver_node type="OPIN" side="right" index="2"/>
+		<driver_node type="OPIN" side="right" index="3"/>
+		<driver_node type="CHANY" side="bottom" index="18"/>
+	</CHANX>
+	<CHANX side="right" index="6" mux_size="3">
+		<driver_node type="OPIN" side="right" index="3"/>
+		<driver_node type="OPIN" side="right" index="4"/>
+		<driver_node type="CHANY" side="bottom" index="16"/>
+	</CHANX>
+	<CHANX side="right" index="8" mux_size="3">
+		<driver_node type="OPIN" side="right" index="4"/>
+		<driver_node type="OPIN" side="right" index="5"/>
+		<driver_node type="CHANY" side="bottom" index="14"/>
+	</CHANX>
+	<CHANX side="right" index="10" mux_size="3">
+		<driver_node type="OPIN" side="right" index="5"/>
+		<driver_node type="OPIN" side="right" index="6"/>
+		<driver_node type="CHANY" side="bottom" index="12"/>
+	</CHANX>
+	<CHANX side="right" index="12" mux_size="4">
+		<driver_node type="OPIN" side="right" index="0"/>
+		<driver_node type="OPIN" side="right" index="6"/>
+		<driver_node type="OPIN" side="right" index="7"/>
+		<driver_node type="CHANY" side="bottom" index="10"/>
+	</CHANX>
+	<CHANX side="right" index="14" mux_size="3">
+		<driver_node type="OPIN" side="right" index="1"/>
+		<driver_node type="OPIN" side="right" index="7"/>
+		<driver_node type="CHANY" side="bottom" index="8"/>
+	</CHANX>
+	<CHANX side="right" index="16" mux_size="3">
+		<driver_node type="OPIN" side="right" index="2"/>
+		<driver_node type="OPIN" side="right" index="8"/>
+		<driver_node type="CHANY" side="bottom" index="6"/>
+	</CHANX>
+	<CHANX side="right" index="18" mux_size="2">
+		<driver_node type="OPIN" side="right" index="3"/>
+		<driver_node type="CHANY" side="bottom" index="4"/>
+	</CHANX>
+	<CHANX side="right" index="20" mux_size="2">
+		<driver_node type="OPIN" side="right" index="4"/>
+		<driver_node type="CHANY" side="bottom" index="2"/>
+	</CHANX>
+	<CHANX side="right" index="22" mux_size="2">
+		<driver_node type="OPIN" side="right" index="5"/>
+		<driver_node type="CHANY" side="bottom" index="0"/>
+	</CHANX>
+	<CHANX side="right" index="24" mux_size="3">
+		<driver_node type="OPIN" side="right" index="0"/>
+		<driver_node type="OPIN" side="right" index="6"/>
+		<driver_node type="CHANY" side="bottom" index="24"/>
+	</CHANX>
+	<CHANY side="bottom" index="1" mux_size="4">
+		<driver_node type="CHANX" side="right" index="23"/>
+		<driver_node type="OPIN" side="bottom" index="0"/>
+		<driver_node type="OPIN" side="bottom" index="1"/>
+		<driver_node type="OPIN" side="bottom" index="7"/>
+	</CHANY>
+	<CHANY side="bottom" index="3" mux_size="4">
+		<driver_node type="CHANX" side="right" index="21"/>
+		<driver_node type="OPIN" side="bottom" index="1"/>
+		<driver_node type="OPIN" side="bottom" index="2"/>
+		<driver_node type="OPIN" side="bottom" index="8"/>
+	</CHANY>
+	<CHANY side="bottom" index="5" mux_size="3">
+		<driver_node type="CHANX" side="right" index="19"/>
+		<driver_node type="OPIN" side="bottom" index="2"/>
+		<driver_node type="OPIN" side="bottom" index="3"/>
+	</CHANY>
+	<CHANY side="bottom" index="7" mux_size="3">
+		<driver_node type="CHANX" side="right" index="17"/>
+		<driver_node type="OPIN" side="bottom" index="3"/>
+		<driver_node type="OPIN" side="bottom" index="4"/>
+	</CHANY>
+	<CHANY side="bottom" index="9" mux_size="3">
+		<driver_node type="CHANX" side="right" index="15"/>
+		<driver_node type="OPIN" side="bottom" index="4"/>
+		<driver_node type="OPIN" side="bottom" index="5"/>
+	</CHANY>
+	<CHANY side="bottom" index="11" mux_size="3">
+		<driver_node type="CHANX" side="right" index="13"/>
+		<driver_node type="OPIN" side="bottom" index="5"/>
+		<driver_node type="OPIN" side="bottom" index="6"/>
+	</CHANY>
+	<CHANY side="bottom" index="13" mux_size="3">
+		<driver_node type="CHANX" side="right" index="11"/>
+		<driver_node type="OPIN" side="bottom" index="6"/>
+		<driver_node type="OPIN" side="bottom" index="7"/>
+	</CHANY>
+	<CHANY side="bottom" index="15" mux_size="4">
+		<driver_node type="CHANX" side="right" index="9"/>
+		<driver_node type="OPIN" side="bottom" index="1"/>
+		<driver_node type="OPIN" side="bottom" index="7"/>
+		<driver_node type="OPIN" side="bottom" index="8"/>
+	</CHANY>
+	<CHANY side="bottom" index="17" mux_size="3">
+		<driver_node type="CHANX" side="right" index="7"/>
+		<driver_node type="OPIN" side="bottom" index="2"/>
+		<driver_node type="OPIN" side="bottom" index="8"/>
+	</CHANY>
+	<CHANY side="bottom" index="19" mux_size="2">
+		<driver_node type="CHANX" side="right" index="5"/>
+		<driver_node type="OPIN" side="bottom" index="3"/>
+	</CHANY>
+	<CHANY side="bottom" index="21" mux_size="2">
+		<driver_node type="CHANX" side="right" index="3"/>
+		<driver_node type="OPIN" side="bottom" index="4"/>
+	</CHANY>
+	<CHANY side="bottom" index="23" mux_size="2">
+		<driver_node type="CHANX" side="right" index="1"/>
+		<driver_node type="OPIN" side="bottom" index="5"/>
+	</CHANY>
+	<CHANY side="bottom" index="25" mux_size="2">
+		<driver_node type="CHANX" side="right" index="25"/>
+		<driver_node type="OPIN" side="bottom" index="6"/>
+	</CHANY>
+</rr_sb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml
new file mode 100644
index 000000000..fcf4a8552
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__0_.xml
@@ -0,0 +1,132 @@
+<rr_sb x="1" y="0" num_sides="4">
+	<CHANY side="top" index="0" mux_size="4">
+		<driver_node type="OPIN" side="top" index="0"/>
+		<driver_node type="OPIN" side="top" index="1"/>
+		<driver_node type="OPIN" side="top" index="7"/>
+		<driver_node type="CHANX" side="left" index="0"/>
+	</CHANY>
+	<CHANY side="top" index="2" mux_size="4">
+		<driver_node type="OPIN" side="top" index="1"/>
+		<driver_node type="OPIN" side="top" index="2"/>
+		<driver_node type="OPIN" side="top" index="8"/>
+		<driver_node type="CHANX" side="left" index="24"/>
+	</CHANY>
+	<CHANY side="top" index="4" mux_size="3">
+		<driver_node type="OPIN" side="top" index="2"/>
+		<driver_node type="OPIN" side="top" index="3"/>
+		<driver_node type="CHANX" side="left" index="22"/>
+	</CHANY>
+	<CHANY side="top" index="6" mux_size="3">
+		<driver_node type="OPIN" side="top" index="3"/>
+		<driver_node type="OPIN" side="top" index="4"/>
+		<driver_node type="CHANX" side="left" index="20"/>
+	</CHANY>
+	<CHANY side="top" index="8" mux_size="3">
+		<driver_node type="OPIN" side="top" index="4"/>
+		<driver_node type="OPIN" side="top" index="5"/>
+		<driver_node type="CHANX" side="left" index="18"/>
+	</CHANY>
+	<CHANY side="top" index="10" mux_size="3">
+		<driver_node type="OPIN" side="top" index="5"/>
+		<driver_node type="OPIN" side="top" index="6"/>
+		<driver_node type="CHANX" side="left" index="16"/>
+	</CHANY>
+	<CHANY side="top" index="12" mux_size="3">
+		<driver_node type="OPIN" side="top" index="6"/>
+		<driver_node type="OPIN" side="top" index="7"/>
+		<driver_node type="CHANX" side="left" index="14"/>
+	</CHANY>
+	<CHANY side="top" index="14" mux_size="4">
+		<driver_node type="OPIN" side="top" index="1"/>
+		<driver_node type="OPIN" side="top" index="7"/>
+		<driver_node type="OPIN" side="top" index="8"/>
+		<driver_node type="CHANX" side="left" index="12"/>
+	</CHANY>
+	<CHANY side="top" index="16" mux_size="3">
+		<driver_node type="OPIN" side="top" index="2"/>
+		<driver_node type="OPIN" side="top" index="8"/>
+		<driver_node type="CHANX" side="left" index="10"/>
+	</CHANY>
+	<CHANY side="top" index="18" mux_size="2">
+		<driver_node type="OPIN" side="top" index="3"/>
+		<driver_node type="CHANX" side="left" index="8"/>
+	</CHANY>
+	<CHANY side="top" index="20" mux_size="2">
+		<driver_node type="OPIN" side="top" index="4"/>
+		<driver_node type="CHANX" side="left" index="6"/>
+	</CHANY>
+	<CHANY side="top" index="22" mux_size="2">
+		<driver_node type="OPIN" side="top" index="5"/>
+		<driver_node type="CHANX" side="left" index="4"/>
+	</CHANY>
+	<CHANY side="top" index="24" mux_size="2">
+		<driver_node type="OPIN" side="top" index="6"/>
+		<driver_node type="CHANX" side="left" index="2"/>
+	</CHANY>
+	<CHANX side="left" index="1" mux_size="4">
+		<driver_node type="CHANY" side="top" index="1"/>
+		<driver_node type="OPIN" side="left" index="0"/>
+		<driver_node type="OPIN" side="left" index="1"/>
+		<driver_node type="OPIN" side="left" index="7"/>
+	</CHANX>
+	<CHANX side="left" index="3" mux_size="4">
+		<driver_node type="CHANY" side="top" index="25"/>
+		<driver_node type="OPIN" side="left" index="1"/>
+		<driver_node type="OPIN" side="left" index="2"/>
+		<driver_node type="OPIN" side="left" index="8"/>
+	</CHANX>
+	<CHANX side="left" index="5" mux_size="3">
+		<driver_node type="CHANY" side="top" index="23"/>
+		<driver_node type="OPIN" side="left" index="2"/>
+		<driver_node type="OPIN" side="left" index="3"/>
+	</CHANX>
+	<CHANX side="left" index="7" mux_size="3">
+		<driver_node type="CHANY" side="top" index="21"/>
+		<driver_node type="OPIN" side="left" index="3"/>
+		<driver_node type="OPIN" side="left" index="4"/>
+	</CHANX>
+	<CHANX side="left" index="9" mux_size="3">
+		<driver_node type="CHANY" side="top" index="19"/>
+		<driver_node type="OPIN" side="left" index="4"/>
+		<driver_node type="OPIN" side="left" index="5"/>
+	</CHANX>
+	<CHANX side="left" index="11" mux_size="3">
+		<driver_node type="CHANY" side="top" index="17"/>
+		<driver_node type="OPIN" side="left" index="5"/>
+		<driver_node type="OPIN" side="left" index="6"/>
+	</CHANX>
+	<CHANX side="left" index="13" mux_size="4">
+		<driver_node type="CHANY" side="top" index="15"/>
+		<driver_node type="OPIN" side="left" index="0"/>
+		<driver_node type="OPIN" side="left" index="6"/>
+		<driver_node type="OPIN" side="left" index="7"/>
+	</CHANX>
+	<CHANX side="left" index="15" mux_size="4">
+		<driver_node type="CHANY" side="top" index="13"/>
+		<driver_node type="OPIN" side="left" index="1"/>
+		<driver_node type="OPIN" side="left" index="7"/>
+		<driver_node type="OPIN" side="left" index="8"/>
+	</CHANX>
+	<CHANX side="left" index="17" mux_size="3">
+		<driver_node type="CHANY" side="top" index="11"/>
+		<driver_node type="OPIN" side="left" index="2"/>
+		<driver_node type="OPIN" side="left" index="8"/>
+	</CHANX>
+	<CHANX side="left" index="19" mux_size="2">
+		<driver_node type="CHANY" side="top" index="9"/>
+		<driver_node type="OPIN" side="left" index="3"/>
+	</CHANX>
+	<CHANX side="left" index="21" mux_size="2">
+		<driver_node type="CHANY" side="top" index="7"/>
+		<driver_node type="OPIN" side="left" index="4"/>
+	</CHANX>
+	<CHANX side="left" index="23" mux_size="2">
+		<driver_node type="CHANY" side="top" index="5"/>
+		<driver_node type="OPIN" side="left" index="5"/>
+	</CHANX>
+	<CHANX side="left" index="25" mux_size="3">
+		<driver_node type="CHANY" side="top" index="3"/>
+		<driver_node type="OPIN" side="left" index="0"/>
+		<driver_node type="OPIN" side="left" index="6"/>
+	</CHANX>
+</rr_sb>
diff --git a/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml
new file mode 100644
index 000000000..86d1919ea
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/no_time_stamp/golden_outputs_no_time_stamp/gsb_xml_no_rr_info/sb_1__1_.xml
@@ -0,0 +1,130 @@
+<rr_sb x="1" y="1" num_sides="4">
+	<CHANY side="bottom" index="1" mux_size="4">
+		<driver_node type="OPIN" side="bottom" index="0"/>
+		<driver_node type="OPIN" side="bottom" index="1"/>
+		<driver_node type="OPIN" side="bottom" index="7"/>
+		<driver_node type="CHANX" side="left" index="2"/>
+	</CHANY>
+	<CHANY side="bottom" index="3" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="1"/>
+		<driver_node type="OPIN" side="bottom" index="2"/>
+		<driver_node type="CHANX" side="left" index="4"/>
+	</CHANY>
+	<CHANY side="bottom" index="5" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="2"/>
+		<driver_node type="OPIN" side="bottom" index="3"/>
+		<driver_node type="CHANX" side="left" index="6"/>
+	</CHANY>
+	<CHANY side="bottom" index="7" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="3"/>
+		<driver_node type="OPIN" side="bottom" index="4"/>
+		<driver_node type="CHANX" side="left" index="8"/>
+	</CHANY>
+	<CHANY side="bottom" index="9" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="4"/>
+		<driver_node type="OPIN" side="bottom" index="5"/>
+		<driver_node type="CHANX" side="left" index="10"/>
+	</CHANY>
+	<CHANY side="bottom" index="11" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="5"/>
+		<driver_node type="OPIN" side="bottom" index="6"/>
+		<driver_node type="CHANX" side="left" index="12"/>
+	</CHANY>
+	<CHANY side="bottom" index="13" mux_size="4">
+		<driver_node type="OPIN" side="bottom" index="0"/>
+		<driver_node type="OPIN" side="bottom" index="6"/>
+		<driver_node type="OPIN" side="bottom" index="7"/>
+		<driver_node type="CHANX" side="left" index="14"/>
+	</CHANY>
+	<CHANY side="bottom" index="15" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="1"/>
+		<driver_node type="OPIN" side="bottom" index="7"/>
+		<driver_node type="CHANX" side="left" index="16"/>
+	</CHANY>
+	<CHANY side="bottom" index="17" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="2"/>
+		<driver_node type="OPIN" side="bottom" index="8"/>
+		<driver_node type="CHANX" side="left" index="18"/>
+	</CHANY>
+	<CHANY side="bottom" index="19" mux_size="2">
+		<driver_node type="OPIN" side="bottom" index="3"/>
+		<driver_node type="CHANX" side="left" index="20"/>
+	</CHANY>
+	<CHANY side="bottom" index="21" mux_size="2">
+		<driver_node type="OPIN" side="bottom" index="4"/>
+		<driver_node type="CHANX" side="left" index="22"/>
+	</CHANY>
+	<CHANY side="bottom" index="23" mux_size="2">
+		<driver_node type="OPIN" side="bottom" index="5"/>
+		<driver_node type="CHANX" side="left" index="24"/>
+	</CHANY>
+	<CHANY side="bottom" index="25" mux_size="3">
+		<driver_node type="OPIN" side="bottom" index="0"/>
+		<driver_node type="OPIN" side="bottom" index="6"/>
+		<driver_node type="CHANX" side="left" index="0"/>
+	</CHANY>
+	<CHANX side="left" index="1" mux_size="4">
+		<driver_node type="CHANY" side="bottom" index="24"/>
+		<driver_node type="OPIN" side="left" index="0"/>
+		<driver_node type="OPIN" side="left" index="1"/>
+		<driver_node type="OPIN" side="left" index="7"/>
+	</CHANX>
+	<CHANX side="left" index="3" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="0"/>
+		<driver_node type="OPIN" side="left" index="1"/>
+		<driver_node type="OPIN" side="left" index="2"/>
+	</CHANX>
+	<CHANX side="left" index="5" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="2"/>
+		<driver_node type="OPIN" side="left" index="2"/>
+		<driver_node type="OPIN" side="left" index="3"/>
+	</CHANX>
+	<CHANX side="left" index="7" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="4"/>
+		<driver_node type="OPIN" side="left" index="3"/>
+		<driver_node type="OPIN" side="left" index="4"/>
+	</CHANX>
+	<CHANX side="left" index="9" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="6"/>
+		<driver_node type="OPIN" side="left" index="4"/>
+		<driver_node type="OPIN" side="left" index="5"/>
+	</CHANX>
+	<CHANX side="left" index="11" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="8"/>
+		<driver_node type="OPIN" side="left" index="5"/>
+		<driver_node type="OPIN" side="left" index="6"/>
+	</CHANX>
+	<CHANX side="left" index="13" mux_size="4">
+		<driver_node type="CHANY" side="bottom" index="10"/>
+		<driver_node type="OPIN" side="left" index="0"/>
+		<driver_node type="OPIN" side="left" index="6"/>
+		<driver_node type="OPIN" side="left" index="7"/>
+	</CHANX>
+	<CHANX side="left" index="15" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="12"/>
+		<driver_node type="OPIN" side="left" index="1"/>
+		<driver_node type="OPIN" side="left" index="7"/>
+	</CHANX>
+	<CHANX side="left" index="17" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="14"/>
+		<driver_node type="OPIN" side="left" index="2"/>
+		<driver_node type="OPIN" side="left" index="8"/>
+	</CHANX>
+	<CHANX side="left" index="19" mux_size="2">
+		<driver_node type="CHANY" side="bottom" index="16"/>
+		<driver_node type="OPIN" side="left" index="3"/>
+	</CHANX>
+	<CHANX side="left" index="21" mux_size="2">
+		<driver_node type="CHANY" side="bottom" index="18"/>
+		<driver_node type="OPIN" side="left" index="4"/>
+	</CHANX>
+	<CHANX side="left" index="23" mux_size="2">
+		<driver_node type="CHANY" side="bottom" index="20"/>
+		<driver_node type="OPIN" side="left" index="5"/>
+	</CHANX>
+	<CHANX side="left" index="25" mux_size="3">
+		<driver_node type="CHANY" side="bottom" index="22"/>
+		<driver_node type="OPIN" side="left" index="0"/>
+		<driver_node type="OPIN" side="left" index="6"/>
+	</CHANX>
+</rr_sb>